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Agilex ™ 5 FPGAs and SoCs Device Data Sheet

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Agilex ™ 5 FPGAs and SoCs Device Data Sheet

813918 2026.01.05

| Agilex ™ 5 FPGAs and SoCs Device Data Sheet............................................................................................................................ 3 |------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Electrical Characteristics........................................................................................................................................ | Operating Conditions..................................................................................................................................................5 | Switching Characteristics....................................................................................................................................................62 | Core Performance Specifications.................................................................................................................................62 | Periphery Performance Specifications..........................................................................................................................80 | GTS Transceiver Performance Specifications.................................................................................................................96 | HPS Performance Specifications................................................................................................................................107 | Configuration Specifications.............................................................................................................................................. 170 | General Configuration Timing Specifications...............................................................................................................170 | POR Specifications..................................................................................................................................................171 | External Configuration Clock Source Requirements......................................................................................................172 | JTAG Configuration Timing.......................................................................................................................................172 | AS Configuration Timing..........................................................................................................................................173 | Avalon Streaming Configuration Timing..................................................................................................................... 176 | Configuration Bit Stream Sizes.................................................................................................................................177 | I/O Timing........................................................................................................................................................ | Programmable IOE Delay..................................................................................................................................................178 | Glossary.......................................................................................................................................................... | Document Revision History for the Agilex 5 FPGAs and SoCs Device Data Sheet.......................................................................182 | -------------------| .............. 5 | | | | | | | | | | | | | | | ..............178 | | ...............179 | |

Agilex ™ 5 FPGAs and SoCs Device Data Sheet

This data sheet describes the electrical characteristics, switching characteristics, configuration specifications, and timing.

Until the data sheet status for a device reaches Final, the specifications are subject to change at any time and at Altera's discretion.

Table 1. Data Sheet Status for Agilex ™ 5 FPGAs and SoCs

| Devices (1) | Specification | Package | Status | |-----------------------------------------------|-----------------|-----------|-------------| | A5E 008, A5E 013 | A, C | All | Final | | A5E 008, A5E 013 (with CS in optional suffix) | B, D, E | All | Final | | All other devices | All | All | Preliminary |

The following descriptors designate the status level currently applicable to the relevant variant:

Advance: These are target specifications based on simulation.
Preliminary: These specifications are based on simulation, early validation, and/or early characterization data.
Final: These are production specifications based on silicon validation and/or characterization.

(1) Refer to Agilex ™ 5 FPGAs and SoCs Device Overview for details on device ordering part numbers.

© Altera Corporation. Altera, the Altera logo, the 'a' logo, and other Altera marks are trademarks of Altera Corporation. Altera reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

*Other names and brands may be claimed as the property of others.

Table 2. Device Grades, Core Speed Grades, and Power Options Supported

For specification status, see the Data Sheet Status table

| Series | Device Group | Temperature Grade | Speed Grade and Power Option Supported | |----------|----------------|-----------------------|------------------------------------------| | D | A | Extended / Industrial | -1V (fastest) | | D | A | Extended / Industrial | -2V | | D | A | Extended / Industrial | -3V | | E | A | Extended / Industrial | -1V (fastest) | | E | A | Extended / Industrial | -2V | | E | A | Extended / Industrial | -2E | | E | A | Extended / Industrial | -3V | | E | B | Extended / Industrial | -4S (fastest) | | E | B | Extended / Industrial | -5S | | E | B | Extended / Industrial | -6S | | E | B | Extended / Industrial | -6X |

The suffix after the speed grade denotes the power options offered.

V-standard power (VID)
E-low power (VID)
S-standard power (fixed voltage)
X-low power (fixed voltage)

Related Information

Agilex ™ 5 FPGAs and SoCs Device Overview

Electrical Characteristics

Operating Conditions

The devices are rated according to a set of defined parameters. To maintain the highest possible performance and reliability of the devices, you must consider the operating requirements described in this section.

Absolute Maximum Ratings

This section defines the maximum operating conditions. The values are based on experiments conducted with the devices and theoretical modeling of breakdown and damage mechanisms. The functional operation of the device is not implied for these conditions.

Caution:

Conditions outside the range listed in the following table may cause permanent damage to the device. Additionally, device operation at the absolute maximum ratings for extended periods of time may have adverse effects on the device.

Table 3. D-Series FPGAs Absolute Maximum Ratings

For specification status, see the Data Sheet Status table

| Symbol | Description | Condition | Minimum | Maximum | Unit | |--------------|------------------------------------------------|--------------|--------------|--------------|--------------| | V CC | Core voltage supply | - | -0.5 | 1.21 | V | | V CCP | Periphery supply voltage for the I/O banks | - | -0.5 | 1.21 | V | | V CCH_SDM | SDM block transceiver supply voltage sense | - | -0.5 | 1.332 | V | | V CCPT | Power supply for I/O, DTS, SDM, and system PLL | - | -0.5 | 2.08 | V | | V CCRCORE | Power supply for programmable power technology | - | -0.5 | 1.64 | V | | continued... | continued... | continued... | continued... | continued... | continued... |

| Symbol | Description | Condition | Minimum | Maximum | Unit | |-----------------------|-------------------------------------------------------------------------------------------------------------------------|--------------|--------------|--------------|--------------| | V CCBAT (2) | Battery back-up power supply (for design security volatile key register) | - | -0.5 | 2.08 | V | | V CCIO_PIO_SDM | SDM block I/O supply voltage sense of bank 3A | 1.2 V | -0.5 | 1.6 | V | | V CC_IO_SDM | I/O digital supply voltage sense in SDM block | - | -0.5 | 1.21 | V | | V CCIO_SDM | SDM block configuration pins power supply | - | -0.5 | 2.08 | V | | V CCL_ADC_SDM | Periphery digital supply voltage sense to ADC, senses HPS digital supply on HPS devices, core supply on non-HPS devices | - | -0.5 | 1.21 | V | | V CCL_SDM | SDM digital power supply | - | -0.5 | 1.07 | V | | V CC_HSSI_[L1, R4] | Transceiver, system PLL, and hard IP digital power supply | - | -0.5 | 1.07 | V | | V CCPLLDIG_SDM | SDM block PLL digital power supply | - | -0.5 | 1.07 | V | | V CCPLL_SDM | SDM block PLL analog power supply | - | -0.5 | 2.08 | V | | V CCFUSEWR_SDM | Fuse block writing power supply | - | -0.5 | 2.08 | V | | V CCADC | ADC voltage sensor power supply | - | -0.5 | 2.08 | V | | V CCL_HPS | HPS DSU voltage and periphery circuitry power supply | - | -0.5 | 1.21 | V | | V CCL_HPS_CORE0_CORE1 | HPS A55 cores power rail | - | -0.5 | 1.21 | V | | continued... | continued... | continued... | continued... | continued... | continued... |

| Symbol | Description | Condition | Minimum | Maximum | Unit | |---------------------------------|-------------------------------------------------------------------------------------------------------------------|---------------------|-----------|-----------|--------------| | V CCL_HPS_CORE2 | HPS A76 core power rail | - | -0.5 | 1.21 | V | | V CCL_HPS_CORE3 | HPS A76 core power rail | - | -0.5 | 1.21 | V | | V CCPLLDIG1_HPS | HPS PLL1 digital power supply | - | -0.5 | 1.21 | V | | V CCPLLDIG2_HPS | HPS PLL2 digital power supply | - | -0.5 | 1.21 | V | | V CCPLL1_HPS | HPS PLL1 analog power supply | - | -0.5 | 2.08 | V | | V CCPLL2_HPS | HPS PLL2 analog power supply | - | -0.5 | 2.08 | V | | V CCIO_HPS | HPS I/O buffers power supply | - | -0.5 | 2.08 | V | | V CCEHT_GTS[L1, R4][A, B, C, D] | Transceiver PMA, TX PLL, transceiver reference clock, and global reference clock high-voltage analog power supply | - | -0.5 | 2.08 | V | | V CCERT_GTS[L1, R4][A, B, C, D] | Transceiver PMA, transceiver reference clock, and global reference clock low-voltage analog power supply | - | -0.5 | 1.34 | V | | V CCIO_PIO | HSIO bank power supply | V CCIO_PIO = 1.0 V | -0.5 | 1.365 | V | | V CCIO_PIO | HSIO bank power supply | V CCIO_PIO = 1.05 V | -0.5 | 1.43 | V | | V CCIO_PIO | HSIO bank power supply | V CCIO_PIO = 1.1 V | -0.5 | 1.5 | V | | V CCIO_PIO | HSIO bank power supply | V CCIO_PIO = 1.2 V | -0.5 | 1.64 | V | | V CCIO_PIO | HSIO bank power supply | V CCIO_PIO = 1.3 V | -0.5 | 1.74 | V | | V CCIO_HVIO | HVIO bank power supply | V CCIO_HVIO = 3.3 V | -0.5 | 3.74 | V | | V CCIO_HVIO | HVIO bank power supply | V CCIO_HVIO = 2.5 V | -0.5 | 2.83 | V | | V CCIO_HVIO | HVIO bank power supply | V CCIO_HVIO = 1.8 V | -0.5 | 2.04 | V | | | | | | | continued... |

| Symbol | Description | Condition | Minimum | Maximum | Unit | |---------------|------------------------------|---------------------------------------------------------|--------------|------------------------|--------------| | V CCPT_HVIO | Supply voltage for 1.8 V I/O | - | -0.5 | 2.04 | V | | V I | DC input voltage | V CCIO_PIO = 1.0 V (3) (4) | -0.3 | V CCIO_PIO(MAX) + 0.25 | V | | V I | DC input voltage | V CCIO_PIO = 1.05 V (3) (4) | -0.3 | V CCIO_PIO(MAX) + 0.25 | V | | V I | DC input voltage | V CCIO_PIO = 1.1 V (3) (4) | -0.3 | V CCIO_PIO(MAX) + 0.25 | V | | V I | DC input voltage | V CCIO_PIO = 1.2 V (3) (4) | -0.3 | V CCIO_PIO(MAX) + 0.25 | V | | V I | DC input voltage | V CCIO_PIO = 1.3 V (3) (4) | -0.3 | V CCIO_PIO(MAX) + 0.25 | V | | V I | DC input voltage | V CCIO_SDM = 1.8 V | -0.3 | V CCIO_SDM(MAX) + 0.3 | V | | V I | DC input voltage | V CCIO_HPS = 1.8 V | -0.3 | V CCIO_HPS(MAX) + 0.3 | V | | V I | DC input voltage | V CCIO_HVIO = 1.8 V, 2.5 V, 3.3 V | -0.3 | V CCIO_HVIO(MAX) + 0.3 | V | | I OUT (5) (6) | DC output current per pin | V CCIO_PIO = 1.0 V, 1.05 V, 1.1 V, 1.2 V, 1.3 V (7) (8) | -7.5 | 7.5 | mA | | I OUT (5) (6) | DC output current per pin | V CCIO_SDM , V CCIO_HPS = 1.8 V (9) | -20 | 20 | mA | | continued... | continued... | continued... | continued... | continued... | continued... |

| Symbol | Description | Condition | Minimum | Maximum | Unit | |----------|-------------------------------|------------------------------------------------------------------------------|-----------|-----------|--------| | | | V CCIO_HVIO = 1.8 V, 2.5 V, 3.3 V Current Strength Setting = 12 mA (10) (11) | -8 | 8 | mA | | | | V CCIO_HVIO = 1.8 V, 2.5 V, 3.3 V Current Strength Setting = 9 mA (10) (11) | -6 | 6 | mA | | | | V CCIO_HVIO = 1.8 V, 2.5 V, 3.3 V Current Strength Setting = 6 mA (10) (11) | -4 | 4 | mA | | | | V CCIO_HVIO = 1.8 V, 2.5 V, 3.3 V Current Strength Setting = 3 mA (10) (11) | -2 | 2 | mA | | T J (12) | Absolute junction temperature | - | -40 | 125 | °C | | T STG | Storage temperature | - | -55 | 150 | °C |

Table 4. E-Series FPGAs Absolute Maximum Ratings

For specification status, see the Data Sheet Status table

| Symbol | Description | Condition | Minimum | Maximum | Unit | |-----------|------------------------------------------------|-------------------------------|-----------|-----------|--------------| | V CC | Core voltage supply | SmartVID: -1V, -2V, -2E, -3V | -0.5 | 1.21 | V | | V CC | Core voltage supply | Fixed voltage: -4S | -0.5 | 1.07 | V | | V CC | Core voltage supply | Fixed voltage: -5S | -0.5 | 1.043 | V | | V CC | Core voltage supply | Fixed voltage: -6S, -6X | -0.5 | 1.004 | V | | V CCP | Periphery supply voltage for the I/O banks | SmartVID: -1V, -2V, -2E, -3V | -0.5 | 1.21 | V | | V CCP | Periphery supply voltage for the I/O banks | Fixed voltage: -4S | -0.5 | 1.07 | V | | V CCP | Periphery supply voltage for the I/O banks | Fixed voltage: -5S | -0.5 | 1.043 | V | | V CCP | Periphery supply voltage for the I/O banks | Fixed voltage: -6S, -6X | -0.5 | 1.004 | V | | V CCH_SDM | SDM block transceiver supply voltage sense | SmartVID: -1V, -2V, -2E, -3V | -0.5 | 1.07 | V | | V CCH_SDM | SDM block transceiver supply voltage sense | Without Transceiver: -4S | -0.5 | 1.07 | V | | V CCH_SDM | SDM block transceiver supply voltage sense | Without Transceiver: -5S, | -0.5 | 1.043 | V | | V CCH_SDM | SDM block transceiver supply voltage sense | Without Transceiver: -6S, -6X | -0.5 | 1.004 | V | | V CCH_SDM | SDM block transceiver supply voltage sense | With Transceiver | -0.5 | 1.332 | V | | V CCPT | Power supply for I/O, DTS, SDM, and system PLL | - | -0.5 | 2.08 | V | | V CCRCORE | Power supply for programmable power technology | - | -0.5 | 1.64 | V | | | | | | | continued... |

| Symbol | Description | Condition | Minimum | Maximum | Unit | |--------------------|-------------------------------------------------------------------------------------------------------------------------|-------------------------------|-----------|-----------|--------------| | V CCBAT (13) | Battery back-up power supply (for design security volatile key register) | - | -0.5 | 2.08 | V | | V CCIO_PIO_SDM | SDM block I/O supply voltage sense of bank 3A | 1.2 V | -0.5 | 1.6 | V | | V CC_IO_SDM | I/O digital supply voltage sense in SDM block | SmartVID: -1V, -2V, -2E, -3V | -0.5 | 1.21 | V | | V CC_IO_SDM | I/O digital supply voltage sense in SDM block | Fixed voltage: -4S | -0.5 | 1.07 | V | | V CC_IO_SDM | I/O digital supply voltage sense in SDM block | Fixed voltage: -5S | -0.5 | 1.043 | V | | V CC_IO_SDM | I/O digital supply voltage sense in SDM block | Fixed voltage: -6S, -6X | -0.5 | 1.004 | V | | V CCIO_SDM | SDM block configuration pins power supply | - | -0.5 | 2.08 | V | | V CCL_ADC_SDM | Periphery digital supply voltage sense to ADC, senses HPS digital supply on HPS devices, core supply on non-HPS devices | SmartVID: -1V, -2V, -2E, -3V | -0.5 | 1.21 | V | | V CCL_ADC_SDM | Periphery digital supply voltage sense to ADC, senses HPS digital supply on HPS devices, core supply on non-HPS devices | Fixed voltage: -4S | -0.5 | 1.07 | V | | V CCL_ADC_SDM | Periphery digital supply voltage sense to ADC, senses HPS digital supply on HPS devices, core supply on non-HPS devices | Fixed voltage: -5S | -0.5 | 1.043 | V | | V CCL_ADC_SDM | Periphery digital supply voltage sense to ADC, senses HPS digital supply on HPS devices, core supply on non-HPS devices | Fixed voltage: -5S, -6S, - 6X | -0.5 | 1.004 | V | | V CCL_SDM | SDM digital power supply | SmartVID: -1V, -2V, -2E, -3V | -0.5 | 1.07 | V | | V CCL_SDM | SDM digital power supply | Fixed voltage: -4S | -0.5 | 1.07 | V | | V CCL_SDM | SDM digital power supply | Fixed voltage: -5S | -0.5 | 1.043 | V | | V CCL_SDM | SDM digital power supply | Fixed voltage: -5S, -6S, - 6X | -0.5 | 1.004 | V | | V CC_HSSI_[L1, R4] | Transceiver, system PLL, and hard IP digital power supply | SmartVID: -1V, -2V, -2E, -3V | -0.5 | 1.07 | V | | V CC_HSSI_[L1, R4] | | | | | continued... |

| Symbol | Description | Condition | Minimum | Maximum | Unit | |-----------------------|------------------------------------------------------|------------------------------|-----------|-----------|--------| | | | Fixed voltage: -4S | -0.5 | 1.07 | V | | | | Fixed voltage: -5S | -0.5 | 1.043 | V | | | | Fixed voltage: -6S, -6X | -0.5 | 1.004 | V | | V CCPLLDIG_SDM | SDM block PLL digital power supply | SmartVID: -1V, -2V, -2E, -3V | -0.5 | 1.07 | V | | | | Fixed voltage: -4S | -0.5 | 1.07 | V | | | | Fixed voltage: -5S | -0.5 | 1.043 | V | | | | Fixed voltage: -6S, -6X | -0.5 | 1.004 | V | | V CCPLL_SDM | SDM block PLL analog power supply | - | -0.5 | 2.08 | V | | V CCFUSEWR_SDM | Fuse block writing power supply | - | -0.5 | 2.08 | V | | V CCADC | ADC voltage sensor power supply | - | -0.5 | 2.08 | V | | V CCL_HPS | HPS DSU voltage and periphery circuitry power supply | SmartVID: -1V, -2V, -2E, -3V | -0.5 | 1.21 | V | | | | Fixed voltage: -4S | -0.5 | 1.07 | V | | | | Fixed voltage: -5S | -0.5 | 1.043 | V | | | | Fixed voltage: -6S, -6X | -0.5 | 1.004 | V | | V CCL_HPS_CORE0_CORE1 | HPS A55 cores power rail | SmartVID: -1V, -2V, -2E, -3V | -0.5 | 1.21 | V | | | | Fixed voltage: -4S | -0.5 | 1.07 | V | | | | Fixed voltage: -5S | -0.5 | 1.043 | V | | | | Fixed voltage: -6S, -6X | -0.5 | 1.004 | V | | V CCL_HPS_CORE2 | HPS A76 core power rail | SmartVID: -1V, -2V, -2E, -3V | -0.5 | 1.21 | V | | | | Fixed voltage: -4S | -0.5 | 1.07 | V |

| Symbol | Description | Condition | Minimum | Maximum | Unit | |------------------------------|-------------------------------------------------------------------------------------------------------------------|------------------------------|-----------|-----------|--------------| | | | Fixed voltage: -5S | -0.5 | 1.043 | V | | | | Fixed voltage: -6S, -6X | -0.5 | 1.004 | V | | V CCL_HPS_CORE3 | HPS A76 core power rail | SmartVID: -1V, -2V, -2E, -3V | -0.5 | 1.21 | V | | | | Fixed voltage: -4S | -0.5 | 1.07 | V | | | | Fixed voltage: -5S | -0.5 | 1.043 | V | | | | Fixed voltage: -6S, -6X | -0.5 | 1.004 | V | | V CCPLLDIG1_HPS | HPS PLL1 digital power supply | SmartVID: -1V, -2V, -2E, -3V | -0.5 | 1.21 | V | | | | Fixed voltage: -4S | -0.5 | 1.07 | V | | | | Fixed voltage: -5S | -0.5 | 1.043 | V | | | | Fixed voltage: -6S, -6X | -0.5 | 1.004 | V | | V CCPLLDIG2_HPS | HPS PLL2 digital power supply | SmartVID: -1V, -2V, -2E, -3V | -0.5 | 1.21 | V | | | | Fixed voltage: -4S | -0.5 | 1.07 | V | | | | Fixed voltage: -5S | -0.5 | 1.043 | V | | | | Fixed voltage: -6S, -6X | -0.5 | 1.004 | V | | V CCPLL1_HPS | HPS PLL1 analog power supply | - | -0.5 | 2.08 | V | | V CCPLL2_HPS | HPS PLL2 analog power supply | - | -0.5 | 2.08 | V | | V CCIO_HPS | HPS I/O buffers power supply | - | -0.5 | 2.08 | V | | V CCEHT_GTS[L1, R4][A, B, C] | Transceiver PMA, TX PLL, transceiver reference clock, and global reference clock high-voltage analog power supply | - | -0.5 | 2.08 | V | | | | | | | continued... |

| Symbol | Description | Condition | Minimum | Maximum | Unit | |------------------------------|----------------------------------------------------------------------------------------------------------|-------------------------------|--------------|------------------------|--------------| | V CCERT_GTS[L1, R4][A, B, C] | Transceiver PMA, transceiver reference clock, and global reference clock low-voltage analog power supply | - | -0.5 | 1.34 | V | | V CCIO_PIO | HSIO bank power supply | V CCIO_PIO = 1.0 V | -0.5 | 1.365 | V | | V CCIO_PIO | HSIO bank power supply | V CCIO_PIO = 1.05 V | -0.5 | 1.43 | V | | V CCIO_PIO | HSIO bank power supply | V CCIO_PIO = 1.1 V | -0.5 | 1.5 | V | | V CCIO_PIO | HSIO bank power supply | V CCIO_PIO = 1.2 V | -0.5 | 1.64 | V | | V CCIO_PIO | HSIO bank power supply | V CCIO_PIO = 1.3 V | -0.5 | 1.74 | V | | V CCIO_HVIO | HVIO bank power supply | V CCIO_HVIO = 3.3 V | -0.5 | 3.74 | V | | V CCIO_HVIO | HVIO bank power supply | V CCIO_HVIO = 2.5 V | -0.5 | 2.83 | V | | V CCIO_HVIO | HVIO bank power supply | V CCIO_HVIO = 1.8 V | -0.5 | 2.04 | V | | V CCPT_HVIO | Supply voltage for 1.8 V I/O | - | -0.5 | 2.04 | V | | V I | DC input voltage | V CCIO_PIO = 1.0 V (14) (15) | -0.3 | V CCIO_PIO(MAX) + 0.25 | V | | V I | DC input voltage | V CCIO_PIO = 1.05 V (14) (15) | -0.3 | V CCIO_PIO(MAX) + 0.25 | V | | V I | DC input voltage | V CCIO_PIO = 1.1 V (14) (15) | -0.3 | V CCIO_PIO(MAX) + 0.25 | V | | V I | DC input voltage | V CCIO_PIO = 1.2 V (14) (15) | -0.3 | V CCIO_PIO(MAX) + 0.25 | V | | V I | DC input voltage | V CCIO_PIO = 1.3 V (14) (15) | -0.3 | V CCIO_PIO(MAX) + 0.25 | V | | V I | DC input voltage | V CCIO_SDM = 1.8 V | -0.3 | V CCIO_SDM(MAX) + 0.3 | V | | V I | DC input voltage | V CCIO_HPS = 1.8 V | -0.3 | V CCIO_HPS(MAX) + 0.3 | V | | continued... | continued... | continued... | continued... | continued... | continued... |

| Symbol | Description | Condition | Minimum | Maximum | Unit | |-----------------|---------------------------|------------------------------------------------------------------------------|--------------|------------------------|--------------| | | | V CCIO_HVIO = 1.8 V, 2.5 V, 3.3 V | -0.3 | V CCIO_HVIO(MAX) + 0.3 | V | | I OUT (16) (17) | DC output current per pin | V CCIO_PIO = 1.0 V, 1.05 V, 1.1 V, 1.2 V, 1.3 V (18) (19) | -7.5 | 7.5 | mA | | I OUT (16) (17) | DC output current per pin | V CCIO_SDM , V CCIO_HPS = 1.8 V (20) | -20 | 20 | mA | | I OUT (16) (17) | DC output current per pin | V CCIO_HVIO = 1.8 V, 2.5 V, 3.3 V Current Strength Setting = 12 mA (21) (22) | -8 | 8 | mA | | I OUT (16) (17) | DC output current per pin | V CCIO_HVIO = 1.8 V, 2.5 V, 3.3 V Current Strength Setting = 9 mA (21) (22) | -6 | 6 | mA | | I OUT (16) (17) | DC output current per pin | V CCIO_HVIO = 1.8 V, 2.5 V, 3.3 V Current Strength Setting = 6 mA (21) (22) | -4 | 4 | mA | | continued... | continued... | continued... | continued... | continued... | continued... |

(21) The maximum current allowed through any HVIO pin when the device is not turned on or during power-up/power-down conditions is 10 mA. Pin voltage during these conditions should not exceed VCCIO_HVIO supply rail of the bank where the I/O pin resides in.
(22) The DC output current per pin may exceed specified values with a duration limit. For more details, refer to General Purpose I/O User Guide .

Related Information

Recommended Operating Conditions on page 22
I/O Standard Specifications on page 45
General-Purpose I/O User Guide: Agilex ™ 5 FPGAs and SoCs

Maximum Allowed Overshoot and Undershoot Voltage

During transitions, the toggling input data or clock signals may overshoot to the voltage listed in the following tables and undershoot to the following limits for input currents less than 100 mA and periods shorter than 20 ns.

Undershoot limit of -1.1 V when using VCCIO_HPS or VCCIO_SDM of 1.8 V.
Undershoot limit of -0.3 V when using VCCIO_PIO of 1.3 V, 1.2 V, 1.1 V, 1.05 V, and 1.0 V.

No overshooting beyond 1.65 V and undershooting below 0.273 V is allowed when using True Differential Signaling I/O standard at VCCIO_PIO = 1.3 V.

No overshooting beyond 1.177 V and undershooting below 0.573 V is allowed when using True Differential Signaling I/O standard at VCCIO_PIO = 1.2 V, 1.1 V, and 1.05 V.

The maximum allowed overshoot duration is specified as a percentage of high time (calculated as ([delta T]/T) × 100) over the lifetime of the device. A DC signal is equivalent to 100% duty cycle.

(23) When using the device at TJ = 100°C, the device can operate under the recommended operating conditions over a minimum device lifetime of 11.4 years.

Table 5. Maximum Allowed Overshoot During Transitions for 1.0 V I/O in HSIO Bank

This table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage of device lifetime.

For specification status, see the Data Sheet Status table

| Symbol | Description | Condition (V) | Overshoot Duration as %at T J = 100°C | Unit | |----------|------------------|------------------------|-----------------------------------------|--------| | V i (AC) | AC input voltage | V CCIO_PIO + 0.25 | 100 | % | | | | V CCIO_PIO + 0.30 (24) | 30 | % | | | | V CCIO_PIO + 0.35 | 4 | % | | | | > V CCIO_PIO + 0.40 | No overshoot allowed | % |

Table 6. Maximum Allowed Overshoot During Transitions for 1.05 V I/O in HSIO Bank

This table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage of device lifetime.

For specification status, see the Data Sheet Status table

| Symbol | Description | Condition (V) | Overshoot Duration as %at T J = 100°C | Unit | |----------|------------------|------------------------|-----------------------------------------|--------| | V i (AC) | AC input voltage | V CCIO_PIO + 0.25 | 100 | % | | V i (AC) | AC input voltage | V CCIO_PIO + 0.30 (25) | 30 | % | | V i (AC) | AC input voltage | V CCIO_PIO + 0.35 | 4 | % | | V i (AC) | AC input voltage | > V CCIO_PIO + 0.40 | No overshoot allowed | % |

Table 7. Maximum Allowed Overshoot During Transitions for 1.1 V I/O in HSIO Bank

This table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage of device lifetime.

For specification status, see the Data Sheet Status table

| Symbol | Description | Condition (V) | Overshoot Duration as %at T J = 100°C | Unit | |----------|------------------|------------------------|-----------------------------------------|--------| | V i (AC) | AC input voltage | V CCIO_PIO + 0.25 | 100 | % | | V i (AC) | AC input voltage | V CCIO_PIO + 0.30 (26) | 30 | % | | V i (AC) | AC input voltage | V CCIO_PIO + 0.35 | 4 | % | | V i (AC) | AC input voltage | > V CCIO_PIO + 0.40 | No overshoot allowed | % |

Table 8. Maximum Allowed Overshoot During Transitions for 1.2 V I/O in HSIO Bank

This table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage of device lifetime.

For specification status, see the Data Sheet Status table

| Symbol | Description | Condition (V) | Overshoot Duration as %at T J = 100°C | Unit | |----------|------------------|------------------------|-----------------------------------------|--------| | V i (AC) | AC input voltage | V CCIO_PIO + 0.25 | 100 | % | | V i (AC) | AC input voltage | V CCIO_PIO + 0.30 (27) | 30 | % | | V i (AC) | AC input voltage | V CCIO_PIO + 0.35 | 4 | % | | V i (AC) | AC input voltage | > V CCIO_PIO + 0.40 | No overshoot allowed | % |

Table 9. Maximum Allowed Overshoot During Transitions for 1.3 V I/O in HSIO Bank

This table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage of device lifetime.

For specification status, see the Data Sheet Status table

| Symbol | Description | Condition (V) | Overshoot Duration as %at T J = 100°C | Unit | |----------|------------------|------------------------|-----------------------------------------|--------| | V i (AC) | AC input voltage | V CCIO_PIO + 0.25 | 100 | % | | | | V CCIO_PIO + 0.30 (28) | 65 | % | | | | V CCIO_PIO + 0.35 | 7 | % | | | | > V CCIO_PIO + 0.40 | No overshoot allowed | % |

Table 10. Maximum Allowed Overshoot During Transitions for 1.8 V I/O in HPS and SDM I/O Banks

This table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage of device lifetime.

For specification status, see the Data Sheet Status table

| Symbol | Description | Condition (V) | Overshoot Duration as %at T J = 100°C | Unit | |--------------|------------------|--------------------------------------|-----------------------------------------|--------------| | V i (AC) | AC input voltage | V CCIO_SDM + 0.30, V CCIO_HPS + 0.30 | 100 | % | | V i (AC) | AC input voltage | V CCIO_SDM + 0.35, V CCIO_HPS + 0.35 | 60 | % | | V i (AC) | AC input voltage | V CCIO_SDM + 0.40, V CCIO_HPS + 0.40 | 30 | % | | V i (AC) | AC input voltage | V CCIO_SDM + 0.45, V CCIO_HPS + 0.45 | 20 | % | | continued... | continued... | continued... | continued... | continued... |

| Symbol | Description | Condition (V) | Overshoot Duration as %at T J = 100°C | Unit | |----------|---------------|------------------------------------------|-----------------------------------------|--------| | | | V CCIO_SDM + 0.50, V CCIO_HPS + 0.50 | 10 | % | | | | V CCIO_SDM + 0.55, V CCIO_HPS + 0.55 | 6 | % | | | | > V CCIO_SDM + 0.55, > V CCIO_HPS + 0.55 | No overshoot allowed | % |

Table 11. Maximum Allowed Overshoot During Transitions for 1.8 V, 2.5 V, and 3.3 V in HVIO Bank

This table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage of device lifetime.

For specification status, see the Data Sheet Status table

| Symbol | Description | Condition (V) | Overshoot Duration as %at T J = 100°C | Unit | |---------------|------------------|----------------------|-----------------------------------------|--------| | V i (AC) (29) | AC input voltage | V CCIO_HVIO + 0.30 | 100 | % | | V i (AC) (29) | AC input voltage | V CCIO_HVIO + 0.35 | 42 | % | | V i (AC) (29) | AC input voltage | V CCIO_HVIO + 0.40 | 18 | % | | V i (AC) (29) | AC input voltage | V CCIO_HVIO + 0.45 | 9 | % | | V i (AC) (29) | AC input voltage | V CCIO_HVIO + 0.50 | 4 | % | | V i (AC) (29) | AC input voltage | > V CCIO_HVIO + 0.55 | No overshoot allow | % |

For example, when using 1.2 V I/O standard with 1.26 V VCCIO_PIO, a signal that overshoots to 1.61 V can only be at 1.61 V for ~4% over the lifetime of the device. For an overshoot of 1.51 V, the percentage of high time for the overshoot can be as high as 100% over the lifetime of the device.

(29) This value applies to both input and output configuration.

Figure 1. Overshoot Duration Example (for 1.2 V HSIO Bank at VCCIO_PIO = 1.26 V)

Recommended Operating Conditions

This section lists the functional operation limits for the AC and DC parameters.

Recommended Operating Conditions

Table 12. D-Series FPGAs Recommended Operating Conditions

This table lists the steady-state voltage values expected. Power supply ramps must all be strictly monotonic, without plateaus.

For specification status, see the Data Sheet Status table

| Symbol | Description | Condition | Minimum (30) | Typical | Maximum (30) | Unit | |--------------|------------------------------------------------|--------------------------------|----------------|------------------|----------------|--------------| | V CC | Core voltage supply | SmartVID (31) : -1V, - 2V, -3V | (Typical) - 3% | 0.70 - 0.90 (32) | (Typical) + 3% | V | | V CCP | Periphery supply voltage for the I/O banks | SmartVID (31) : -1V, - 2V, -3V | (Typical) - 3% | 0.70 - 0.90 (32) | (Typical) + 3% | V | | V CCH_SDM | SDM block transceiver supply voltage sense | - | 0.975 | 1 | 1.025 | V | | V CCPT (33) | Power supply for I/O, DTS, SDM, and system PLL | - | 1.746 | 1.8 | 1.854 | V | | V CCRCORE | Power supply for programmable power technology | - | 1.14 | 1.2 | 1.26 | V | | continued... | continued... | continued... | continued... | continued... | continued... | continued... |

| Symbol | Description | Condition | Minimum (30) | Typical | Maximum (30) | Unit | |---------------------|-------------------------------------------------------------------------------------------------------------------------|--------------------------------|----------------|------------------|----------------|--------------| | V CCBAT (34) | Battery back-up power supply (for design security volatile key register) | - | 1 | 1 - 1.80 | 1.8 | V | | I BAT | Battery back-up power supply (for design security volatile key register) | V CCBAT = 1.2 V | - | - | 200 | nA | | V CCIO_PIO_SDM (35) | SDM block I/O supply voltage sense of bank 3A | 1.2 V | 1.164 | 1.2 | 1.236 | V | | V CC_IO_SDM | I/O digital supply voltage sense in SDM block | SmartVID (31) : -1V, - 2V, -3V | (Typical) - 3% | 0.70 - 0.90 (32) | (Typical) + 3% | V | | V CCIO_SDM | SDM block configuration pins power supply | - | 1.71 | 1.8 | 1.89 | V | | V CCL_ADC_SDM | Periphery digital supply voltage sense to ADC, senses HPS digital supply on HPS devices, core supply on non-HPS devices | SmartVID (31) : -1V, - 2V, -3V | (Typical) - 3% | 0.70 - 0.90 (32) | (Typical) + 3% | V | | V CCL_SDM | SDM digital power supply | - | 0.776 | 0.8 | 0.824 | V | | V CCPLLDIG_SDM | SDM block PLL digital power supply | - | 0.776 | 0.8 | 0.824 | V | | continued... | continued... | continued... | continued... | continued... | continued... | continued... |

| Symbol | Description | Condition | Minimum (30) | Typical | Maximum (30) | Unit | |----------------|-----------------------------------|-------------------------|----------------|--------------|-------------------|--------------| | V CCPLL_SDM | SDM block PLL analog power supply | - | 1.71 | 1.8 | 1.89 | V | | V CCFUSEWR_SDM | Fuse block writing power supply | - | 1.71 | 1.8 | 1.89 | V | | V CCADC | ADC voltage sensor power supply | - | 1.71 | 1.8 | 1.89 | V | | V CCIO_PIO | HSIO bank power supply | 1.0 V | 0.95 | 1 | 1.05 | V | | V CCIO_PIO | HSIO bank power supply | 1.05 V (36) | 1.0185 | 1.05 | 1.0815 | V | | V CCIO_PIO | HSIO bank power supply | 1.1 V (36) | 1.067 | 1.1 | 1.133 | V | | V CCIO_PIO | HSIO bank power supply | 1.2 V (36) | 1.164 | 1.2 | 1.236 | V | | V CCIO_PIO | HSIO bank power supply | 1.3 V | 1.261 | 1.3 | 1.339 | V | | V CCIO_HVIO | HVIO bank power supply | 3.3 V | 3.201 | 3.3 | 3.399 | V | | V CCIO_HVIO | HVIO bank power supply | 2.5 V | 2.425 | 2.5 | 2.575 | V | | V CCIO_HVIO | HVIO bank power supply | 1.8 V | 1.746 | 1.8 | 1.854 | V | | V CCPT_HVIO | Supply voltage for 1.8 V I/O | - | 1.746 | 1.8 | 1.854 | V | | V I (37) | DC input voltage | V CCIO_PIO = 1.0 V (38) | -0.3000 | - | V CCIO_PIO + 0.25 | V | | continued... | continued... | continued... | continued... | continued... | continued... | continued... |

| Symbol | Description | Condition | Minimum (30) | Typical | Maximum (30) | Unit | |----------|----------------|-------------------------------------------------|----------------|-----------|-------------------|--------------| | | | V CCIO_PIO = 1.05 V (39) (38) | -0.3000 | - | V CCIO_PIO + 0.25 | V | | | | V CCIO_PIO = 1.1 V (39) (38) | -0.3000 | - | V CCIO_PIO + 0.25 | V | | | | V CCIO_PIO = 1.2 V (39) (38) | -0.3000 | - | V CCIO_PIO + 0.25 | V | | | | V CCIO_PIO = 1.3 V (39) (38) | -0.3000 | - | V CCIO_PIO + 0.25 | V | | | | V CCIO_SDM = 1.8 V | -0.3000 | - | V CCIO_SDM + 0.3 | V | | | | V CCIO_HPS = 1.8 V | -0.3000 | - | V CCIO_HPS + 0.3 | V | | | | V CCIO_HVIO = 1.8 V, 2.5 V, 3.3 V | -0.3000 | - | V CCIO_HVIO + 0.3 | V | | V O | Output voltage | V CCIO_PIO = 1.0 V, 1.05 V, 1.1 V, 1.2 V, 1.3 V | 0 | - | V CCIO_PIO | V | | V O | Output voltage | V CCIO_SDM = 1.8 V | 0 | - | V CCIO_SDM | V | | V O | Output voltage | V CCIO_HPS = 1.8 V | 0 | - | V CCIO_HPS | V | | V O | Output voltage | V CCIO_HVIO = 1.8 V, 2.5 V, 3.3 V | 0 | - | V CCIO_HVIO | V | | | | | | | | continued... |

| Symbol | Description | Condition | Minimum (30) | Typical | Maximum (30) | Unit | |------------------|--------------------------------|--------------|----------------|-----------|----------------|--------| | T J | Operating junction temperature | Extended | 0 | - | 100 (40) | °C | | T J | | Industrial | -40 | - | 100 (40) | °C | | t RAMP (41) (42) | Power supply ramp time | Standard POR | 200 μs | - | 100 ms | - |

Table 13. E-Series FPGAs Recommended Operating Conditions

This table lists the steady-state voltage values expected. Power supply ramps must all be strictly monotonic, without plateaus.

For specification status, see the Data Sheet Status table

| Symbol | Description | Condition | Minimum (43) | Typical | Maximum (43) | Unit | |--------------|---------------------|-------------------------------------|----------------|------------------|----------------|--------------| | V CC | Core voltage supply | SmartVID (44) : -1V, - 2V, -2E, -3V | (Typical) - 3% | 0.70 - 0.90 (45) | (Typical) + 3% | V | | | | Fixed voltage: -4S | 0.776 | 0.8 | 0.824 | V | | continued... | continued... | continued... | continued... | continued... | continued... | continued... |

(43) This value describes the required voltage measured between the PCB power and ground ball during normal device operation. The voltage ripple includes both regulator DC ripple and the dynamic noise.
(44) The use of Power Management Bus (PMBus) voltage regulator dedicated to SmartVID devices is mandatory. The PMBus voltage regulator and SmartVID devices are connected via PMBus.
(45) The typical value is based on the SmartVID programmed value.

| Symbol | Description | Condition | Minimum (43) | Typical | Maximum (43) | Unit | |-------------|------------------------------------------------|-------------------------------------|----------------|------------------|----------------|--------------| | | | Fixed voltage: -5S | 0.756 | 0.78 | 0.803 | V | | | | Fixed voltage: -6S, - 6X | 0.7275 | 0.75 | 0.7725 | V | | V CCP | Periphery supply voltage for the I/O banks | SmartVID (44) : -1V, - 2V, -2E, -3V | (Typical) - 3% | 0.70 - 0.90 (45) | (Typical) + 3% | V | | V CCP | Periphery supply voltage for the I/O banks | Fixed voltage: -4S | 0.776 | 0.8 | 0.824 | V | | V CCP | Periphery supply voltage for the I/O banks | Fixed voltage: -5S | 0.756 | 0.78 | 0.803 | V | | V CCP | Periphery supply voltage for the I/O banks | Fixed voltage: -6S, - 6X | 0.7275 | 0.75 | 0.7725 | V | | V CCH_SDM | SDM block transceiver supply voltage sense | SmartVID (44) : -1V, - 2V, -2E, -3V | 0.776 | 0.8 | 0.824 | V | | V CCH_SDM | SDM block transceiver supply voltage sense | Without transceiver: - 4S | 0.776 | 0.8 | 0.824 | V | | V CCH_SDM | SDM block transceiver supply voltage sense | Without transceiver: - 5S | 0.756 | 0.78 | 0.803 | V | | V CCH_SDM | SDM block transceiver supply voltage sense | Without transceiver: - 6S, -6X | 0.7275 | 0.75 | 0.7725 | V | | V CCH_SDM | SDM block transceiver supply voltage sense | With transceiver | 0.975 | 1 | 1.025 | V | | V CCPT (46) | Power supply for I/O, DTS, SDM, and system PLL | - | 1.746 | 1.8 | 1.854 | V | | V CCRCORE | Power supply for programmable power technology | - | 1.14 | 1.2 | 1.26 | V | | | | | | | | continued... |

| Symbol | Description | Condition | Minimum (43) | Typical | Maximum (43) | Unit | |---------------------|-------------------------------------------------------------------------------------------------------------------------|-------------------------------------|----------------|------------------|----------------|--------------| | V CCBAT (47) | Battery back-up power supply (for design security volatile key register) | - | 1 | 1 - 1.80 | 1.8 | V | | I BAT | Battery back-up power supply (For design security volatile key register) | V CCBAT = 1.2 V | - | - | 200 | nA | | V CCIO_PIO_SDM (48) | SDM block I/O supply voltage sense of bank 3A | 1.2 V | 1.164 | 1.2 | 1.236 | V | | V CC_IO_SDM | I/O digital supply voltage sense in SDM block | SmartVID (44) : -1V, - 2V, -2E, -3V | (Typical) - 3% | 0.70 - 0.90 (45) | (Typical) + 3% | V | | V CC_IO_SDM | I/O digital supply voltage sense in SDM block | Fixed voltage: -4S | 0.776 | 0.8 | 0.824 | V | | V CC_IO_SDM | I/O digital supply voltage sense in SDM block | Fixed voltage: -5S | 0.756 | 0.78 | 0.803 | V | | V CC_IO_SDM | I/O digital supply voltage sense in SDM block | Fixed voltage: -6S, - 6X | 0.7275 | 0.75 | 0.7725 | V | | V CCIO_SDM | SDM block configuration pins power supply | - | 1.71 | 1.8 | 1.89 | V | | V CCL_ADC_SDM | Periphery digital supply voltage sense to ADC, senses HPS digital supply on HPS devices, core supply on non-HPS devices | SmartVID (44) : -1V, - 2V, -2E, -3V | (Typical) - 3% | 0.70 - 0.90 (45) | (Typical) + 3% | V | | V CCL_ADC_SDM | Periphery digital supply voltage sense to ADC, senses HPS digital supply on HPS devices, core supply on non-HPS devices | Fixed voltage: -4S | 0.776 | 0.8 | 0.824 | V | | V CCL_ADC_SDM | Periphery digital supply voltage sense to ADC, senses HPS digital supply on HPS devices, core supply on non-HPS devices | Fixed voltage: -5S | 0.756 | 0.78 | 0.803 | V | | continued... | continued... | continued... | continued... | continued... | continued... | continued... |

| Symbol | Description | Condition | Minimum (43) | Typical | Maximum (43) | Unit | |----------------|------------------------------------|-------------------------------------|----------------|--------------|----------------|--------------| | | | Fixed voltage: -6S, - 6X | 0.7275 | 0.75 | 0.7725 | V | | V CCL_SDM | SDM digital power supply | SmartVID (44) : -1V, - 2V, -2E, -3V | 0.776 | 0.8 | 0.824 | V | | V CCL_SDM | SDM digital power supply | Fixed voltage: -4S | 0.776 | 0.8 | 0.824 | V | | V CCL_SDM | SDM digital power supply | Fixed voltage: -5S | 0.756 | 0.78 | 0.803 | V | | V CCL_SDM | SDM digital power supply | Fixed voltage: -6S, - 6X | 0.7275 | 0.75 | 0.7725 | V | | V CCPLLDIG_SDM | SDM block PLL digital power supply | SmartVID (44) : -1V, - 2V, -2E, -3V | 0.776 | 0.8 | 0.824 | V | | V CCPLLDIG_SDM | SDM block PLL digital power supply | Fixed voltage: -4S | 0.776 | 0.8 | 0.824 | V | | V CCPLLDIG_SDM | SDM block PLL digital power supply | Fixed voltage: -5S | 0.756 | 0.78 | 0.803 | V | | V CCPLLDIG_SDM | SDM block PLL digital power supply | Fixed voltage: -6S, - 6X | 0.7275 | 0.75 | 0.7725 | V | | V CCPLL_SDM | SDM block PLL analog power supply | - | 1.71 | 1.8 | 1.89 | V | | V CCFUSEWR_SDM | Fuse block writing power supply | - | 1.71 | 1.8 | 1.89 | V | | V CCADC | ADC voltage sensor power supply | - | 1.71 | 1.8 | 1.89 | V | | V CCIO_PIO | HSIO bank power supply | 1.0 V | 0.95 | 1 | 1.05 | V | | V CCIO_PIO | HSIO bank power supply | 1.05 V (49) | 1.0185 | 1.05 | 1.0815 | V | | continued... | continued... | continued... | continued... | continued... | continued... | continued... |

| Symbol | Description | Condition | Minimum (43) | Typical | Maximum (43) | Unit | |--------------|------------------------------|-------------------------------|----------------|--------------|-------------------|--------------| | | | 1.1 V (49) | 1.067 | 1.1 | 1.133 | V | | | | 1.2 V (49) | 1.164 | 1.2 | 1.236 | V | | | | 1.3 V | 1.261 | 1.3 | 1.339 | V | | V CCIO_HVIO | HVIO bank power supply | 3.3 V | 3.201 | 3.3 | 3.399 | V | | V CCIO_HVIO | HVIO bank power supply | 2.5 V | 2.425 | 2.5 | 2.575 | V | | V CCIO_HVIO | HVIO bank power supply | 1.8 V | 1.746 | 1.8 | 1.854 | V | | V CCPT_HVIO | Supply voltage for 1.8 V I/O | - | 1.746 | 1.8 | 1.854 | V | | V I (50) | DC input voltage | V CCIO_PIO = 1.0 V (51) | -0.3000 | - | V CCIO_PIO + 0.25 | V | | V I (50) | DC input voltage | V CCIO_PIO = 1.05 V (52) (51) | -0.3000 | - | V CCIO_PIO + 0.25 | V | | V I (50) | DC input voltage | V CCIO_PIO = 1.1 V (52) (51) | -0.3000 | - | V CCIO_PIO + 0.25 | V | | continued... | continued... | continued... | continued... | continued... | continued... | continued... |

LVDS SERDES receiver mode with the use of 1.05 V, 1.1 V, 1.2 V True Differential Signaling input standard

· PHYLITE mode

· GPIO mode

(50) This value applies to both input and tri-stated output configuration. Pin voltage should not be externally pulled higher than the maximum value.

(51) For LVCMOS pin utilization of equal to or less than 25 pins within a bank, the VI(DC) for the LVCMOS input can go up to VCCIO_PIO + 0.3 V.
(52) Applies to LVCMOS I/O standards only. For true differential input, refer to the VICM(min), VICM(max), and VID(max) specifications.

| Symbol | Description | Condition | Minimum (43) | Typical | Maximum (43) | Unit | |------------------|--------------------------------|-------------------------------------------------|----------------|-----------|-------------------|--------| | | | V CCIO_PIO = 1.2 V (52) (51) | -0.3000 | - | V CCIO_PIO + 0.25 | V | | | | V CCIO_PIO = 1.3 V (52) (51) | -0.3000 | - | V CCIO_PIO + 0.25 | V | | | | V CCIO_SDM = 1.8 V | -0.3000 | - | V CCIO_SDM + 0.3 | V | | | | V CCIO_HPS = 1.8 V | -0.3000 | - | V CCIO_HPS + 0.3 | V | | | | V CCIO_HVIO = 1.8 V, 2.5 V, 3.3 V | -0.3000 | - | V CCIO_HVIO + 0.3 | V | | V O | Output voltage | V CCIO_PIO = 1.0 V, 1.05 V, 1.1 V, 1.2 V, 1.3 V | 0 | - | V CCIO_PIO | V | | V O | Output voltage | V CCIO_SDM = 1.8 V | 0 | - | V CCIO_SDM | V | | V O | Output voltage | V CCIO_HPS = 1.8 V | 0 | - | V CCIO_HPS | V | | V O | Output voltage | V CCIO_HVIO = 1.8 V, 2.5 V, 3.3 V | 0 | - | V CCIO_HVIO | V | | T J | Operating junction temperature | Extended | 0 | - | 100 (53) | °C | | T J | Operating junction temperature | Industrial | -40 | - | 100 (53) | °C | | t RAMP (54) (55) | Power supply ramp time | Standard POR | 200 μs | - | 100 ms | - |

Related Information

I/O Standard Specifications on page 45

GTS Transceiver Power Supply Operating Conditions

Table 14. D-Series FPGAs GTS Transceiver Power Supply Operating Conditions

For specification status, see the Data Sheet Status table

| Symbol | Description | Typical DC Level (V) | Recommended VR Accuracy (% of Typical DC Level) | Recommended VR Ripple (% of Typical DC Level) | Recommended AC Transient (% of Typical DC Level) | Maximum (VR Accuracy + Ripple + AC Transient) (% of Typical DC Level) (56) | Unit | |---------------------------------------|----------------------------------------------------------------------------------------------------|------------------------|---------------------------------------------------|-------------------------------------------------|----------------------------------------------------|------------------------------------------------------------------------------|--------| | V CC_HSSI_[L1, R4] | Transceiver, system PLL, and hard IP digital power supply | 0.8 | ±0.5 | ±2.5 | ±2.5 | ±3 | V | | V CCEHT_GTS[L1, R4] [A, B, C, D] (57) | Transceiver PMA, transceiver PLL, and transceiver reference clock high voltage analog power supply | 1.8 | ±0.5 | ±2.0 | ±2.0 | ±2.5 | V | | V CCERT_GTS[L1, R4] [A, B, C, D] | Transceiver PMA and transceiver reference clock low voltage analog power supply | 1 | ±0.5 | ±2.0 | ±2.0 | ±2.5 | V |

Table 15. E-Series FPGAs GTS Transceiver Power Supply Operating Conditions

For specification status, see the Data Sheet Status table

| Symbol | Description | Speed Grade | Typical DC Level (V) | Recommended VR Accuracy (% of Typical DC Level) | Recommended VR Ripple (% of Typical DC level) | Recommended AC Transient (% of Typical DC level) | Maximum (VR Accuracy + Ripple + AC Transient) (% of Typical DC Level) (58) | Unit | |-----------------------------------|----------------------------------------------------------------------------------------------------|--------------------------|------------------------|---------------------------------------------------|-------------------------------------------------|----------------------------------------------------|------------------------------------------------------------------------------|--------| | V CC_HSSI_[L1, R4] | Transceiver, system PLL, and hard IP digital power supply | -6S, -6X | 0.75 | ±0.5 | ±2.5 | ±2.5 | ±3 | V | | V CC_HSSI_[L1, R4] | | -5S | 0.78 | ±0.5 | ±2.5 | ±2.5 | ±3 | V | | V CC_HSSI_[L1, R4] | | -1V, -2V, -2E, - 3V, -4S | 0.8 | ±0.5 | ±2.5 | ±2.5 | ±3 | V | | V CCEHT_GTS[L1,R4] [A, B, C] (59) | Transceiver PMA, transceiver PLL, and transceiver reference clock high voltage analog power supply | - | 1.8 | ±0.5 | ±2.0 | ±2.0 | ±2.5 | V | | V CCERT_GTS[L1, R4] [A, B, C] | Transceiver PMA and transceiver reference clock low voltage analog power supply | - | 1 | ±0.5 | ±2.0 | ±2.0 | ±2.5 | V |

HPS Power Supply Operating Conditions

Table 16. D-Series FPGAs HPS Power Supply Operating Conditions

This table lists the steady-state voltage and current values expected for system-on-a-chip (SoC) devices with Arm*-based hard processor system (HPS). Power supply ramps must all be strictly monotonic, without plateaus. Refer to the Recommended Operating Conditions table for the steady-state voltage values expected from the FPGA portion of the SoC devices.

For specification status, see the Data Sheet Status table

| Symbol | Description | Condition | Minimum | Typical | Maximum | Unit | |-----------------------|----------------------------------------------------------------|-------------------------------|----------------|-------------|----------------|--------| | V CCL_HPS | HPS DSU voltage and periphery circuitry power supply | SmartVID: -1V, -2V, - 3V (60) | (Typical) - 3% | 0.70 - 0.90 | (Typical) + 3% | V | | V CCL_HPS_CORE0_CORE1 | HPS Cortex*-A55 core 0 and core 1 power rail | SmartVID: -1V, -2V, - 3V (60) | (Typical) - 3% | 0.70 - 0.90 | (Typical) + 3% | V | | V CCL_HPS_CORE2 | HPS Cortex*-A76 core 2 power rail | SmartVID: -1V, -2V, - 3V (60) | (Typical) - 3% | 0.70 - 0.90 | (Typical) + 3% | V | | V CCL_HPS_CORE3 | HPS Cortex*-A76 core 3 power rail | SmartVID: -1V, -2V, - 3V (60) | (Typical) - 3% | 0.70 - 0.90 | (Typical) + 3% | V | | V CCPLLDIG1_HPS | HPS PLL1 digital power supply (can be connected to V CCL_HPS ) | SmartVID: -1V, -2V, - 3V (60) | (Typical) - 3% | 0.70 - 0.90 | (Typical) + 3% | V | | V CCPLLDIG2_HPS | HPS PLL2 digital power supply (can be connected to V CCL_HPS ) | SmartVID: -1V, -2V, - 3V (60) | (Typical) - 3% | 0.70 - 0.90 | (Typical) + 3% | V | | V CCPLL1_HPS | HPS PLL1 analog power supply | 1.8 V | 1.71 | 1.8 | 1.89 | V | | V CCPLL2_HPS | HPS PLL2 analog power supply | 1.8 V | 1.71 | 1.8 | 1.89 | V | | V CCIO_HPS | HPS I/O buffers power supply | 1.8 V | 1.71 | 1.8 | 1.89 | V |

Table 17. E-Series FPGAs HPS Power Supply Operating Conditions

This table lists the steady-state voltage and current values expected for system-on-a-chip (SoC) devices with Arm-based hard processor system (HPS). Power supply ramps must all be strictly monotonic, without plateaus. Refer to the Recommended Operating Conditions table for the steady-state voltage values expected from the FPGA portion of the SoC devices.

For specification status, see the Data Sheet Status table

| Symbol | Description | Condition | Minimum | Typical | Maximum | Unit | |-----------------------|------------------------------------------------------|------------------------------------|----------------|--------------|----------------|--------------| | V CCL_HPS | HPS DSU voltage and periphery circuitry power supply | SmartVID: -1V, -2V, - 2E, -3V (61) | (Typical) - 3% | 0.70 - 0.90 | (Typical) + 3% | V | | V CCL_HPS | HPS DSU voltage and periphery circuitry power supply | Fixed voltage: -4S | (Typical) - 3% | 0.8 | (Typical) + 3% | V | | V CCL_HPS | HPS DSU voltage and periphery circuitry power supply | Fixed voltage: -5S | (Typical) - 3% | 0.78 | (Typical) + 3% | V | | V CCL_HPS | HPS DSU voltage and periphery circuitry power supply | Fixed voltage: -6S, - 6X | (Typical) - 3% | 0.75 | (Typical) + 3% | V | | V CCL_HPS_CORE0_CORE1 | HPS Cortex*-A55 core 0 and core 1 power rail | SmartVID: -1V, -2V, - 2E, -3V (61) | (Typical) - 3% | 0.70 - 0.90 | (Typical) + 3% | V | | V CCL_HPS_CORE0_CORE1 | HPS Cortex*-A55 core 0 and core 1 power rail | Fixed voltage: -4S | (Typical) - 3% | 0.8 | (Typical) + 3% | V | | V CCL_HPS_CORE0_CORE1 | HPS Cortex*-A55 core 0 and core 1 power rail | Fixed voltage: -5S | (Typical) - 3% | 0.78 | (Typical) + 3% | V | | V CCL_HPS_CORE0_CORE1 | HPS Cortex*-A55 core 0 and core 1 power rail | Fixed voltage: -6S, - 6X | (Typical) - 3% | 0.75 | (Typical) + 3% | V | | V CCL_HPS_CORE2 | HPS Cortex*-A76 core 2 power rail | SmartVID: -1V, -2V, - 2E, -3V (61) | (Typical) - 3% | 0.70 - 0.90 | (Typical) + 3% | V | | V CCL_HPS_CORE2 | HPS Cortex*-A76 core 2 power rail | Fixed voltage: -4S | (Typical) - 3% | 0.8 | (Typical) + 3% | V | | V CCL_HPS_CORE2 | HPS Cortex*-A76 core 2 power rail | Fixed voltage: -5S | (Typical) - 3% | 0.78 | (Typical) + 3% | V | | V CCL_HPS_CORE2 | HPS Cortex*-A76 core 2 power rail | Fixed voltage: -6S, - 6X | (Typical) - 3% | 0.75 | (Typical) + 3% | V | | V CCL_HPS_CORE3 | HPS Cortex*-A76 core 3 power rail | SmartVID: -1V, -2V, - 2E, -3V (61) | (Typical) - 3% | 0.70 - 0.90 | (Typical) + 3% | V | | V CCL_HPS_CORE3 | HPS Cortex*-A76 core 3 power rail | Fixed voltage: -4S | (Typical) - 3% | 0.8 | (Typical) + 3% | V | | continued... | continued... | continued... | continued... | continued... | continued... | continued... |

| Symbol | Description | Condition | Minimum | Typical | Maximum | Unit | |-----------------|----------------------------------------------------------------|------------------------------------|----------------|-------------|----------------|--------| | | | Fixed voltage: -5S | (Typical) - 3% | 0.78 | (Typical) + 3% | V | | | | Fixed voltage: -6S, - 6X | (Typical) - 3% | 0.75 | (Typical) + 3% | V | | V CCPLLDIG1_HPS | HPS PLL1 digital power supply (can be connected to V CCL_HPS ) | SmartVID: -1V, -2V, - 2E, -3V (61) | (Typical) - 3% | 0.70 - 0.90 | (Typical) + 3% | V | | V CCPLLDIG1_HPS | HPS PLL1 digital power supply (can be connected to V CCL_HPS ) | Fixed voltage: -4S | (Typical) - 3% | 0.8 | (Typical) + 3% | V | | V CCPLLDIG1_HPS | HPS PLL1 digital power supply (can be connected to V CCL_HPS ) | Fixed voltage: -5S | (Typical) - 3% | 0.78 | (Typical) + 3% | V | | V CCPLLDIG1_HPS | HPS PLL1 digital power supply (can be connected to V CCL_HPS ) | Fixed voltage: -6S, - 6X | (Typical) - 3% | 0.75 | (Typical) + 3% | V | | V CCPLLDIG2_HPS | HPS PLL2 digital power supply (can be connected to V CCL_HPS ) | SmartVID: -1V, -2V, - 2E, -3V (61) | (Typical) - 3% | 0.70 - 0.90 | (Typical) + 3% | V | | V CCPLLDIG2_HPS | HPS PLL2 digital power supply (can be connected to V CCL_HPS ) | Fixed voltage: -4S | (Typical) - 3% | 0.8 | (Typical) + 3% | V | | V CCPLLDIG2_HPS | HPS PLL2 digital power supply (can be connected to V CCL_HPS ) | Fixed voltage: -5S | (Typical) - 3% | 0.78 | (Typical) + 3% | V | | V CCPLLDIG2_HPS | HPS PLL2 digital power supply (can be connected to V CCL_HPS ) | Fixed voltage: -6S, - 6X | (Typical) - 3% | 0.75 | (Typical) + 3% | V | | V CCPLL1_HPS | HPS PLL1 analog power supply | 1.8 V | 1.71 | 1.8 | 1.89 | V | | V CCPLL2_HPS | HPS PLL2 analog power supply | 1.8 V | 1.71 | 1.8 | 1.89 | V | | V CCIO_HPS | HPS I/O buffers power supply | 1.8 V | 1.71 | 1.8 | 1.89 | V |

Related Information

Recommended Operating Conditions on page 22 Provides the steady-state voltage values for the FPGA portion of the device.
HPS Clock Performance on page 107

DC Characteristics

Supply Current and Power Consumption

Altera offers two ways to estimate power for your design-the Power and Thermal Calculator (PTC) and the Quartus ® Prime Power Analyzer feature.

Use the PTC before you start your design to estimate the supply current for your design. The PTC provides a magnitude estimate of the device power because these currents vary greatly with the usage of the resources.

The Quartus Prime Power Analyzer provides better quality estimates based on the specifics of the design after you complete place-and-route. The Power Analyzer can apply a combination of user-entered, simulation-derived, and estimated signal activities that, when combined with detailed circuit models, yield very accurate power estimates.

HSIO DC Characteristics

HSIO I/O Pin Leakage Current

Table 18. HSIO I/O Pin Leakage Current

For specification status, see the Data Sheet Status table

| Symbol | Description | Condition | Min | Max | Unit | |----------|--------------------|-------------------------------|-------|-------|--------| | I I | Input pin | V I = 0 V to V CCIO_PIO (MAX) | -360 | 360 | µA | | I OZ | Tri-stated I/O pin | V O = 0 V to V CCIO_PIO (MAX) | -360 | 360 | µA |

HSIO OCT Calibration Accuracy Specifications

If you enable on-chip termination (OCT) calibration, calibration is automatically performed at power up for I/Os connected to the calibration block.

Table 19. HSIO OCT Calibration Accuracy Specifications

Calibration accuracy for the calibrated on-chip series termination (RS OCT) and on-chip parallel termination (RT OCT) are applicable at the moment of calibration. When process, voltage, and temperature (PVT) conditions change after calibration, the tolerance may change.

These specifications require RZQ reference accuracy of 240 Ω ±1%.

For specification status, see the Data Sheet Status table

| Symbol | Description | Condition (V) | Calibration Accuracy | Unit | |-------------------------------|--------------------------------------------------------------------------------|----------------------------------------------------|------------------------|--------| | 34-Ω and 40-Ω R S (62) | Internal series termination with calibration (34-Ω and 40-Ω setting) | SSTL-12, HSTL-12, HSUL-12, and POD12 I/O standards | 20 | % | | 34-Ω and 40-Ω R S (62) | Internal series termination with calibration (34-Ω and 40-Ω setting) | POD11 and LVSTL11 I/O standards | 20 | % | | 34-Ω and 40-Ω R S (62) | Internal series termination with calibration (34-Ω and 40-Ω setting) | LVSTL105 I/O standard | 20 | % | | 40-Ω R S (62) | Internal series termination with calibration (40-Ω setting) | LVSTL700 I/O standard | 20 | % | | 45-Ω R S | Internal series termination with calibration (45-Ω setting) | DPHY I/O standard | -20 to +25 | % | | 50-Ω and 60-Ω R T (62) | Internal parallel termination with calibration (50-Ω and 60-Ω setting) | SSTL-12 and HSTL-12 I/O standards | 20 | % | | 40-Ω, 50-Ω, and 60-Ω R T (62) | Internal parallel termination with calibration (40-Ω, 50-Ω, and 60- Ω setting) | POD11 and POD12 I/O standards | 20 | % | | 40-Ω, 50-Ω, and 60-Ω R T (62) | Internal parallel termination with calibration (40-Ω, 50-Ω, and 60- Ω setting) | LVSTL11, LVSTL105, and LVSTL700 I/O standards | 20 | % | | 100-Ω R D | Internal differential termination with calibration (100-Ω setting) | DPHY I/O standard | -20 to +25 | % |

HSIO OCT Without Calibration Resistance Tolerance Specifications

Table 20. HSIO OCT Without Calibration Resistance Tolerance Specifications

This table lists the GPIO OCT without calibration resistance tolerance to PVT changes.

For specification status, see the Data Sheet Status table

| Symbol | Description | Condition (V) | Calibration Accuracy | Unit | |------------------------|-------------------------------------------------------------------------|------------------------------------------------------------------|------------------------|--------------| | 34-Ω and 40-Ω R S | Internal series termination without calibration (34-Ω and 40-Ω setting) | 1.3 V LVCMOS I/O standard | 30 | % | | 34-Ω and 40-Ω R S (63) | Internal series termination without calibration (34-Ω and 40-Ω setting) | 1.2 V LVCMOS, SSTL-12, HSTL-12, HSUL-12, and POD12 I/O standards | 25 | % | | 34-Ω and 40-Ω R S (63) | Internal series termination without calibration (34-Ω and 40-Ω setting) | 1.1 V LVCMOS, POD11, and LVSTL11 I/O standards | 25 | % | | 34-Ω and 40-Ω R S (63) | Internal series termination without calibration (34-Ω and 40-Ω setting) | 1.05 V LVCMOS and LVSTL105 I/O standards | 25 | % | | 34-Ω and 40-Ω R S | Internal series termination without calibration (34-Ω and 40-Ω setting) | 1.0 V LVCMOS I/O standard | 30 | % | | 50-Ω R T (63) | Internal parallel termination without calibration (50-Ω setting) | SSTL-12 and HSTL-12 I/O standards | 25 | % | | 50-Ω R T (63) | Internal parallel termination without calibration (50-Ω setting) | POD11 and POD12 I/O standards | 25 | % | | 50-Ω R T (63) | Internal parallel termination without calibration (50-Ω setting) | LVSTL11 and LVSTL105 I/O standards | 25 | % | | 100-Ω R D (64) | Internal differential termination (100-Ω setting) | True differential signaling I/O standard at V CCIO_PIO = 1.05 | 40 | % | | 100-Ω R D (64) | Internal differential termination (100-Ω setting) | True differential signaling I/O standard at V CCIO_PIO = 1.1 | 40 | % | | continued... | continued... | continued... | continued... | continued... |

| Symbol | Description | Condition (V) | Calibration Accuracy | Unit | |-----------|---------------------------------------------------|--------------------------------------------------------------|------------------------|--------| | | | True differential signaling I/O standard at V CCIO_PIO = 1.2 | 40 | % | | | | True differential signaling I/O standard at V CCIO_PIO = 1.3 | 40 | % | | 100-Ω R D | Internal differential termination (100-Ω setting) | SLVS400 I/O standard | 30 | % |

HSIO Pin Capacitance

Table 21. HSIO Pin Capacitance

For specification status, see the Data Sheet Status table

| Symbol | Description | Maximum | Unit | |----------|--------------------------------------|-----------|--------| | C IO | Input/output capacitance of I/O pins | 2.6 (65) | pF |

HSIO Internal Weak Pull-Up Resistor

All I/O pins in GPIO bank have an option to enable weak pull-up when using 1.0 V, 1.05 V, 1.1 V, 1.2 V, and 1.3 V LVCMOS I/O standards.

Table 22. HSIO Internal Weak Pull-Up Resistor

For specification status, see the Data Sheet Status table

| Symbol | Description | Condition (V) | Min | Typ | Max | Unit | |----------|-----------------------------------------------------------------------------------------------------------------------------------------------------------|-----------------------|-------|-------|-------|--------| | R PU | Value of the I/O pin pull-up resistor before and during configuration, as well as user mode if you have enabled the programmable pull-up resistor option. | V CCIO_PIO = 1.3 ±3% | 3 | 10 | 30 | kΩ | | R PU | Value of the I/O pin pull-up resistor before and during configuration, as well as user mode if you have enabled the programmable pull-up resistor option. | V CCIO_PIO = 1.2 ±5% | 3 | 10 | 30 | kΩ | | R PU | Value of the I/O pin pull-up resistor before and during configuration, as well as user mode if you have enabled the programmable pull-up resistor option. | V CCIO_PIO = 1.1 ±5% | 3 | 10 | 30 | kΩ | | R PU | Value of the I/O pin pull-up resistor before and during configuration, as well as user mode if you have enabled the programmable pull-up resistor option. | V CCIO_PIO = 1.05 ±5% | 3 | 10 | 30 | kΩ | | R PU | Value of the I/O pin pull-up resistor before and during configuration, as well as user mode if you have enabled the programmable pull-up resistor option. | V CCIO_PIO = 1.0 ±5% | 3 | 10 | 30 | kΩ |

HVIO DC Characteristics

HVIO I/O Pin Leakage Current

Table 23. HVIO I/O Pin Leakage Current

For specification status, see the Data Sheet Status table

| Symbol | Description | Condition | Min | Max | Unit | |----------|--------------------|--------------------------------|-------|-------|--------| | I I | Input pin | V I = 0 V to V CCIO_HVIO (MAX) | -10 | 10 | μA | | I OZ | Tri-stated I/O pin | V O = 0 V to V CCIO_HVIO (MAX) | -10 | 10 | μA |

HVIO Pin Capacitance

Table 24. HVIO Pin Capacitance

For specification status, see the Data Sheet Status table

| Symbol | Description | Maximum | Unit | |----------|--------------------------------------|-----------|--------| | C IO | Input/output capacitance of I/O pins | 4 (66) | pF |

HVIO Internal Weak Pull-Up and Pull-Down Resistor

Only input and bidirectional pins in HVIO bank have an option to enable weak pull-up and pull-down when using LVCMOS I/O standard.

Table 25. HVIO Internal Weak Pull-Up and Pull-Down Resistor Values

For specification status, see the Data Sheet Status table

| Symbol | Description | Condition (V) | Min | Typ | Max | Unit | |----------|----------------------------------------------------|-----------------|-------|-------|-------|--------| | | programmable pull-up or pull-down resistor option. | | | | | |

HVIO Hysteresis Specifications for Schmitt Trigger Input

Table 26. HVIO Hysteresis Specifications for Schmitt Trigger Input

This device supports built-in Schmitt trigger input that always enabled on HVIO I/O bank. A Schmitt trigger feature introduces hysteresis to the input signal for improved noise immunity, especially for signal with slow edge rate.

For specification status, see the Data Sheet Status table

| Symbol | Description | Condition | Min | Typ | Max | Unit | |----------|--------------------------------------|---------------------|-------|-------|-------|--------| | V HYS | Hysteresis for Schmitt trigger input | V CCIO_HVIO = 1.8 V | - | 200 | - | mV | | V HYS | Hysteresis for Schmitt trigger input | V CCIO_HVIO = 2.5 V | - | 250 | - | mV | | V HYS | Hysteresis for Schmitt trigger input | V CCIO_HVIO = 3.3 V | - | 250 | - | mV |

HPS I/O DC Characteristics

HPS I/O Pin Leakage Current

Table 27. HPS I/O Pin Leakage Current

For specification status, see the Data Sheet Status table

| Symbol | Description | Condition | Min | Max | Unit | |----------|--------------------|-------------------------------|-------|-------|--------| | I I | Input pin | V I = 0 V to V CCIO_HPS (MAX) | -15 | 15 | µA | | | Tri-stated I/O pin | V O = 0 V to V CCIO_HPS (MAX) | -15 | 15 | µA |

HPS I/O Pin Capacitance

Table 28. HPS I/O Pin Capacitance

For specification status, see the Data Sheet Status table

| Symbol | Description | Maximum | Unit | |----------|--------------------------------------|-----------|--------| | C IO | Input/output capacitance of I/O pins | 5 (67) | pF |

HPS I/O Internal Weak Pull-Up Resistor

The I/O pins in HPS bank are supported with weak pull-up and weak pull-down options.

Table 29. HPS Internal Weak Pull-Up Resistor

For specification status, see the Data Sheet Status table

| Symbol | Description | Condition (V) | Min | Typ | Max | Unit | |-------------------------|-------------------------------------------------------------------------------------------------------------------------------------------------|----------------------|--------------|--------------|--------------|--------------| | 20 kΩ R PU , 20 kΩ R PD | Value of the I/O pin pull-up and pull-down resistor during user mode if you have enabled the programmable pull-up or pull-down resistor option. | V CCIO_HPS = 1.8 ±5% | 15 | 20 | 25 | kΩ | | 50 kΩ R PU , 50 kΩ R PD | Value of the I/O pin pull-up and pull-down resistor during user mode if you have enabled the programmable pull-up or pull-down resistor option. | V CCIO_HPS = 1.8 ±5% | 37.5 | 50 | 62.5 | kΩ | | 80 kΩ R PU , 80 kΩ R PD | Value of the I/O pin pull-up and pull-down resistor during user mode if you have enabled the | V CCIO_HPS = 1.8 ±5% | 57 | 80 | 105 | kΩ | | continued... | continued... | continued... | continued... | continued... | continued... | continued... |

HPS I/O Hysteresis Specifications for Schmitt Trigger Input

Table 30. HPS I/O Hysteresis Specifications for Schmitt Trigger Input

This device supports Schmitt trigger input on HPS I/O bank. A Schmitt trigger feature introduces hysteresis to the input signal for improved noise immunity, especially for signal with slow edge rate.

For specification status, see the Data Sheet Status table

| Symbol | Description | Condition | Min | Typ | Max | Unit | |----------|--------------------------------------|--------------------|-------|-------|-------|--------| | V HYS | Hysteresis for Schmitt trigger input | V CCIO_HPS = 1.8 V | 180 | - | - | mV |

SDM I/O DC Characteristics

SDM I/O Pin Leakage Current

Table 31. SDM I/O Pin Leakage Current

For specification status, see the Data Sheet Status table

| Symbol | Description | Condition | Min | Max | Unit | |----------|--------------------|-------------------------------|-------|-------|--------| | I I | Input pin | V I = 0 V to V CCIO_SDM (MAX) | -15 | 15 | µA | | | Tri-stated I/O pin | V O = 0 V to V CCIO_SDM (MAX) | -15 | 15 | µA |

SDM I/O Pin Capacitance

Table 32. SDM I/O Pin Capacitance

For specification status, see the Data Sheet Status table

| Symbol | Description | Maximum | Unit | |----------|--------------------------------------|-----------|--------| | C IO | Input/output capacitance of I/O pins | 5 (68) | pF |

SDM I/O Internal Weak Pull-Up Resistor

The I/O pins in SDM bank are supported with weak pull-up and weak pull-down feature. The weak pull-up and weak pull-down feature is pre-configured according to the configuration mode.

Table 33. SDM I/O Internal Weak Pull-Up Resistor

For specification status, see the Data Sheet Status table

| Symbol | Description | Condition (V) | Min | Typ | Max | Unit | |-------------------------|---------------------------------------------------------------------------|----------------------|-------|-------|-------|--------| | 20 kΩ R PU , 20 kΩ R PD | Value of the I/O pin pull-up and pull-down resistor during configuration. | V CCIO_SDM = 1.8 ±5% | 15 | 20 | 25 | kΩ |

SDM I/O Hysteresis Specifications for Schmitt Trigger Input

Table 34. SDM I/O Hysteresis Specifications for Schmitt Trigger Input

This device supports Schmitt trigger input on SDM I/O bank. A Schmitt trigger feature introduces hysteresis to the input signal for improved noise immunity, especially for signal with slow edge rate.

For specification status, see the Data Sheet Status table

I/O Standard Specifications

HSIO I/O Standard Specifications

Tables in this section list the supported input voltage (VIH and VIL), output voltage (VOH and VOL), and current drive characteristics (IOH and IOL) for various I/O standards.

For minimum voltage values, use the minimum VCCIO_PIO values. For maximum voltage values, use the maximum VCCIO_PIO values.

(68) This value refers to die-level pin capacitance without the device package.

You must perform timing closure analysis to determine the maximum achievable frequency for general-purpose I/O standards.

Related Information

Recommended Operating Conditions on page 22

HSIO Single-Ended I/O Standards Specifications

Table 35. HSIO Single-Ended I/O Standards Specifications

For specification status, see the Data Sheet Status table

| I/O Standard | V CCIO_PIO (V) | V CCIO_PIO (V) | V CCIO_PIO (V) | V IL (V) | V IL (V) | V IH (V) | V IH (V) | V OL (V) (69) | V OH (V) (69) | |----------------|------------------|------------------|------------------|------------|-------------------|-------------------|-------------------|-------------------|-------------------| | I/O Standard | Min | Typ | Max | Min | Max | Min | Max (70) | Max | Min | | 1.3 V LVCMOS | 1.261 | 1.3 | 1.339 | -0.3 | 0.35 × V CCIO_PIO | 0.65 × V CCIO_PIO | V CCIO_PIO + 0.25 | 0.25 × V CCIO_PIO | 0.75 × V CCIO_PIO | | 1.2 V LVCMOS | 1.14 | 1.2 | 1.26 | -0.3 | 0.35 × V CCIO_PIO | 0.65 × V CCIO_PIO | V CCIO_PIO + 0.25 | 0.25 × V CCIO_PIO | 0.75 × V CCIO_PIO | | 1.1 V LVCMOS | 1.045 | 1.1 | 1.155 | -0.3 | 0.35 × V CCIO_PIO | 0.65 × V CCIO_PIO | V CCIO_PIO + 0.25 | 0.25 × V CCIO_PIO | 0.75 × V CCIO_PIO | | 1.05 V LVCMOS | 0.9975 | 1.05 | 1.1025 | -0.3 | 0.35 × V CCIO_PIO | 0.65 × V CCIO_PIO | V CCIO_PIO + 0.25 | 0.25 × V CCIO_PIO | 0.75 × V CCIO_PIO | | 1.0 V LVCMOS | 0.95 | 1 | 1.05 | -0.3 | 0.35 × V CCIO_PIO | 0.65 × V CCIO_PIO | V CCIO_PIO + 0.25 | 0.25 × V CCIO_PIO | 0.75 × V CCIO_PIO |

HSIO Single-Ended SSTL, HSTL, HSUL, POD, and LVSTL I/O Reference Voltage Specifications

Table 36. HSIO Single-Ended SSTL, HSTL, HSUL, POD, and LVSTL I/O Reference Voltage Specifications

For specification status, see the Data Sheet Status table

| I/O Standard | V CCIO_PIO (V) | V CCIO_PIO (V) | V CCIO_PIO (V) | Internal V REF (V) | Internal V REF (V) | Internal V REF (V) | V TT (V) | V TT (V) | V TT (V) | |---------------------------|------------------|------------------|------------------|----------------------|----------------------|----------------------|-------------------|------------------|-------------------| | I/O Standard | Min | Typ | Max | Min | Typ | Max | Min | Typ | Max | | SSTL-12 | 1.14 | 1.2 | 1.26 | 0.49 × V CCIO_PIO | 0.5 × V CCIO_PIO | 0.51 × V CCIO_PIO | 0.45 × V CCIO_PIO | 0.5 × V CCIO_PIO | 0.55 × V CCIO_PIO | | HSTL-12 | 1.14 | 1.2 | 1.26 | 0.47 × V CCIO_PIO | 0.5 × V CCIO_PIO | 0.53 × V CCIO_PIO | 0.45 × V CCIO_PIO | 0.5 × V CCIO_PIO | 0.55 × V CCIO_PIO | | HSUL-12 (71) | 1.14 | 1.2 | 1.26 | 0.49 × V CCIO_PIO | 0.5 × V CCIO_PIO | 0.51 × V CCIO_PIO | 0.45 × V CCIO_PIO | 0.5 × V CCIO_PIO | 0.55 × V CCIO_PIO | | POD12 (GPIO) (72) (73) | 1.164 | 1.2 | 1.236 | 0.69 × V CCIO_PIO | 0.7 × V CCIO_PIO | 0.71 × V CCIO_PIO | - | V CCIO_PIO | - | | POD12 (PHYLITE) (72) (73) | 1.164 | 1.2 | 1.236 | 0.74 × V CCIO_PIO | 0.75 × V CCIO_PIO | 0.76 × V CCIO_PIO | - | V CCIO_PIO | - | | POD11 (GPIO) (72) (73) | 1.067 | 1.1 | 1.133 | 0.69 × V CCIO_PIO | 0.7 × V CCIO_PIO | 0.71 × V CCIO_PIO | - | V CCIO_PIO | - | | POD11 (PHYLITE) (72) (73) | 1.067 | 1.1 | 1.133 | 0.74 × V CCIO_PIO | 0.75 × V CCIO_PIO | 0.76 × V CCIO_PIO | - | V CCIO_PIO | - | | continued... | continued... | continued... | continued... | continued... | continued... | continued... | continued... | continued... | continued... |

| I/O Standard | V CCIO_PIO (V) | V CCIO_PIO (V) | V CCIO_PIO (V) | Internal V REF (V) | Internal V REF (V) | Internal V REF (V) | V TT (V) | V TT (V) | V TT (V) | |----------------|------------------|------------------|------------------|----------------------|----------------------|----------------------|------------|------------|------------| | | Min | Typ | Max | Min | Typ | Max | Min | Typ | Max | | LVSTL11 (72) | 1.067 | 1.1 | 1.133 | 0.24 × V CCIO_PIO | 0.25 × V CCIO_PIO | 0.26 × V CCIO_PIO | - | GND | - | | LVSTL105 (72) | 1.0185 | 1.05 | 1.0815 | 0.24 × V CCIO_PIO | 0.25 × V CCIO_PIO | 0.26 × V CCIO_PIO | - | GND | - | | LVSTL700 | 1.0185 | 1.05 | 1.0815 | 0.174 × V CCIO_PIO | 0.184 × V CCIO_PIO | 0.194 × V CCIO_PIO | - | GND | - |

HSIO Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications

Table 37. HSIO Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications

For specification status, see the Data Sheet Status table

| I/O Standard | V IL(DC) (V) | V IH(DC) (V) | V IL(AC) (V) | V IH(AC) (V) | |----------------|----------------|----------------|----------------|----------------| | | Max | Min | Max | Min | | SSTL-12 | V REF - 0.075 | V REF + 0.075 | V REF - 0.100 | V REF + 0.100 | | HSTL-12 | V REF - 0.080 | V REF + 0.080 | V REF - 0.150 | V REF + 0.150 | | HSUL-12 | V REF - 0.100 | V REF + 0.100 | V REF - 0.135 | V REF + 0.135 | | POD12 | V REF - 0.055 | V REF + 0.055 | V REF - 0.070 | V REF + 0.070 | | POD11 | V REF - 0.055 | V REF + 0.055 | V REF - 0.070 | V REF + 0.070 |

Note:

For output voltage swing calculation example, refer to the General-Purpose I/O User Guide for this device. Differential voltage referenced I/O standard uses two single-ended outputs with second output programmed as inverted.

Note:

For eye height position estimation in EMIF interfaces, refer to the PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex ™ 5 FPGAs and SoCs . The eye mask estimation methodology defined in the PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex ™ 5 FPGAs and SoCs takes precedence over specifications in HSIO Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications table.

Related Information

General-Purpose I/O User Guide: Agilex ™ 5 FPGAs and SoCs

PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex ™ 5 FPGAs and SoCs Provides eye mask estimation for EMIF interfaces.

HSIO Single-Ended LVSTL I/O Standards Specifications

Table 38. HSIO Single-Ended LVSTL I/O Standards Specifications

For specification status, see the Data Sheet Status table

| I/O Standard | V CCIO_PIO (V) | V CCIO_PIO (V) | V CCIO_PIO (V) | V IL(DC) (V) | V IH(DC) (V) | V IL(AC) (V) | V IH(AC) (V) | |----------------|------------------|------------------|------------------|----------------|----------------|----------------|----------------| | I/O Standard | Min | Typ | Max | Max | Min | Max | Min | | LVSTL11 (74) | 1.067 | 1.1 | 1.133 | V REF - 0.055 | V REF + 0.055 | V REF - 0.070 | V REF + 0.070 | | LVSTL105 (74) | 1.0185 | 1.05 | 1.0815 | V REF - 0.055 | V REF + 0.055 | V REF - 0.070 | V REF + 0.070 | | LVSTL700 | 1.0185 | 1.05 | 1.0815 | V REF - 0.055 | V REF + 0.055 | V REF - 0.070 | V REF + 0.070 |

Note:

For eye height position estimation in EMIF interfaces, refer to the PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex ™ 5 FPGAs and SoCs. The eye mask estimation methodology defined in the PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex ™ 5 FPGAs and SoCs takes precedence over specifications in HSIO Single-Ended LVSTL I/O Standards Specifications table.

Related Information

PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex ™ 5 FPGAs and SoCs

(74) Each sub-bank can only support a single voltage tolerance. The VCCIO_PIO tolerance can be extended to ±5% if the entire HSIO subbank is operating in any of the following modes. Else, you must supply the VCCIO_PIO voltage rail with a ±3% voltage supply tolerance.

· PHYLITE mode

· GPIO mode

HSIO Differential SSTL, HSTL, and HSUL I/O Standards Specifications

Table 39. HSIO Differential SSTL, HSTL, and HSUL I/O Standards Specifications

For specification status, see the Data Sheet Status table

| I/O Standard | V CCIO_PIO (V) | V CCIO_PIO (V) | V CCIO_PIO (V) | V ILdiff(DC) (V) | V IHdiff(DC) (V) | V ILdiff(AC) (V) | V IHdiff(AC) (V) | V IX(AC) (V) | V IX(AC) (V) | V IX(AC) (V) | V OX(AC) (V) | V OX(AC) (V) | V OX(AC) (V) | |----------------|------------------|------------------|------------------|--------------------|--------------------|--------------------|--------------------|-------------------------|------------------|-------------------------|-------------------------|------------------|-------------------------| | I/O Standard | Min | Typ | Max | Max | Min | Max | Min | Min | Typ | Max | Min | Typ | Max | | SSTL-12 (7 5) | 1.14 | 1.2 | 1.26 | -0.15 | 0.15 | -0.2 | 0.2 | 0.5 × V CCIO_PIO - 0.12 | 0.5 × V CCIO_PIO | 0.5 × V CCIO_PIO + 0.12 | 0.5 × V CCIO_PIO - 0.12 | 0.5 × V CCIO_PIO | 0.5 × V CCIO_PIO + 0.12 | | HSTL-12 (7 5) | 1.14 | 1.2 | 1.26 | -0.16 | 0.16 | -0.3 | 0.3 | 0.5 × V CCIO_PIO - 0.12 | 0.5 × V CCIO_PIO | 0.5 × V CCIO_PIO + 0.12 | 0.5 × V CCIO_PIO - 0.12 | 0.5 × V CCIO_PIO | 0.5 × V CCIO_PIO + 0.12 | | HSUL-12 ( 75) | 1.14 | 1.2 | 1.26 | -0.2 | 0.2 | -0.27 | 0.27 | 0.5 × V CCIO_PIO - 0.12 | 0.5 × V CCIO_PIO | 0.5 × V CCIO_PIO + 0.12 | 0.5 × V CCIO_PIO - 0.12 | 0.5 × V CCIO_PIO | 0.5 × V CCIO_PIO + 0.12 |

HSIO Differential POD I/O Standards Specifications

Table 40. HSIO Differential POD I/O Standards Specifications

For specification status, see the Data Sheet Status table

| I/O Standard | V CCIO_PIO (V) | V CCIO_PIO (V) | V CCIO_PIO (V) | V ILdiff(DC) (V) | V IHdiff(DC) (V) | V ILdiff(AC) (V) | V IHdiff(AC) (V) | V IX(AC) (%) (76) | |----------------|------------------|------------------|------------------|--------------------|--------------------|--------------------|--------------------|---------------------| | I/O Standard | Min | Typ | Max | Max | Min | Max | Min | Max | | POD12 (77) | 1.164 | 1.2 | 1.236 | -0.11 | 0.11 | -0.14 | 0.14 | 25 | | POD11 (77) | 1.067 | 1.1 | 1.133 | -0.11 | 0.11 | -0.14 | 0.14 | 25 |

Note:

For eye height position estimation in EMIF interfaces, refer to the PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex ™ 5 FPGAs and SoCs . The eye mask estimation methodology defined in the PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex ™ 5 FPGAs and SoCs takes precedence over specifications in HSIO Differential POD I/O Standards Specifications table.

Related Information

PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex ™ 5 FPGAs and SoCs Provides eye mask estimation for EMIF interfaces.

HSIO Differential LVSTL I/O Standards Specifications

Table 41. HSIO Differential LVSTL I/O Standards Specifications

For specification status, see the Data Sheet Status table

| I/O Standard | V CCIO_PIO (V) | V CCIO_PIO (V) | V CCIO_PIO (V) | V ILdiff(DC) (V) | V IHdiff(DC) (V) | V ILdiff(AC) (V) | V IHdiff(AC) (V) | V IX(AC) (%) (78) | |----------------|------------------|------------------|------------------|--------------------|--------------------|--------------------|--------------------|---------------------| | I/O Standard | Min | Typ | Max | Max | Min | Max | Min | Max | | LVSTL11 (79) | 1.067 | 1.1 | 1.133 | -0.11 | 0.11 | -0.14 | 0.14 | 25 | | LVSTL105 (79) | 1.0185 | 1.05 | 1.0815 | -0.11 | 0.11 | -0.14 | 0.14 | 25 | | LVSTL700 | 1.0185 | 1.05 | 1.0815 | -0.11 | 0.11 | -0.14 | 0.14 | 25 |

PHYLITE mode
GPIO mode

(78) Percentage of P-leg and N-leg crossing relative to the midpoint of P-leg and N-leg signal swings.

(79) Each sub-bank can only support a single voltage tolerance. The VCCIO_PIO tolerance can be extended to ±5% if the entire HSIO subbank is operating in any of the following modes. Else, you must supply the VCCIO_PIO voltage rail with a ±3% voltage supply tolerance.

PHYLITE mode
GPIO mode

Note:

For eye height position estimation in EMIF interfaces, refer to the PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex ™ 5 FPGAs and SoCs. The eye mask estimation methodology defined in the PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex ™ 5 FPGAs and SoCs takes precedence over specifications in HSIO Differential LVSTL I/O Standards Specifications table.

Related Information

PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex ™ 5 FPGAs and SoCs

HSIO Differential I/O Standards Specifications

Table 42. HSIO Differential I/O Standards Specifications

For specification status, see the Data Sheet Status table

| I/O Standard | V CCIO_PIO (V) | V CCIO_PIO (V) | V CCIO_PIO (V) | V ID (mV) | V ID (mV) | V ICM(DC) (V) | V ICM(DC) (V) | V ICM(DC) (V) | V OD (mV) (80) | V OD (mV) (80) | V OD (mV) (80) | V OCM (V) (80) | V OCM (V) (80) | V OCM (V) (80) | |------------------------------------------------------------------------|------------------|------------------|------------------|--------------|--------------|-----------------|-----------------|-----------------|------------------|------------------|------------------|------------------|------------------|------------------| | I/O Standard | Min | Typ | Max | Min | Max | Min | Typ | Max | Min | Typ | Max | Min | Typ | Max | | True Differenti al Signaling -1.3 V (LVDS compatib le Transmitt er and | 1.261 | 1.3 | 1.339 | 100 | 500 | 0.5 | - | 1.40 (84) | 247 | - | 454 | 0.9 | 1 | 1.1 | | continued... | continued... | continued... | continued... | continued... | continued... | continued... | continued... | continued... | continued... | continued... | continued... | continued... | continued... | continued... |

| I/O Standard | V CCIO_PIO (V) | V CCIO_PIO (V) | V CCIO_PIO (V) | V ID (mV) | V ID (mV) | V ICM(DC) (V) | V ICM(DC) (V) | V ICM(DC) (V) | V OD (mV) (80) | V OD (mV) (80) | V OD (mV) (80) | V OCM (V) (80) | V OCM (V) (80) | V OCM (V) (80) | |----------------------------------------------------------|------------------|------------------|------------------|--------------|--------------|-----------------|-----------------|-----------------|------------------|------------------|------------------|------------------|------------------|------------------| | I/O Standard | Min | Typ | Max | Min | Max | Min | Typ | Max | Min | Typ | Max | Min | Typ | Max | | Receiver) (81) (82) (83) | | | | | | | | | | | | | | | | True Differenti al Signaling -1.2 V (Receiver only) (81) | 1.14 | 1.2 | 1.26 | 100 | 454 | 0.8 | - | 0.95 | - | - | - | - | - | - | | True Differenti al Signaling -1.1 V (Receiver only) (81) | 1.045 | 1.1 | 1.155 | 100 | 454 | 0.8 | - | 0.95 | - | - | - | - | - | - | | continued... | continued... | continued... | continued... | continued... | continued... | continued... | continued... | continued... | continued... | continued... | continued... | continued... | continued... | continued... |

| I/O Standard | V CCIO_PIO (V) | V CCIO_PIO (V) | V CCIO_PIO (V) | V ID (mV) | V ID (mV) | V ICM(DC) (V) | V ICM(DC) (V) | V ICM(DC) (V) | V OD (mV) (80) | V OD (mV) (80) | V OD (mV) (80) | V OCM (V) (80) | V OCM (V) (80) | V OCM (V) (80) | |-----------------------------------------------------------|------------------|------------------|------------------|-------------|-------------|-----------------|-----------------|-----------------|------------------|------------------|------------------|------------------|------------------|------------------| | I/O Standard | Min | Typ | Max | Min | Max | Min | Typ | Max | Min | Typ | Max | Min | Typ | Max | | True Differenti al Signaling -1.05 V (Receiver only) (81) | 0.9975 | 1.05 | 1.1025 | 100 | 454 | 0.8 | - | 0.95 | - | - | - | - | - | - | | SLVS400 | 1.164 | 1.2 | 1.236 | 70 | - | 0.07 | 0.2 | 0.33 | - | - | - | - | - | - | | SLVS400 | 1.067 | 1.1 | 1.133 | 70 | - | 0.07 | 0.2 | 0.33 | - | - | - | - | - | - |

Related Information

General-Purpose I/O User Guide: Agilex ™ 5 FPGAs and SoCs
LVDS SERDES User Guide: Agilex ™ 5 FPGAs and SoCs
AN 555: True Differential Signaling Termination and Biasing for Agilex ™ 7 M-Series, Agilex ™ 5, and Agilex ™ 3 FPGAs

(80) RL range: 90 ≤ RL ≤ 110 Ω.

(81) The True Differential Signaling input buffer is supported on 1.05 V, 1.1 V, 1.2 V, and 1.3 V VCCIO_PIO banks. The maximum input voltage driven into the True Differential Signaling input buffer must not exceed VICM(max) + VID(max)/2.

(82) True Differential Signaling - 1.3 V standard is compatible with LVDS and capable to interface with LVDS subsets such as:

· RSDS

· Mini-LVDS

· Any I/O standards using equivalent electrical specifications

(83) For further information on True Differential Signaling - 1.3 V feature support and guidelines on interfacing True Differential Signaling -1.3V standard with LVDS and its subset compliant standards, refer to the related information.

(84) The VICM(DC) voltage must not exceed 1.2 V when on-chip differential termination (RD OCT) is disabled with the use of external onboard termination.

MIPI D-PHY I/O Standards Specifications

Table 43. D-Series FPGAs MIPI D-PHY Low-Power I/O Standards Specifications

For specification status, see the Data Sheet Status table

| I/O Standard | Note | V CCIO_PIO (V) | V CCIO_PIO (V) | V CCIO_PIO (V) | V IL (V) | V IL (V) | IH (V) | IH (V) | V OH (V) | V OH (V) | V OH (V) | V OL (V) | V OL (V) | V OL (V) | |----------------|---------------------------------------------------------------------------------------|------------------|------------------|------------------|------------|------------|----------|----------|------------|------------|------------|------------|------------|------------| | I/O Standard | Note | Min | Typ | Max | Min | Max | Min | Max | Min | Typ | Max | Min | Typ | Max | | DPHY | Applicabl e for low power when the supporte d High Speed data rate 150Mbps to 3.5Gbps | 1.164 | 1.2 | 1.236 | - | 0.55 | 0.74 | - | 1.1 | 1.2 | 1.3 | -0.05 | - | 0.05 | | DPHY | Applicabl e for low power when the supporte d High Speed data rate 150Mbps to 3.5Gbps | 1.067 | 1.1 | 1.133 | - | 0.55 | 0.74 | - | 0.95 (85) | 1.1 (85) | 1.2 (85) | -0.05 | - | 0.05 |

Table 44. D-Series FPGAs MIPI D-PHY High-Speed I/O Standards Specifications

For specification status, see the Data Sheet Status table

| I/O Standa rd | Conditi on | V CCIO_PIO (V) | V CCIO_PIO (V) | V CCIO_PIO (V) | V ID (V) | V ID (V) | V ICM(DC) (V) | V ICM(DC) (V) | V ICM(DC) (V) | V OD(DC) (V) | V OD(DC) (V) | V OD(DC) (V) | V OCM (V) | V OCM (V) | V OCM (V) | V ILHS (V) | V IHHS (V) | |-----------------|----------------------------------|------------------|------------------|------------------|------------|------------|-----------------|-----------------|-----------------|----------------|----------------|----------------|-------------|-------------|-------------|--------------|--------------| | I/O Standa rd | Conditi on | Min | Typ | Max | Min | Max | Min | Typ | Max | Min | Typ | Max | Min | Typ | Max | Min | Max | | DPHY | Data rate ≤ 1.5 Gbps | 1.164 | 1.2 | 1.236 | 0.07 | - | 0.07 | - | 0.33 | 0.14 | 0.2 | 0.27 | 0.15 | 0.2 | 0.25 | -0.04 | 0.46 | | DPHY | Data rate > 1.5 Gbps to 3.5 Gbps | 1.164 | 1.2 | 1.236 | 0.04 | - | 0.07 | - | 0.33 | 0.14 | 0.2 | 0.27 | 0.15 | 0.2 | 0.25 | -0.04 | 0.46 | | DPHY | Data rate ≤ 1.5 Gbps | 1.067 | 1.1 | 1.133 | 0.07 | - | 0.07 | - | 0.33 | 0.14 | 0.2 | 0.27 | 0.15 | 0.2 | 0.25 | -0.04 | 0.46 | | DPHY | Data rate > 1.5 Gbps to 3.5 Gbps | 1.067 | 1.1 | 1.133 | 0.04 | - | 0.07 | - | 0.33 | 0.14 | 0.2 | 0.27 | 0.15 | 0.2 | 0.25 | -0.04 | 0.46 |

Table 45. E-Series FPGAs MIPI D-PHY Low-Power I/O Standards Specifications

For specification status, see the Data Sheet Status table

| I/O Standar | Device Group | Note | V CCIO_PIO (V) | V CCIO_PIO (V) | V CCIO_PIO (V) | V IL (V) | V IL (V) | V IH (V) | V IH (V) | V OH (V) | V OH (V) | V OH (V) | V OL (V) | V OL (V) | V OL (V) | |---------------|----------------|---------------------|------------------|------------------|------------------|--------------|--------------|--------------|--------------|--------------|--------------|--------------|--------------|--------------|--------------| | d | | | Min | Typ | Max | Min | Max | Min | Max | Min | Typ | Max | Min | Typ | Max | | DPHY | A | Applicab le for low | 1.164 | 1.2 | 1.236 | - | 0.55 | 0.74 | - | 1.1 | 1.2 | 1.3 | -0.05 | - | 0.05 | | continued... | continued... | continued... | continued... | continued... | continued... | continued... | continued... | continued... | continued... | continued... | continued... | continued... | continued... | continued... | continued... |

| I/O Standar | Device Group | Note | V CCIO_PIO (V) | V CCIO_PIO (V) | V CCIO_PIO (V) | V IL (V) | V IL (V) | V IH (V) | V IH (V) | V OH (V) | V OH (V) | V OH (V) | V OL (V) | V OL (V) | V OL (V) | |---------------|----------------|-----------------------------------------------------------------------------------------|------------------|------------------|------------------|------------|------------|------------|------------|------------|------------|------------|--------------|--------------|--------------| | d | | | Min | Typ | Max | Min | Max | Min | Max | Min | Typ | Max | Min | Typ | Max | | | | ed High Speed data rate 150 Mbps to 3.5 Gbps | | | | | | | | | | 1.2 (86) | | | | | | | Applicab le for low power when the support ed High Speed data rate 150 Mbps to 3.5 Gbps | 1.067 | 1.1 | 1.133 | | | | | 0.95 (86) | 1.1 (86) | | | | | | | B | Applicab le for low power when the support ed High | 1.164 | 1.2 | 1.236 | - | 0.55 | 0.74 | - | 1.1 | 1.2 | 1.3 | -0.05 | - | 0.05 | | | B | Applicab le for | 1.067 | 1.1 | 1.133 | | | | | 0.95 (86) | 1.1 (86) | 1.2 (86) | -0.05 | - | 0.05 | | | | | | | | | | | | | | | continued... | continued... | continued... |

| I/O Standar d | Device Group | Note | V CCIO_PIO (V) | V CCIO_PIO (V) | V CCIO_PIO (V) | V IL (V) | V IL (V) | V IH (V) | V IH (V) | V OH (V) | V OH (V) | V OH (V) | V OL (V) | V OL (V) | V OL (V) | |-----------------|----------------|-------------------------------------------------------------------------|------------------|------------------|------------------|------------|------------|------------|------------|------------|------------|------------|------------|------------|------------| | I/O Standar d | Device Group | Note | Min | Typ | Max | Min | Max | Min | Max | Min | Typ | Max | Min | Typ | Max | | | | low power when the support ed High Speed data rate 150 Mbps to 2.5 Gbps | | | | | | | | | | | | | |

Table 46. E-Series FPGAs MIPI D-PHY High-Speed I/O Standards Specifications

For specification status, see the Data Sheet Status table

| I/O Standa rd | Condition | Condition | V CCIO_PIO (V) | V CCIO_PIO (V) | V CCIO_PIO (V) | V ID (V) | V ID (V) | V ICM(DC) (V) | V ICM(DC) (V) | V ICM(DC) (V) | V OD(DC) (V) | V OD(DC) (V) | V OD(DC) (V) | V OCM (V) | V OCM (V) | V OCM (V) | V ILHS (V) | V IHHS (V) | |-----------------|--------------|----------------------------------|------------------|------------------|------------------|--------------|--------------|-----------------|-----------------|-----------------|----------------|----------------|----------------|--------------|--------------|--------------|--------------|--------------| | I/O Standa rd | Device Group | Data Rate | Min | Typ | Max | Min | Max | Min | Typ | Max | Min | Typ | Max | Min | Typ | Max | Min | Max | | | A | Data rate ≤ 1.5 Gbps | 1.164 | 1.2 | 1.236 | 0.07 | - | 0.07 | - | 0.33 | 0.14 | 0.2 | 0.27 | 0.15 | 0.2 | 0.25 | -0.04 | 0.46 | | | A | Data rate > 1.5 Gbps to 3.5 Gbps | 1.164 | 1.2 | 0.04 | 0.07 | - | 0.07 | - | 0.33 | 0.14 | 0.2 | 0.27 | 0.15 | 0.2 | 0.25 | -0.04 | 0.46 | | | A | Data rate ≤ 1.5 Gbps | 1.067 | 1.1 | 1.133 0.07 | 0.07 | - | 0.07 | - | 0.33 | 0.14 | 0.2 | 0.27 | 0.15 | 0.2 | 0.25 | -0.04 | 0.46 | | | A | Data rate > 1.5 | 1.067 | 1.1 | 0.04 | 0.07 | - | 0.07 | - | 0.33 | 0.14 | 0.2 | 0.27 | 0.15 | 0.2 | 0.25 | -0.04 | 0.46 | | continued... | continued... | continued... | continued... | continued... | continued... | continued... | continued... | continued... | continued... | continued... | continued... | continued... | continued... | continued... | continued... | continued... | continued... | continued... |

| I/O Standa rd | Condition | Condition | V CCIO_PIO (V) | V CCIO_PIO (V) | V CCIO_PIO (V) | V ID (V) V ICM(DC) | V ID (V) V ICM(DC) | V ID (V) V ICM(DC) | (V) | (V) | V OD(DC) (V) | V OD(DC) (V) | V OD(DC) (V) | V OCM (V) | V OCM (V) | V ILHS (V) | V IHHS (V) | |-----------------|--------------|----------------------------------|------------------|------------------|------------------|----------------------|----------------------|----------------------|-------|-------|----------------|----------------|----------------|-------------|-------------|--------------|--------------| | I/O Standa rd | Device Group | Data Rate | Min | Typ | Max | Min | Min | | Typ | Max | Min | Typ | Max | Min | Max | Min | Max | | | | Gbps to 3.5 Gbps | | | | | | | | | | | | | | | | | | B | Data rate ≤ 1.5 Gbps | 1.164 1.2 | 1.236 | 0.07 | - | 0.07 | - | 0.33 | 0.14 | 0.2 | 0.27 | 0.15 | 0.2 | 0.25 | -0.04 | 0.46 | | | B | Data rate > 1.5 Gbps to 2.5 Gbps | 1.164 1.2 | 1.236 | 0.04 | - | 0.07 | - | 0.33 | 0.14 | 0.2 | 0.27 | 0.15 | 0.2 | 0.25 | -0.04 | 0.46 | | | B | Data rate ≤ 1.5 Gbps | 1.067 | 1.1 1.133 | 0.07 | - | 0.07 | - | 0.33 | 0.14 | 0.2 | 0.27 | 0.15 | 0.2 | 0.25 | -0.04 | 0.46 | | | B | Data rate > 1.5 Gbps to 2.5 Gbps | 1.067 | 1.1 1.133 | 0.04 | - | 0.07 | - | 0.33 | 0.14 | 0.2 | 0.27 | 0.15 | 0.2 | 0.25 | -0.04 | 0.46 |

HVIO I/O Standard Specifications

Related Information

Recommended Operating Conditions on page 22

HVIO Single-Ended I/O Standards Specifications

Table 47. HVIO Single-Ended I/O Standards Specifications

For specification status, see the Data Sheet Status table

| I/O Standard | V CCIO_HVIO (V) | V CCIO_HVIO (V) | V CCIO_HVIO (V) | V IL (V) | V IL (V) | V IH (V) | V IH (V) | V OL (V) (87) | V OH (V) (87) | |--------------------------|-------------------|-------------------|-------------------|------------|---------------|---------------|--------------|-----------------|-----------------| | | Min | Typ | Max | Min | Max | Min | Max | Max | Min | | 1.8 V LVCMOS 1.8 V LVTTL | 1.746 | 1.8 | 1.854 | -0.3 | 0.35 × V CCIO | 0.65 × V CCIO | V CCIO + 0.3 | 0.45 | V CCIO - 0.45 | | 2.5 V LVCMOS 2.5 V LVTTL | 2.425 | 2.5 | 2.575 | -0.3 | 0.7 | 1.7 | V CCIO + 0.3 | 0.4 | 2 | | 3.3 V LVCMOS 3.3 V LVTTL | 3.201 | 3.3 | 3.399 | -0.3 | 0.8 | 2 | V CCIO + 0.3 | 0.4 | 2.4 |

HPS I/O Standard Specifications

Tables in this section list the supported input voltage (VIH and VIL), output voltage (VOH and VOL), and current drive characteristics (IOH and IOL) for various I/O standards.

For minimum voltage values, use the minimum VCCIO_HPS values. For maximum voltage values, use the maximum VCCIO_HPS values.

You must perform timing closure analysis to determine the maximum achievable frequency for general purpose I/O standards.

(87) Applicable to test condition of IOH and IOL at 3 mA.

HPS Single-Ended I/O Standards Specifications

Table 48. HPS Single-Ended I/O Standards Specifications

For specification status, see the Data Sheet Status table

| I/O Standard | V CCIO_HPS | V CCIO_HPS | V CCIO_HPS | V IL (V) | V IL (V) | V IH (V) | V IH (V) | V OL (V) | V OH (V) | I OL (mA) (88) | I OH (mA) (88) | |----------------|--------------|--------------|--------------|------------|-------------------|-------------------|------------------|------------|------------------|------------------|------------------| | | Min | Typ | Max | Min | Max | Min | Max | Max | Min | Max | Min | | 1.8 V LVCMOS | 1.71 | 1.8 | 1.89 | -0.3 | 0.35 × V CCIO_HPS | 0.65 × V CCIO_HPS | V CCIO_HPS + 0.3 | 0.4 | V CCIO_HPS - 0.4 | 8 | -8 |

SDM I/O Standard Specifications

Tables in this section list the supported input voltage (VIH and VIL), output voltage (VOH and VOL), and current drive characteristics (IOH and IOL) for various I/O standards.

For minimum voltage values, use the minimum VCCIO_SDM values. For maximum voltage values, use the maximum VCCIO_SDM values.

SDM Single-Ended I/O Standards Specifications

Table 49. SDM Single-Ended I/O Standards Specifications

For specification status, see the Data Sheet Status table

| I/O Standard | V CCIO_SDM (V) | V CCIO_SDM (V) | V CCIO_SDM (V) | V IL (V) | V IL (V) | V IH (V) | V IH (V) | V OL (V) | V OH (V) | I OL (mA) (89) | I OH (mA) (89) | |----------------|------------------|------------------|------------------|------------|-------------------|-------------------|------------------|------------|------------------|------------------|------------------| | | Min | Typ | Max | Min | Max | Min | Max | Max | Min | Max | Min | | 1.8 V LVCMOS | 1.71 | 1.8 | 1.89 | -0.3 | 0.35 × V CCIO_SDM | 0.65 × V CCIO_SDM | V CCIO_SDM + 0.3 | 0.4 | V CCIO_SDM - 0.4 | 8 | -8 |

Switching Characteristics

This section provides the performance characteristics of core and periphery blocks.

Core Performance Specifications

Clock Tree Specifications

Table 50. D-Series FPGAs Clock Tree Performance Specifications

For specification status, see the Data Sheet Status table

| Parameter | Performance | Performance | Unit | |----------------------------|---------------|---------------|--------| | | -1V, -2V | -3V | | | Programmable clock routing | 1,000 | 780 | MHz |

Table 51. E-Series FPGAs Clock Tree Performance Specifications

For specification status, see the Data Sheet Status table

| Parameter | Performance | Performance | Performance | Performance | Performance | Unit | |----------------------------|---------------|---------------|---------------|---------------|---------------|--------| | Parameter | -1V, -2V, -2E | -3V | -4S | -5S | -6S, -6X | | | Programmable clock routing | 1,000 | 780 | 850 | 710 | 554 | MHz |

I/O PLL Specifications

Table 52. D-Series FPGAs I/O PLL Specifications

For specification status, see the Data Sheet Status table

| Symbol | Parameter | Condition | Minimum | Typical | Maximum | Unit | |--------------|------------------------------------------------------------------------------|--------------|--------------|--------------|--------------|--------------| | f IN | Input clock frequency source from core clock input and reference clock input | -1V | 10 | - | 1,100 (90) | MHz | | f IN | Input clock frequency source from core clock input and reference clock input | -2V | 10 | - | 900 (90) | MHz | | f IN | Input clock frequency source from core clock input and reference clock input | -3V | 10 | - | 625 (90) | MHz | | f IN | Input clock frequency source from HSIO clock input | -1V | 10 | - | 800 (90) | MHz | | f IN | Input clock frequency source from HSIO clock input | -2V | 10 | - | 717 (90) | MHz | | f IN | Input clock frequency source from HSIO clock input | -3V | 10 | - | 625 (90) | MHz | | f IN | Input clock frequency source from HVIO clock input | - | 10 | - | 156.25 (90) | MHz | | f INPFD | Input clock frequency to the PFD | - | 10 | - | 325 | MHz | | f VCO | I/O PLL VCO operating range | -1V | 600 | - | 3,200 | MHz | | f VCO | I/O PLL VCO operating range | -2V | 600 | - | 3,200 | MHz | | f VCO | I/O PLL VCO operating range | -3V | 600 | - | 2,400 | MHz | | f CLBW | I/O PLL closed-loop bandwidth | - | 0.5 | - | 20 | MHz | | f OUT | Output frequency for internal clock ( C counter) | -1V | - | - | 1,100 | MHz | | f OUT | Output frequency for internal clock ( C counter) | -2V | - | - | 1,000 | MHz | | f OUT | Output frequency for internal clock ( C counter) | -3V | - | - | 780 | MHz | | continued... | continued... | continued... | continued... | continued... | continued... | continued... |

| Symbol | Parameter | Condition | Minimum | Typical | Maximum | Unit | |------------------|------------------------------------------------------------------------------------------------------------|---------------------|--------------|--------------|--------------|--------------| | f OUT_EXT | Output frequency for external clock output | -1V | - | - | 800 | MHz | | f OUT_EXT | Output frequency for external clock output | -2V | - | - | 717 | MHz | | f OUT_EXT | Output frequency for external clock output | -3V | - | - | 625 | MHz | | t OUTDUTY | Duty cycle for dedicated external clock output (when set to 50%) | f OUT_EXT < 300 MHz | 45 | 50 | 55 | % | | t OUTDUTY | Duty cycle for dedicated external clock output (when set to 50%) | f OUT_EXT ≥ 300 MHz | 40/45 (91) | 50 | 55 (91) /60 | % | | t FCOMP (92) | External feedback clock compensation time | - | - | - | 5 | ns | | f DYCONFIGCLK | Dynamic configuration clock | - | - | - | 100 | MHz | | t LOCK | Time required to lock from end-of-device configuration or deassertion of areset | - | - | - | 1 | ms | | t DLOCK | Time required to lock dynamically (after switchover or reconfiguring any non- post-scale counters/ delays) | - | - | - | 1 | ms | | t PLL_PSERR (93) | Accuracy of PLL phase shift | - | - | - | ±50 | ps | | t ARESET | Minimum pulse width on the areset signal | - | 10 | - | - | ns | | continued... | continued... | continued... | continued... | continued... | continued... | continued... |

| Symbol | Parameter | Condition | Minimum | Typical | Maximum | Unit | |----------------------|------------------------------------------|--------------------------------------------------------------------------|--------------|--------------|--------------|--------------| | t INCCJ | Input clock cycle-to- cycle jitter | f REF < 100 MHz (94) | - | - | ±750 | ps (p-p) | | t INCCJ | Input clock cycle-to- cycle jitter | f REF ≥ 100 MHz (94) | - | - | 0.15 | UI (p-p) | | t REFPJ | Reference phase jitter (rms) (95) | Carrier frequency: 100 MHz with integrated bandwidth of 10 kHz to 50 MHz | - | - | 1.42 | ps | | t REFPN | Reference phase noise (96) (95) | 10 Hz | - | - | -90 | dBc/Hz | | t REFPN | Reference phase noise (96) (95) | 100 Hz | - | - | -100 | dBc/Hz | | t REFPN | Reference phase noise (96) (95) | 1 kHz | - | - | -110 | dBc/Hz | | t REFPN | Reference phase noise (96) (95) | 10 kHz | - | - | -120 | dBc/Hz | | t REFPN | Reference phase noise (96) (95) | 100 kHz | - | - | -130 | dBc/Hz | | t REFPN | Reference phase noise (96) (95) | 1 MHz | - | - | -138 | dBc/Hz | | t REFPN | Reference phase noise (96) (95) | 10 MHz | - | - | -142 | dBc/Hz | | t REFPN | Reference phase noise (96) (95) | 100 MHz | - | - | -144 | dBc/Hz | | t OUTPJ_DC (92) (97) | Period jitter for dedicated clock output | f OUT < 100 MHz (94) | - | - | 17.5 | mUI (p-p) | | t OUTPJ_DC (92) (97) | Period jitter for dedicated clock output | f OUT ≥ 100 MHz (94) | - | - | 175 | ps (p-p) | | continued... | continued... | continued... | continued... | continued... | continued... | continued... |

| Symbol | Parameter | Condition | Minimum | Typical | Maximum | Unit | |-----------------------|-----------------------------------------------------------|--------------------------|-----------|-----------|-----------|-----------| | t OUTCCJ_DC (92) (97) | Cycle-to-cycle jitter for dedicated clock output | f OUT < 100 MHz (94) | - | - | 17.5 | mUI (p-p) | | t OUTCCJ_DC (92) (97) | Cycle-to-cycle jitter for dedicated clock output | f OUT ≥ 100 MHz (94) | - | - | 175 | ps (p-p) | | t OUTPJ_IO (98) (97) | Period jitter for clock output on the regular I/O | f OUT < 100 MHz (94) | - | - | 60 | mUI (p-p) | | t OUTPJ_IO (98) (97) | Period jitter for clock output on the regular I/O | f OUT ≥ 100 MHz (94) | - | - | 600 | ps (p-p) | | t OUTCCJ_IO (98) (97) | Cycle-to-cycle jitter for clock output on the regular I/O | f OUT < 100 MHz (94) | - | - | 60 | mUI (p-p) | | t OUTCCJ_IO (98) (97) | Cycle-to-cycle jitter for clock output on the regular I/O | f OUT ≥ 100 MHz (94) | - | - | 600 | ps (p-p) | | t CASC_OUTPJ_DC (92) | Period jitter for dedicated clock output in cascaded PLLs | f OUT < 100 MHz (94) | - | - | 17.5 | mUI (p-p) | | t CASC_OUTPJ_DC (92) | Period jitter for dedicated clock output in cascaded PLLs | f OUT ≥ 100 MHz (94) | - | - | 175 | ps (p-p) | | t EINDUTY | Input clock or external feedback clock input duty cycle | f IN ≥ 600 MHz | 30 | - | 70 | % | | t EINDUTY | Input clock or external feedback clock input duty cycle | 450 MHz ≤ f IN < 600 MHz | 35 | - | 65 | % | | t EINDUTY | Input clock or external feedback clock input duty cycle | 250 MHz ≤ f IN < 450 MHz | 40 | - | 60 | % | | t EINDUTY | Input clock or external feedback clock input duty cycle | 10 MHz ≤ f IN < 250 MHz | 45 | - | 55 | % |

Table 53. E-Series FPGAs I/O PLL Specifications

For specification status, see the Data Sheet Status table

| Symbol | Parameter | Condition | Min | Typ | Max | Unit | |-----------|------------------------------------------------------------------------------|---------------|-------|-------|-------------|--------| | f IN | Input clock frequency source from core clock input and reference clock input | -1V, -4S | 10 | - | 1,100 (99) | MHz | | f IN | Input clock frequency source from core clock input and reference clock input | -2V, -2E, -5S | 10 | - | 900 (99) | MHz | | f IN | Input clock frequency source from core clock input and reference clock input | -3V, -6S, -6X | 10 | - | 625 (99) | MHz | | f IN | Input clock frequency source from HSIO clock input | -1V, -4S | 10 | - | 800 (99) | MHz | | f IN | Input clock frequency source from HSIO clock input | -2V, -2E, -5S | 10 | - | 717 (99) | MHz | | f IN | Input clock frequency source from HSIO clock input | -3V, -6S, -6X | 10 | - | 625 (99) | MHz | | f IN | Input clock frequency source from HVIO clock input | - | 10 | - | 156.25 (99) | MHz | | f INPFD | Input clock frequency to the PFD | - | 10 | - | 325 | MHz | | f VCO | I/O PLL VCO operating range | -1V, -4S | 600 | - | 3,200 | MHz | | f VCO | I/O PLL VCO operating range | -2V, -2E, -5S | 600 | - | 3,200 | MHz | | f VCO | I/O PLL VCO operating range | -3V, -6S, -6X | 600 | - | 2,400 | MHz | | f CLBW | I/O PLL closed-loop bandwidth | - | 0.5 | - | 20 | MHz | | f OUT | Output frequency for internal clock ( C counter) | -1V,-4S | - | - | 1,100 | MHz | | f OUT | Output frequency for internal clock ( C counter) | -2V, -2E, -5S | - | - | 1,000 | MHz | | f OUT | Output frequency for internal clock ( C counter) | -3V, -6S, -6X | - | - | 780 | MHz | | f OUT_EXT | Output frequency for external clock output | -1V, -4S | - | - | 800 | MHz | | f OUT_EXT | Output frequency for external clock output | -2V, -2E, -5S | - | - | 717 | MHz |

| Symbol | Parameter | Condition | Min | Typ | Max | Unit | |-------------------|------------------------------------------------------------------------------------------------------------|-----------------------|-------------|-------|--------------|--------------| | | | -3V, -6S, -6X | - | - | 625 | MHz | | t OUTDUTY | Duty cycle for dedicated external clock output (when set to 50%) | f OUT_EXT < 300 MHz | 45 | 50 | 55 | % | | t OUTDUTY | Duty cycle for dedicated external clock output (when set to 50%) | f OUT_EXT ≥ 300 MHz | 40/45 (100) | 50 | 55 (100) /60 | % | | t FCOMP (101) | External feedback clock compensation time | - | - | - | 5 | ns | | f DYCONFIGCLK | Dynamic configuration clock | - | - | - | 100 | MHz | | t LOCK | Time required to lock from end-of-device configuration or deassertion of areset | - | - | - | 1 | ms | | t DLOCK | Time required to lock dynamically (after switchover or reconfiguring any non- post-scale counters/ delays) | - | - | - | 1 | ms | | t PLL_PSERR (102) | Accuracy of PLL phase shift | - | - | - | ±50 | ps | | t ARESET | Minimum pulse width on the areset signal | - | 10 | - | - | ns | | t INCCJ | Input clock cycle-to- cycle jitter | f REF < 100 MHz (103) | - | - | ±750 | ps (p-p) | | | | | | | | continued... |

| Symbol | Parameter | Condition | Min | Typ | Max | Unit | |-------------------------|--------------------------------------------------|--------------------------------------------------------------------------|-------|-------|-------|--------------| | | | f REF ≥ 100 MHz (103) | - | - | 0.15 | UI (p-p) | | t REFPJ | Reference phase jitter (rms) (104) | Carrier frequency: 100 MHz with integrated bandwidth of 10 kHz to 50 MHz | - | - | 1.42 | ps | | t REFPN | Reference phase noise (105) (104) | 10 Hz | - | - | -90 | dBc/Hz | | t REFPN | Reference phase noise (105) (104) | 100 Hz | - | - | -100 | dBc/Hz | | t REFPN | Reference phase noise (105) (104) | 1 kHz | - | - | -110 | dBc/Hz | | t REFPN | Reference phase noise (105) (104) | 10 kHz | - | - | -120 | dBc/Hz | | t REFPN | Reference phase noise (105) (104) | 100 kHz | - | - | -130 | dBc/Hz | | t REFPN | Reference phase noise (105) (104) | 1 MHz | - | - | -138 | dBc/Hz | | t REFPN | Reference phase noise (105) (104) | 10 MHz | - | - | -142 | dBc/Hz | | t REFPN | Reference phase noise (105) (104) | 100 MHz | - | - | -144 | dBc/Hz | | t OUTPJ_DC (101) (106) | Period jitter for dedicated clock output | f OUT < 100 MHz (103) | - | - | 17.5 | mUI (p-p) | | t OUTPJ_DC (101) (106) | Period jitter for dedicated clock output | f OUT ≥ 100 MHz (103) | - | - | 175 | ps (p-p) | | t OUTCCJ_DC (101) (106) | Cycle-to-cycle jitter for dedicated clock output | f OUT < 100 MHz (103) | - | - | 17.5 | mUI (p-p) | | t OUTCCJ_DC (101) (106) | Cycle-to-cycle jitter for dedicated clock output | f OUT ≥ 100 MHz (103) | - | - | 175 | ps (p-p) | | | | | | | | continued... |

| Symbol | Parameter | Condition | Min | Typ | Max | Unit | |-------------------------|-----------------------------------------------------------|--------------------------|-------|-------|-------|-----------| | t OUTPJ_IO (107) (106) | Period jitter for clock output on the regular I/O | f OUT < 100 MHz (103) | - | - | 60 | mUI (p-p) | | t OUTPJ_IO (107) (106) | Period jitter for clock output on the regular I/O | f OUT ≥ 100 MHz (103) | - | - | 600 | ps (p-p) | | t OUTCCJ_IO (107) (106) | Cycle-to-cycle jitter for clock output on the regular I/O | f OUT < 100 MHz (103) | - | - | 60 | mUI (p-p) | | t OUTCCJ_IO (107) (106) | Cycle-to-cycle jitter for clock output on the regular I/O | f OUT ≥ 100 MHz (103) | - | - | 600 | ps (p-p) | | t CASC_OUTPJ_DC (101) | Period jitter for dedicated clock output in cascaded PLLs | f OUT < 100 MHz (103) | - | - | 17.5 | mUI (p-p) | | t CASC_OUTPJ_DC (101) | Period jitter for dedicated clock output in cascaded PLLs | f OUT ≥ 100 MHz (103) | - | - | 175 | ps (p-p) | | t EINDUTY | Input clock or external feedback clock input duty cycle | f IN ≥ 600 MHz | 30 | - | 70 | % | | t EINDUTY | Input clock or external feedback clock input duty cycle | 450 MHz ≤ f IN < 600 MHz | 35 | - | 65 | % | | t EINDUTY | Input clock or external feedback clock input duty cycle | 250 MHz ≤ f IN < 450 MHz | 40 | - | 60 | % | | t EINDUTY | Input clock or external feedback clock input duty cycle | 10 MHz ≤ f IN < 250 MHz | 45 | - | 55 | % |

Related Information

Memory Output Clock Jitter Specifications on page 93

Provides more information about the external memory interface clock output jitter specifications.

(107) External memory interface clock output jitter specifications use a different measurement method, which are available in the Memory Output clock Jitter Specifications table.

DSP Block Specifications

Table 54. D-Series FPGAs DSP Block Performance Specifications for Single DSP Block

For specification status, see the Data Sheet Status table

| Mode | Performance | Performance | Performance | Unit | |------------------------------------------------------------------------|---------------|---------------|---------------|--------------| | Mode | -1V | -2V | -3V | Unit | | Fixed-point 18 × 19 multiplication mode | 768 | 655 | 574 | MHz | | Fixed-point 27 × 27 multiplication mode | 768 | 655 | 574 | MHz | | Fixed-point 18 × 19 multiplier adder mode | 768 | 655 | 574 | MHz | | Fixed-point 18 × 19 multiplier adder summed with 36-bit input mode | 768 | 655 | 574 | MHz | | Fixed-point six 9 × 9 multiplier adder mode | 768 | 655 | 574 | MHz | | FP32 floating-point multiplication mode | 637 | 492 | 431 | MHz | | FP32 floating-point adder or subtract mode | 637 | 492 | 431 | MHz | | FP32 floating-point multiplier adder or subtract mode | 637 | 492 | 431 | MHz | | FP32 floating-point multiplier accumulate mode | 637 | 492 | 431 | MHz | | Addition or subtraction of two FP16 floating-point multiplication mode | 637 | 492 | 431 | MHz | | Sum/sub of two FP16 multiplications with FP32 (addition/subtraction) | 637 | 492 | 431 | MHz | | | | | | continued... |

| Mode | Performance | Performance | Performance | Unit | |-------------------------------------------------------------------------------|---------------|---------------|---------------|--------| | Mode | -1V | -2V | -3V | Unit | | Sum/sub of two FP16 multiplications with accumulation (addition/ subtraction) | 637 | 492 | 431 | MHz | | Tensor floating-point mode | 637 | 492 | 431 | MHz | | Tensor accumulation mode: fp32 | 637 | 492 | 431 | MHz | | Tensor fixed-point mode | 768 | 655 | 574 | MHz | | INT16 complex multiplication mode | 768 | 655 | 574 | MHz |

Table 55. D-Series FPGAs DSP Block Performance Specifications for Multiple DSP Blocks

For specification status, see the Data Sheet Status table

| Mode | Performance | Performance | Performance | Unit | |-------------------------------------------------|---------------|---------------|---------------|--------------| | Mode | -1V | -2V | -3V | Unit | | Fixed-point 18 x 19 complex multiplication mode | 768 | 655 | 574 | MHz | | Fixed-point 18 × 19 FIR systolic mode | 768 | 655 | 574 | MHz | | Fixed-point 27 × 27 multiplication mode | 576 | 492 | 431 | MHz | | Fixed-point 9 × 9 multiplication mode | 576 | 492 | 431 | MHz | | FP32 floating-point complex multiplication | 637 | 492 | 431 | MHz | | FP32 floating-point vector dot product | 637 | 492 | 431 | MHz | | FP16 floating-point complex multiplication | 637 | 492 | 431 | MHz | | continued... | continued... | continued... | continued... | continued... |

| Mode | Performance | Performance | Performance | Unit | |----------------------------------------|---------------|---------------|---------------|--------| | Mode | -1V | -2V | -3V | Unit | | FP16 floating-point vector dot product | 637 | 492 | 431 | MHz | | Tensor floating-point cascade chain | 637 | 492 | 431 | MHz | | Tensor fixed-point cascade chain | 768 | 655 | 574 | MHz |

Table 56. E-Series FPGAs DSP Block Performance Specifications for Single DSP Block

For specification status, see the Data Sheet Status table

| Mode | Performance | Performance | Performance | Performance | Performance | Performance | Unit | |---------------------------------------------------------------------|---------------|---------------|---------------|---------------|---------------|---------------|--------------| | Mode | -1V | -2V, -2E | -3V | -4S | -5S | -6S, -6X | Unit | | Fixed-point 18 × 19 multiplication mode | 768 | 655 | 574 | 558 | 489 | 408 | MHz | | Fixed-point 27 × 27 multiplication mode | 768 | 655 | 574 | 558 | 489 | 408 | MHz | | Fixed-point 18 × 19 multiplier adder mode | 768 | 655 | 574 | 558 | 489 | 408 | MHz | | Fixed-point 18 × 19 multiplier adder summed with 36- bit input mode | 768 | 655 | 574 | 558 | 489 | 408 | MHz | | Fixed-point six 9 × 9 multiplier adder mode | 768 | 655 | 574 | 558 | 489 | 408 | MHz | | FP32 floating-point multiplication mode | 637 | 492 | 431 | 418 | 367 | 306 | MHz | | FP32 floating-point adder or subtract mode | 637 | 492 | 431 | 418 | 367 | 306 | MHz | | continued... | continued... | continued... | continued... | continued... | continued... | continued... | continued... |

| Mode | Performance | Performance | Performance | Performance | Performance | Performance | Unit | |-------------------------------------------------------------------------------|---------------|---------------|---------------|---------------|---------------|---------------|--------| | Mode | -1V | -2V, -2E | -3V | -4S | -5S | -6S, -6X | Unit | | FP32 floating-point multiplier adder or subtract mode | 637 | 492 | 431 | 418 | 367 | 306 | MHz | | FP32 floating-point multiplier accumulate mode | 637 | 492 | 431 | 418 | 367 | 306 | MHz | | Addition or subtraction of two FP16 floating-point multiplication mode | 637 | 492 | 431 | 418 | 367 | 306 | MHz | | Sum/sub of two FP16 multiplications with FP32 (addition/ subtraction) | 637 | 492 | 431 | 418 | 367 | 306 | MHz | | Sum/sub of two FP16 multiplications with accumulation (addition/ subtraction) | 637 | 492 | 431 | 418 | 367 | 306 | MHz | | Tensor floating- point mode | 637 | 492 | 431 | 418 | 367 | 306 | MHz | | Tensor accumulation mode: fp32 | 637 | 492 | 431 | 418 | 367 | 306 | MHz | | Tensor fixed-point mode | 768 | 655 | 574 | 558 | 489 | 408 | MHz | | INT16 complex multiplication mode | 768 | 655 | 574 | 558 | 489 | 408 | MHz |

Table 57. E-Series FPGAs DSP Block Performance Specifications for Multiple DSP Blocks

For specification status, see the Data Sheet Status table

| Mode | Performance | Performance | Performance | Performance | Performance | Performance | Unit | |-------------------------------------------------|---------------|---------------|---------------|---------------|---------------|---------------|--------| | Mode | -1V | -2V, -2E | -3V | -4S | -5S | -6S, -6X | Unit | | Fixed-point 18 x 19 complex multiplication mode | 768 | 655 | 574 | 558 | 489 | 408 | MHz | | Fixed-point 18 × 19 FIR systolic mode | 768 | 655 | 574 | 558 | 489 | 408 | MHz | | Fixed-point 27 × 27 multiplication mode | 576 | 492 | 431 | 418 | 367 | 306 | MHz | | Fixed-point 9 × 9 multiplication mode | 576 | 492 | 431 | 418 | 367 | 306 | MHz | | FP32 floating-point complex multiplication | 637 | 492 | 431 | 418 | 367 | 306 | MHz | | FP32 floating-point vector dot product | 637 | 492 | 431 | 418 | 367 | 306 | MHz | | FP16 floating-point complex multiplication | 637 | 492 | 431 | 418 | 367 | 306 | MHz | | FP16 floating-point vector dot product | 637 | 492 | 431 | 418 | 367 | 306 | MHz | | Tensor floating- point cascade chain | 637 | 492 | 431 | 418 | 367 | 306 | MHz | | Tensor fixed-point cascade chain | 768 | 655 | 574 | 558 | 489 | 408 | MHz |

Memory Block Specifications

To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on-chip PLL and set to 50% output duty cycle. Use the Quartus Prime software to report timing for the memory block clocking schemes.

When you use the error detection cyclical redundancy check (CRC) feature, there is no degradation in fMAX.

Table 58. D-Series FPGAs Memory Block Performance Specifications

For specification status, see the Data Sheet Status table

| Memory | Mode | Performance | Performance | Performance | Unit | |------------------|------------------------------------------------------------------------------------------------------------------------------------------|---------------|---------------|---------------|--------| | Memory | Mode | -1V | -2V | -3V | Unit | | MLAB | Single-port RAM/ROM Simple dual-port RAM | 1,000 | 782 | 667 | MHz | | MLAB | Simple dual-port RAM with read-during-write option set to New Data or Old Data | 630 | 510 | 460 | MHz | | M20K block (108) | Single-port RAM/ROM Simple dual-port RAM | 1,000 | 782 | 667 | MHz | | M20K block (108) | Simple dual-port RAM, coherent read enabled | 1,000 | 782 | 667 | MHz | | M20K block (108) | Single-port RAM with the read-during-write option set to Old Data Simple dual-port RAM with the read-during-write option set to Old Data | 800 | 640 | 560 | MHz | | M20K block (108) | Simple dual-port RAM with ECC enabled, 512 × 32 | 600 | 480 | 420 | MHz | | M20K block (108) | Simple dual-port RAM with ECC, optional pipeline registers enabled, 512 × 32 | 1,000 | 782 | 667 | MHz | | M20K block (108) | Dual-port ROM True dual-port RAM | 600 | 500 | 420 | MHz | | M20K block (108) | Simple quad-port RAM | 600 | 500 | 420 | MHz |

Table 59. E-Series FPGAs Memory Block Performance Specifications

For specification status, see the Data Sheet Status table

| Memory | Mode | Performance | Performance | Performance | Performance | Performance | Performance | Unit | |------------------|--------------------------------------------------------------------------------------------------------------------------------------------|---------------|---------------|---------------|---------------|---------------|---------------|--------------| | Memory | Mode | -1V | -2V, -2E | -3V | -4S | -5S | -6S, -6X | Unit | | MLAB | Single-port RAM/ROM Simple dual-port RAM | 850 | 750 | 510 | 600 | 469 | 400 | MHz | | MLAB | Simple dual-port RAM with read- during-write option set to New Data or Old Data | 530 | 450 | 380 | 400 | 310 | 280 | MHz | | M20K block (109) | Single-port RAM/ROM Simple dual-port RAM | 1,000 | 782 | 667 | 700 | 550 | 465 | MHz | | M20K block (109) | Simple dual-port RAM, coherent read enabled | 1,000 | 782 | 667 | 700 | 550 | 465 | MHz | | M20K block (109) | Single-port RAM with the read- during-write option set to Old Data Simple dual-port RAM with the read-during- write option set to Old Data | 800 | 640 | 560 | 560 | 440 | 370 | MHz | | M20K block (109) | Simple dual-port RAM with ECC enabled, 512 × 32 | 600 | 480 | 420 | 420 | 330 | 280 | MHz | | | | | | | | | | continued... |

| Memory | Mode | Performance | Performance | Performance | Performance | Performance | Performance | Unit | |----------|------------------------------------------------------------------------------|---------------|---------------|---------------|---------------|---------------|---------------|--------| | Memory | Mode | -1V | -2V, -2E | -3V | -4S | -5S | -6S, -6X | Unit | | | Simple dual-port RAM with ECC, optional pipeline registers enabled, 512 × 32 | 1,000 | 782 | 667 | 700 | 550 | 465 | MHz | | | Dual-port ROM True dual-port RAM | 600 | 500 | 420 | 445 | 335 | 280 | MHz | | | Simple quad- port RAM | 600 | 500 | 420 | 445 | 335 | 280 | MHz |

Local Temperature Sensor Specifications

Table 60. Local Temperature Sensor Specifications

For specification status, see the Data Sheet Status table

| Description | Temperature Range | Accuracy | Sampling Rate (110) | Conversion Time | |--------------------------|---------------------|------------|-----------------------|-------------------| | Local temperature sensor | -40 to 125°C (111) | ±5°C | 1 KSPS | < 1 ms |

Related Information

Recommended Operating Conditions on page 22

Remote Temperature Diode Specifications

Note the following for the remote temperature diode specifications:

The temperature diode characteristics in this table target for three-currents temperature sensing chip implementation. The characteristics can also apply to two-currents temperature sensing chip implementation.
Absolute accuracy is dependent on third-party external diode ADC and integration specifics.

(110) The read out is subject to the SDM mailbox activity status.

(111) Temperature range refers to junction temperature.

Table 61. Remote Temperature Diode Specifications (Core Fabric TSD)

For specification status, see the Data Sheet Status table

| Description | Min | Typ | Max | Unit | |-------------------------------|-------|-------------|-------|--------| | I bias , diode source current | 30 | - | 170 | μA | | V bias , voltage across diode | 0.51 | - | 0.82 | V | | Series resistance | - | - | <5 | Ω | | Diode ideality factor | - | 1.005 (112) | - | - |

Voltage Sensor Specifications

Table 62. Voltage Sensor Specifications

For specification status, see the Data Sheet Status table

| Parameter | Minimum | Typical | Maximum | Unit | |---------------------------------------------------------------|--------------|--------------|--------------|--------------| | Resolution | - | 7 | - | Bit | | Sampling rate (113) | - | - | 1 | KSPS | | Input capacitance | - | - | 40 | pF | | External reference voltage | 1.125 | 1.25 | 1.375 | V | | Voltage sensor accuracy, V in range: 0 V to 1.1 V (114) (115) | - | - | ±3.5 | % | | continued... | continued... | continued... | continued... | continued... |

For low voltage channels in channels 0, 1, 2, 6, and 7, the accuracy is ±5.5%. This equals to ±68.75mV.
For high voltage channels in channels 3, 4, 5, and 9, the accuracy is ±6.5%. This equals to ±81.25mV.

| Parameter | Parameter | Minimum | Typical | Maximum | Unit | |---------------------|--------------------------------------|-----------|-----------|-----------|--------| | Unipolar input mode | Input signal range for Vsigp | - | - | 1.35 | V | | | Common mode voltage on Vsign | - | - | 0.25 | V | | | Input signal range for Vsigp - Vsign | - | - | 1.1 | V |

Periphery Performance Specifications

This section describes the periphery performance, LVDS SERDES, and external memory interface.

Actual achievable frequency depends on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.

LVDS SERDES Specifications

Table 63. D-Series and E-Series Device Group A FPGAs LVDS SERDES Specifications

LVDS serializer/deserializer (SERDES) block supports SERDES factor J = 4 and 8.

DDR registers support SERDES factor J = 1 and 2.

You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew margin, transmitter channel-to-channel skew, and receiver sampling margin to determine the leftover timing margin.

For specification status, see the Data Sheet Status table

| Symbol | Condition | -1 Speed Grade | -1 Speed Grade | -1 Speed Grade | -2 Speed Grade | -2 Speed Grade | -2 Speed Grade | -3 Speed Grade | -3 Speed Grade | -3 Speed Grade | Unit | |--------------------------------------------------------------------------------|---------------------------------------|------------------|------------------|------------------|------------------|------------------|------------------|------------------|------------------|------------------|--------| | Symbol | Condition | Min | Typ | Max | Min | Typ | Max | Min | Typ | Max | Unit | | Signaling I/O Standards | | | | | | | | | | | | | f HSCLK_in (input clock frequency) SLVS400 I/O Standards | Clock boost factor W = 1 to 40 (116) | 10 | - | 445.5 | 10 | - | 445.5 | 10 | - | 445.5 | MHz | | f HSCLK_in (input clock frequency) Single- Ended I/O Standards | Clock boost factor W = 1 to 40 (116) | 10 | - | 625 | 10 | - | 625 | 10 | - | 525 | MHz | | f HSCLK_OUT (output clock frequency) True Differential Signaling I/O Standards | - | - | - | 800 | - | - | 800 | - | - | 625 | MHz | | True Differential Signaling I/O | SERDES factor J = 4 and 8 (118) (119) | 600 | - | 1,600 | 600 | - | 1,600 | 600 | - | 1,250 | Mbps |

| Parameter | Symbol | Condition | -1 Speed Grade | -1 Speed Grade | -1 Speed Grade | -2 Speed Grade | -2 Speed Grade | -2 Speed Grade | -3 Speed Grade | -3 Speed Grade | -3 Speed Grade | Unit | |--------------|--------------------------------------------------------|-------------------------------------------------|---------------------------------------------------------------------------------|---------------------------------------------------------------------------------|---------------------------------------------------------------------------------|-------------------------------------------------------------------|------------------|-------------------------------------------------------------------|----------------------------------------------------------------|----------------------------------------------------------------|----------------------------------------------------------------|--------------| | | | | Min | Typ | Max | Min | Typ | Max | Min | Typ | Max | | | | Standards - f HSDR (data rate) (117) | SERDES factor J = 2, uses DDR registers | (120) | - | 500 (121) | (120) | - | 500 (121) | (120) | - | 500 (121) | Mbps | | | Standards - f HSDR (data rate) (117) | SERDES factor J = 1, uses DDR registers | (120) | - | 250 (121) | (120) | - | 250 (121) | (120) | - | 250 (121) | Mbps | | | t x Jitter - True Differential Signaling I/O Standards | Total jitter for data rate, 600 Mbps - 1.6 Gbps | ≤1,600 Mbps: 140 ≤1,250 Mbps: 160 ≤1,000 Mbps: 180 ≤800 Mbps: 210 600 Mbps: 240 | ≤1,600 Mbps: 140 ≤1,250 Mbps: 160 ≤1,000 Mbps: 180 ≤800 Mbps: 210 600 Mbps: 240 | ≤1,600 Mbps: 140 ≤1,250 Mbps: 160 ≤1,000 Mbps: 180 ≤800 Mbps: 210 600 Mbps: 240 | ≤1,600 Mbps: 140 ≤1,250 Mbps: 160 ≤1,000 Mbps: 180 ≤800 Mbps: 210 | Mbps: | ≤1,600 Mbps: 140 ≤1,250 Mbps: 160 ≤1,000 Mbps: 180 ≤800 Mbps: 210 | ≤1,250 Mbps: 160 ≤1,000 Mbps: 180 ≤800 Mbps: 210 600 Mbps: 240 | ≤1,250 Mbps: 160 ≤1,000 Mbps: 180 ≤800 Mbps: 210 600 Mbps: 240 | ≤1,250 Mbps: 160 ≤1,000 Mbps: 180 ≤800 Mbps: 210 600 Mbps: 240 | ps | | continued... | continued... | continued... | continued... | continued... | continued... | continued... | continued... | continued... | continued... | continued... | continued... | continued... |

| Parameter | Symbol | Condition | -1 Speed Grade | -1 Speed Grade | -1 Speed Grade | -2 Speed Grade | -2 Speed Grade | -2 Speed Grade | -3 Speed Grade | -3 Speed Grade | -3 Speed Grade | Unit | |---------------------|----------------------------------------|-----------------------------------------|------------------|------------------|-------------------------------|------------------|------------------|-------------------------------|------------------|------------------|-------------------------------|--------| | Parameter | Symbol | Condition | Min | Typ | Max | Min | Typ | Max | Min | Typ | Max | Unit | | | f HSDR (data rate) (without DPA) (117) | SERDES factor J = 4 and 8 (118) (119) | 150 | - | (125) | 150 | - | (125) | 150 | - | (125) | Mbps | | | f HSDR (data rate) (without DPA) (117) | SERDES factor J = 2, uses DDR registers | (120) | - | 500 (121) | (120) | - | 500 (121) | (120) | - | 500 (121) | Mbps | | | f HSDR (data rate) (without DPA) (117) | SERDES factor J = 1, uses DDR registers | (120) | - | 250 (121) | (120) | - | 250 (121) | (120) | - | 250 (121) | Mbps | | DPA (FIFO mode) | DPA run length | - | - | - | ≤10,000 | - | - | ≤10,000 | - | - | ≤10,000 | UI | | DPA (soft CDR mode) | DPA run length | SGMII/GbE protocol | - | - | 5 | - | - | 5 | - | - | 5 | UI | | DPA (soft CDR mode) | DPA run length | All other protocols | - | - | 50 data transition per 208 UI | - | - | 50 data transition per 208 UI | - | - | 50 data transition per 208 UI | - | | Soft CDR mode | Soft-CDR ppm tolerance | - | -300 | - | 300 | -300 | - | 300 | -300 | - | 300 | ppm | | Non DPA mode | Sampling window | - | - | - | 330 | - | - | 330 | - | - | 330 | ps |

Table 64. E-Series Device Group B FPGAs LVDS SERDES Specifications

LVDS serializer/deserializer (SERDES) block supports SERDES factor J = 4 and 8.

DDR registers support SERDES factor J = 1 and 2.

For specification status, see the Data Sheet Status table

| Parameter | Symbol | Condition | -4 Speed Grade | -4 Speed Grade | -4 Speed Grade | -5 Speed Grade | -5 Speed Grade | -5 Speed Grade | -6 Speed Grade | -6 Speed Grade | -6 Speed Grade | Unit | |--------------|--------------------------------------------------------|--------------------------------------------------------------------------|----------------------------------------------------------------|----------------------------------------------------------------|----------------------------------------------------------------|----------------------------------------------------------------|----------------------------------------------------------------|----------------------------------------------------------------|-----------------------------------------------|-----------------------------------------------|-----------------------------------------------|--------------| | | | | Min | Typ | Max | Min | Typ | Max | Min | Typ | Max | | | | t x Jitter - True Differential Signaling I/O Standards | Total jitter for data rate, 600 Mbps - 1.25 Gbps | ≤1,250 Mbps: 160 ≤1,000 Mbps: 180 ≤800 Mbps: 210 600 Mbps: 240 | ≤1,250 Mbps: 160 ≤1,000 Mbps: 180 ≤800 Mbps: 210 600 Mbps: 240 | ≤1,250 Mbps: 160 ≤1,000 Mbps: 180 ≤800 Mbps: 210 600 Mbps: 240 | ≤1,250 Mbps: 160 ≤1,000 Mbps: 180 ≤800 Mbps: 210 600 Mbps: 240 | ≤1,250 Mbps: 160 ≤1,000 Mbps: 180 ≤800 Mbps: 210 600 Mbps: 240 | ≤1,250 Mbps: 160 ≤1,000 Mbps: 180 ≤800 Mbps: 210 600 Mbps: 240 | ≤1,000 Mbps: 180 ≤800 Mbps: 210 600 Mbps: 240 | ≤1,000 Mbps: 180 ≤800 Mbps: 210 600 Mbps: 240 | ≤1,000 Mbps: 180 ≤800 Mbps: 210 600 Mbps: 240 | ps | | | t DUTY (132) | TX output clock duty cycle for True Differential Signaling I/O Standards | 45 | 50 | 55 | 45 | 50 | 55 | 45 | 50 | 55 | % | | | t RISE and t FALL (129) (133) | True Differential Signaling I/O Standards | - | - | 160 | - | - | 160 | - | - | 200 | ps | | | T CCS (127) (132) | True Differential Signaling I/O Standards | - | - | 202 | - | - | 202 | - | - | 202 | ps | | continued... | continued... | continued... | continued... | continued... | continued... | continued... | continued... | continued... | continued... | continued... | continued... | continued... |

| Parameter | Symbol | Condition | -4 Speed Grade | -4 Speed Grade | -4 Speed Grade | -5 Speed Grade | -5 Speed Grade | -5 Speed Grade | -6 Speed Grade | -6 Speed Grade | -6 Speed Grade | Unit | |-----------------|-------------------------------------------------------------------|-----------------------------------------|------------------|------------------|------------------|------------------|------------------|------------------|------------------|------------------|------------------|--------------| | Parameter | Symbol | Condition | Min | Typ | Max | Min | Typ | Max | Min | Typ | Max | Unit | | Receiver (13 4) | True Differential Signaling I/O Standards - f HSDRDPA (data rate) | SERDES factor J = 4 and 8 (128) (129) | 600 | - | 1250 (135) | 600 | - | 1250 (135) | 600 | - | 1000 (135) | Mbps | | Receiver (13 4) | SLVS400 I/O Standards - f HSDRDPA (data rate) | SERDES factor J = 4 and 8 (128) (129) | 600 | - | 891 | 600 | - | 891 | 600 | - | 891 | Mbps | | Receiver (13 4) | f HSDR (data rate) (without DPA) (127) | SERDES factor J = 4 and 8 (128) (129) | 150 | - | (136) | 150 | - | (136) | 150 | - | (136) | Mbps | | Receiver (13 4) | | SERDES factor J = 2, uses DDR registers | (130) | - | 500 (131) | (130) | - | 500 (131) | (130) | - | 500 (131) | Mbps | | Receiver (13 4) | | SERDES factor J = 1, uses DDR registers | (130) | - | 250 (131) | (130) | - | 250 (131) | (130) | - | 250 (131) | Mbps | | DPA (FIFO mode) | DPA run length | - | - | - | ≤10,000 | - | - | ≤10,000 | - | - | ≤10,000 | UI | | continued... | continued... | continued... | continued... | continued... | continued... | continued... | continued... | continued... | continued... | continued... | continued... | continued... |

DPA Lock Time Specifications

Table 65. DPA Lock Time Specifications

The DPA lock time is for one channel. One data transition is defined as a 0-to-1 or 1-to-0 transition.

For specification status, see the Data Sheet Status table

| Standard | Training Pattern | Number of Data Transitions in One Repetition of the Training Pattern | Number of Repetitions per 256 Data Transitions (137) | Maximum Data Transition | |--------------------|----------------------|------------------------------------------------------------------------|--------------------------------------------------------|---------------------------| | SPI-4 | 00000000001111111111 | 2 | 128 | 768 | | Parallel Rapid I/O | 00001111 | 2 | 128 | 768 | | Parallel Rapid I/O | 10010000 | 4 | 64 | 768 | | Miscellaneous | 10101010 | 8 | 32 | 768 | | Miscellaneous | 01010101 | 8 | 32 | 768 |

LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications

Figure 2. LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications for a Data Rate Equal to 1.6 Gbps

Table 66. LVDS SERDES Soft-CDR Sinusoidal Jitter Mask Values for a Data Rate Equal to 1.6 Gbps

For specification status, see the Data Sheet Status table

| Parameter | Jitter Frequency (Hz) | Sinusoidal Jitter (UI) | |-------------|-------------------------|--------------------------| | F1 | 10,000 | 25 | | F2 | 17,565 | 25 | | F3 | 1,493,000 | 0.22 | | F4 | 50,000,000 | 0.22 |

Figure 3. LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications for a Data Rate Less than 1.6 Gbps

Memory Standards Supported

Table 67. D-Series FPGAs Memory Standards Supported

This table lists the overall capability of External Memory Interface supported by D-Series FPGAs. For specific details, refer to the External Memory Interface Spec Estimator .

For specification status, see the Data Sheet Status table

| Memory Standard | Controller Type | Maximum Frequency (MHz) | |-------------------|------------------------|---------------------------| | DDR4 SDRAM | Hard memory controller | 1,600 | | DDR5 SDRAM | Hard memory controller | 2,800 | | LPDDR4 SDRAM | Hard memory controller | 2,133 | | LPDDR5 SDRAM | Hard memory controller | 2,750 | | continued... | continued... | continued... |

| Memory Standard | Controller Type | Maximum Frequency (MHz) | |-------------------|----------------------------|---------------------------| | DDR4 SDRAM | HPS hard memory controller | 1,333 | | DDR5 SDRAM | HPS hard memory controller | 2,600 | | LPDDR4 SDRAM | HPS hard memory controller | 2,133 | | LPDDR5 SDRAM | HPS hard memory controller | 2,600 |

Table 68. E-Series Device Group A FPGAs Memory Standards Supported

This table lists the overall capability of External Memory Interface supported by E-Series Device Group A. For specific details, refer to the External Memory Interface Spec Estimator .

For specification status, see the Data Sheet Status table

| Memory Standard | Controller Type | Maximum Frequency (MHz) | |-------------------|----------------------------|---------------------------| | DDR4 SDRAM | Hard memory controller | 1,333 | | DDR5 SDRAM | Hard memory controller | 1,800 | | LPDDR4 SDRAM | Hard memory controller | 1,866 | | LPDDR5 SDRAM | Hard memory controller | 1,866 | | DDR4 SDRAM | HPS hard memory controller | 1,333 | | DDR5 SDRAM | HPS hard memory controller | 1,800 | | LPDDR4 SDRAM | HPS hard memory controller | 1,866 | | LPDDR5 SDRAM | HPS hard memory controller | 1,866 |

Table 69. E-Series Device Group B FPGAs Memory Standards Supported

This table lists the overall capability of External Memory Interface supported by E-Series Device Group B. For specific details, refer to the External Memory Interface Spec Estimator .

For specification status, see the Data Sheet Status table

| Memory Standard | Controller Type | Maximum Frequency (MHz) | |-------------------|------------------------|---------------------------| | DDR4 SDRAM | Hard memory controller | 1,200 | | LPDDR4 SDRAM | Hard memory controller | 1,333 | | continued... | continued... | continued... |

| Memory Standard | Controller Type | Maximum Frequency (MHz) | |-------------------|----------------------------|---------------------------| | LPDDR5 SDRAM | Hard memory controller | 1,066 | | DDR4 SDRAM | HPS hard memory controller | 1,066 | | LPDDR4 SDRAM | HPS hard memory controller | 1,333 | | LPDDR5 SDRAM | HPS hard memory controller | 1,066 |

Related Information

External Memory Interface (EMIF) Spec Estimator

Memory Output Clock Jitter Specifications

The clock jitter specification applies to the memory output clock pins clocked by an I/O PLL, or generated using double data I/O circuits clocked by a PLL output routed on a PHY clock network as specified. Altera recommends using PHY clock networks for better jitter performance.

The memory clock output jitter is within the JEDEC* specifications when the phase jitter (integration bandwidth 10 kHz to 50 MHz) of the input clock is not more than 20 ps peak-to-peak, or 1.42 ps RMS at 1e -12 BER and 1.22 ps at 1e -16 BER.

MIPI D-PHY Performance

Table 70. D-Series FPGAs MIPI D-PHY Performance

For specification status, see the Data Sheet Status table

Table 71. E-Series FPGAs MIPI D-PHY Performance

For specification status, see the Data Sheet Status table

| Paramete r | Device Group | Symbol | Condition | -1, -4 Speed Grade | -1, -4 Speed Grade | -1, -4 Speed Grade | -2, -5 Speed Grade | -2, -5 Speed Grade | -2, -5 Speed Grade | -3, -6 Speed Grade | -3, -6 Speed Grade | -3, -6 Speed Grade | Unit | |--------------------------------------|----------------|---------------------------|--------------------------------------------------------------|----------------------|----------------------|----------------------|----------------------|----------------------|----------------------|----------------------|----------------------|----------------------|--------| | Paramete r | Device Group | Symbol | Condition | Min | Typ | Max | Min | Typ | Max | Min | Typ | Max | Unit | | MIPI D- PHY transmitt er or receiver | A | High- speed interface, Hs | Long reference ( 139) | 150 | - | 2,500 | 150 | - | 2,500 | 150 | - | 2,500 | Mbps | | MIPI D- PHY transmitt er or receiver | A | High- speed interface, Hs | Short reference and standard reference ( 139) | 150 | - | 3,500 | 150 | - | 3,500 | 150 | - | 3,500 | Mbps | | MIPI D- PHY transmitt er or receiver | A | Low- power interface, Lp | - | - | - | 20 | - | - | 20 | - | - | 20 | MHz | | MIPI D- PHY transmitt er or receiver | B | High- speed interface, Hs | Short reference, standard reference, or long reference (139) | 150 | - | 2,500 | 150 | - | 2,500 | 150 | - | 2,500 | Mbps | | MIPI D- PHY transmitt er or receiver | B | Low- power interface, Lp | - | - | - | 20 | - | - | 20 | - | - | 20 | MHz |

GTS Transceiver Performance Specifications

GTS Transceiver Performance

Table 72. Transmitter and Receiver Data Rate Performance

For specification status, see the Data Sheet Status table

| Symbol/Description | Transceiver Speed | Unit | |-------------------------------------------------------|---------------------|--------| | Supported data rate for E-Series Device Group B (NRZ) | 1 - 17.16 | Gbps | | Supported data rate for E-Series Device Group A (NRZ) | 1 - 28.1 | Gbps | | Supported data rate for D-Series (NRZ) | 1 - 28.1 | Gbps |

GTS Transceiver Reference Clock Specifications

Table 73. GTS Transceiver and System PLL Reference Clock Input Specifications

For specification status, see the Data Sheet Status table

| Symbol | Description | Condition | Min | Typical | Max | Unit | |----------------------|----------------------------------------------|-------------------------------|--------------|--------------|--------------|--------------| | - | Supported I/O standards | Dedicated reference clock pin | CML, HCSL | CML, HCSL | CML, HCSL | CML, HCSL | | F REF | Reference clock operating frequency | - | 100 (140) | - | 380 | MHz | | T REF-DUTY | Duty cycle | - | 45 | 50 | 55 | % | | T REF-RISE/FALL | Rise and fall time (as percentage of period) | 20% - 80% | - | - | 0.15 | T REF | | SSC | Spread-spectrum downspread | PCIe* | - | -5,000 to 0 | - | ppm | | T REF-SINGLEEND-SKEW | Skew between REFCLKP and REFCLKN | - | - | - | 50 | ps | | continued... | continued... | continued... | continued... | continued... | continued... | continued... |

| Symbol | Description | Condition | Min | Typical | Max | Unit | |-----------------|-----------------------------------------------------------------------------------|-------------|-------------|-------------|-------------|--------------| | Z REF-DIFF-DC | Reference clock differential input impedance - terminated mode | - | 80 | 100 | 120 | Ω | | V min-ABS | Absolute V min | - | -0.15 | - | - | V | | V max-ABS | Absolute V max | - | - | - | 0.85 | V | | V REFIN-DIFF-AC | Input reference clock differential peak-to- peak voltage when AC-coupled on board | - | 0.6 | 1.2 | 1.7 | V | | V REFIN-IL-DC | Input reference clock input low voltage when DC-coupled on board | - | -0.15 | 0 | 0.15 | V | | V REFIN-IH-DC | Input reference clock input high voltage when DC-coupled on board | - | 0.66 | 0.7 | 0.85 | V | | V REFIN-CM-AC | Input reference clock common-mode voltage when AC- coupled on board | - | Set on chip | Set on chip | Set on chip | V | | V REFIN-CM-DC | Input reference clock common-mode voltage when DC- coupled on board | - | 0.255 | 0.35 | 0.5 | V | | PN REF | Transmitter REFCLK phase noise (156.25 MHz) (141) (140) | 10 kHz | - | - | -130 | dBc/Hz | | PN REF | Transmitter REFCLK phase noise (156.25 MHz) (141) (140) | 100 kHz | - | - | -138 | dBc/Hz | | PN REF | Transmitter REFCLK phase noise (156.25 MHz) (141) (140) | 500 kHz | - | - | -138 | dBc/Hz | | PN REF | Transmitter REFCLK phase noise (156.25 MHz) (141) (140) | 3 MHz | - | - | -140 | dBc/Hz | | | | | | | | continued... |

| Symbol | Description | Condition | Min | Typical | Max | Unit | |-------------------|------------------------------------------------------------|-------------|------------|------------|------------|--------| | | | 10 MHz | - | - | -144 | dBc/Hz | | | | 20 MHz | - | - | -146 | dBc/Hz | | | | 1 GHz | - | - | -146 | dBc/Hz | | V REFIN-RJ-RMS | RMS jitter integrated from 10 kHz - 20 MHz including spurs | - | - | - | 522 | fs | | V REFIN-PPM-ERROR | Reference clock frequency error | - | -350 + SSC | - | +350 + SSC | ppm | | R COMP | External resistor for calibration | - | - | 499 ± 0.1% | - | Ω |

Table 74. System PLL Reference Clock (Using HVIO) Specifications

For specifications on the I/O PLL using HVIO pin, refer to D-Series FPGAs I/O PLL Specifications or E-Series FPGAs I/O PLL Specifications respectively.

For specification status, see the Data Sheet Status table

| Symbol | Description | Condition | Min | Typical | Max | Unit | |------------|------------------------|------------------------|-------|-----------|-------|--------| | F REF | Clock input frequency | Powered by V CCIO_HVIO | 25 | - | 125 | MHz | | T REF-DUTY | Clock input duty cycle | | 45 | 50 | 55 | % |

Table 75. GTS Transceiver Reference Clock Output Driver Specifications

For specification status, see the Data Sheet Status table

| Symbol | Description | Condition | Min | Typical | Max | Unit | |-------------------------|----------------------------------------------|--------------|--------------|--------------|--------------|--------------| | F REF_OUT | Reference clock operating frequency | - | 25 | - | 380 | MHz | | T REF-DUTY_OUT | Duty cycle | - | 45 | 50 | 55 | % | | T REF-RISE_OUT/FALL_OUT | Rise and fall time (as percentage of period) | 20% - 80% | - | - | 0.15 | T REF | | T REF-SINGLEEND-SKEW | Skew between REFCLKP and REFCLKN | - | - | - | 50 | ps | | continued... | continued... | continued... | continued... | continued... | continued... | continued... |

| Symbol | Description | Condition | Min | Typical | Max | Unit | |-------------------|-----------------------------------------------------------------------------------|-------------|-------|-----------|--------|--------| | Z REF-DIFF-DC_OUT | Reference clock differential output impedance - terminated mode | - | 80 | 100 | 120 | Ω | | V REF-DIFF-AC_OUT | Output reference clock differential peak to peak voltage when AC-coupled on board | - | 0.9 | 1 | 1.1 | V | | V REF-CM-OUT | Output reference clock common-mode | - | 0.45 | 0.5 | 0.55 | V |

Transmitter Specifications

Table 76. Transmitter Electrical Specifications

For specification status, see the Data Sheet Status table

| Parameter | Symbol | Description | Condition | Min | Typical | Max | Unit | |---------------------------------------|-----------------|--------------------------------------------------------|--------------|--------------|--------------|--------------|--------------| | On-chip termination | - | Transmitter differential on-chip termination resistors | - | 80 | 90 | 120 | Ω | | Transmitter output eye specifications | V TX-DIFF-PKPK | Back-porch transmit amplitude | - | 300 | - | 1,050 | mV | | Transmitter output eye specifications | V TX-DEEMP_STEP | Transmitter tap resolution | - | - | - | 2 | % | | Transmitter output eye specifications | D TX-PRE_TAP_2 | Pre-cursor tap 2 de-emphasis | - | 0 | - | 2.5 | dB | | Transmitter output eye specifications | D TX-PRE_TAP_1 | Pre-cursor tap 1 de-emphasis | - | 0 | - | 4.5 | dB | | Transmitter output eye specifications | D TX-POST_TAP_1 | Post-cursor tap 1 de-emphasis | - | 0 | - | 6.5 | dB | | Transmitter output eye specifications | T TX-SLEW | Rise/fall time at 20%-80% | - | 10 | - | 20 | ps | | continued... | continued... | continued... | continued... | continued... | continued... | continued... | continued... |

| Parameter | Symbol | Description | Condition | Min | Typical | Max | Unit | |--------------------------|---------------|------------------------------------------------------------------------------------------|------------------|--------------|--------------|--------------|--------------| | | T TX-DJ | Transmitter deterministic jitter at 25 Gbps | - | - | - | 0.15 | UI pkpk | | | T TX-RJ | Transmitter total peak-peak random jitter (142) | At BER of 10 -12 | - | - | 0.15 | UI pkpk | | | T TX-TJ | Transmitter total peak-peak jitter (T TX-TJ = T TX-DDJ + T TX-PJ + T TX-RJ ) (142) (143) | At BER of 10 -12 | - | - | 0.28 | UI pkpk | | Transmitter DC impedance | Z TX-DIFF-DC | Transmitter output differential DC impedance with OCT 90 Ω mode while configured (144) | - | 80 | 90 | 120 | Ω | | Transmitter DC impedance | Z TX-CM-DC | Transmitter output common-mode DC impedance | - | 20 | 22.5 | 30 | Ω | | Transmitter return loss | Z RL-DIFF-DC | Transmitter differential DC return loss | - | - | - | -12 | dB | | Transmitter return loss | Z RL-DIFF-NYQ | Transmitter differential return loss at Nyquist frequency (F BAUD /2) | - | - | - | -6 | dB | | continued... | continued... | continued... | continued... | continued... | continued... | continued... | continued... |

| Parameter | Symbol | Description | Condition | Min | Typical | Max | Unit | |--------------------------|--------------------|------------------------------------------------------------------|--------------------|-------|-----------|---------------|--------| | | Z RL-CMN | Transmitter common-mode return loss below 10 GHz | - | - | - | -6 | dB | | Electrical idle | V TX-IDLE | Electrical idle output voltage | PCIe/ SATA/SAS/USB | - | - | 20 | mV | | Electrical idle | V CM-DELTA-SQUELCH | Maximum common-mode step entering/ exiting squelch mode | PCIe/ SATA/SAS/USB | - | - | 100 | mV | | Electrical idle | T TX-IDLE-LATENCY | Latency entering/ exiting electrical idle | PCIe/ SATA/SAS/USB | - | - | 8 | µs | | Receiver detect | V TX-RCV-DETECT | Receiver detect voltage change allowed during receiver detection | PCIe/ SATA/SAS/USB | - | - | 600 | mV | | Lane-to-lane output skew | - | Lane-to-lane output skew | 4 < Lane count ≤ 8 | - | - | 2 UI + 250 ps | ps | | Lane-to-lane output skew | - | Lane-to-lane output skew | Lane count ≤ 4 | - | - | 2 UI + 166 ps | ps |

Receiver Specifications

Table 77. Receiver Electrical Specifications

For specification status, see the Data Sheet Status table

| Parameter | Symbol | Description | Condition | Min | Typical | Max | Unit | |-----------------------------------|----------------|---------------------------------------------------------|--------------|------------------|--------------|--------------|--------------| | On-chip termination | - | Receiver differential on-chip termination resistors | - | 65 | 85 | 102 | Ω | | On-chip termination | - | Receiver differential on-chip termination resistors | - | 80 | 100 | 120 | Ω | | Receiver input eye specifications | V RX-DIFF-PKPK | Receiver input differential peak- to-peak voltage (145) | - | Closed eye (146) | - | 1,200 | mV | | continued... | continued... | continued... | continued... | continued... | continued... | continued... | continued... |

| Parameter | Symbol | Description | Condition | Min | Typical | Max | Unit | |------------------------------|-----------------------------|-----------------------------------------------------------|--------------------------------------|--------------|--------------|--------------|--------------| | | V RX-MAX | Receiver input maximum voltage (147) | - | - | - | 1 | V | | | V RX-MIN | Receiver input minimum voltage (147) | - | -0.3 | - | - | V | | | V RX-CM-DC | Receiver input DC common-mode voltage (148) | When squelch detector is not enabled | 0 | - | 700 | mV | | | V RX-CM-DC | Receiver input DC common-mode voltage (148) | When squelch detector is enabled | 200 | - | 300 | mV | | | T RX-RJ | Receiver input random jitter | At BER of 10 -12 | - | - | 0.15 | UI pkpk | | | T RX-PJ | Receiver input periodic jitter (at high frequency ) (149) | - | - | - | 0.05 | UI pkpk | | Insertion loss specification | I INS-LOSS-28Gb/ s_BER10-15 | Insertion loss at Nyquist frequency (F BAUD /2) (150) | At BER of 10 -15 | - | - | -27 | dB | | Insertion loss specification | I INS-LOSS-28Gb/ s_BER10-12 | Insertion loss at Nyquist frequency (F BAUD /2) (150) | At BER of 10 -12 | - | - | -30 | dB | | continued... | continued... | continued... | continued... | continued... | continued... | continued... | continued... |

| Parameter | Symbol | Description | Condition | Min | Typical | Max | Unit | |---------------------------------|-----------------------------|--------------------------------------------------------------------|---------------------------|-------|-----------|-------|--------| | | I INS-LOSS-17Gb/ s_BER10-12 | Insertion loss at Nyquist frequency (F BAUD /2) (150) | At BER of 10 -12 | - | - | -30 | dB | | Receiver return loss | Z RL-DIFF-DC | Receiver differential DC return loss | - | - | - | -12 | dB | | Receiver return loss | Z RL-DIFF-NYQ | Receiver differential return loss at Nyquist frequency (F BAUD /2) | - | - | - | -6 | dB | | Receiver return loss | Z RL-CM | Receiver common- mode return loss below 10 GHz | - | - | - | -6 | dB | | Receiver DC impedance | R DIFF-DC | Receiver differential DC impedance | 85 Ω on-chip termination | 65 | 85 | 102 | Ω | | Receiver DC impedance | R DIFF-DC | Receiver differential DC impedance | 100 Ω on-chip termination | 80 | 100 | 120 | Ω | | Receiver DC impedance | R CM-DC | Receiver common- mode DC impedance | - | 20 | 25 | 30 | Ω | | Receiver signal detection (151) | V IDLE-THRESH | Receiver signal detect input voltage threshold | - | 75 | 120 | 175 | mV |

Electrical Compliance

Table 78. Electrical Compliance List

For specification status, see the Data Sheet Status table

| Specification/Clause | Protocol | Lane Rate (Gbps) | Lane Rate (Gbps) | |-------------------------------------|-----------------------|-------------------------|-----------------------------------| | Specification/Clause | Protocol | E-Series Device Group B | E-Series Device Group A, D-Series | | XFP MSA | XFI | 10.3125 | 10.3125 | | IEEE 802.3ba-2010 | XLPPI | 10.3125 | 10.3125 | | Serial-GMII Specification V1.7 | 1GE SGMII | 1.25 | 1.25 | | IEEE 802.3ba | XLAUI | 10.3125 | 10.3125 | | IEEE 802.3ba | CAUI-10 | 10.3125 | 10.3125 | | IEEE 802.3by | 25GAUI-C2C/C2M | - | 1x25.78125 | | IEEE 802.3ap 2007 | 10GBASE-KR | 10.3125 | 10.3125 | | IEEE 802.3by 111/110 | 25GBASE-KR/CR | - | 25.78125 | | IEEE 803.3ap-2007 IEEE 802.3an-2006 | 1000BASE-KX/CX | 1.25 | 1.25 | | OIF-CEI 4.0 | OIF-CEI-11G SR/MR/LR | 9.95 - 11.2 | 9.95 - 11.2 | | OIF-CEI 4.0 | OIF-CEI-6G SR/LR | 4.976 - 6.375 | 4.976 - 6.375 | | OIF-CEI 4.0 | OIF-CEI-28G VSR/SR/MR | - | 24 - 28.1 | | OIF-CEI 4.0 | OIF-CEI-25G LR | - | 24 - 28.1 | | G.709 G.sup56 G.sup43 G.sup58 | OTU1 | - | 1.327451, 2.666 | | G.709 G.sup56 G.sup43 G.sup58 | OTU2 | - | 10.709, 11.049, 11.270 | | G.709 G.sup56 G.sup43 G.sup58 | OTU2e | - | 11.095 | | G.709 G.sup56 G.sup43 G.sup58 | OTU2f | - | 11.317, 11.846, 12.639 | | G.709 G.sup56 G.sup43 G.sup58 | OTU4 OTL4.4 | - | 4x27.952493 | | G.709 G.sup56 G.sup43 G.sup58 | OTU4 OTLC.4 | - | 4x28.076177 | | continued... | continued... | continued... | continued... |

| Specification/Clause | Protocol | Lane Rate (Gbps) | Lane Rate (Gbps) | |--------------------------|---------------------|-------------------------|-----------------------------------| | Specification/Clause | Protocol | E-Series Device Group B | E-Series Device Group A, D-Series | | PCIe BASE 4.0 PIPE 4.4.1 | PCIe 3.0 , PCIe 4.0 | 8, 16 (152) | 8, 16 | | SMPTE 259M | SDI SD | 0.27 | 0.27 | | SMPTE 292M | SDI HD | 1.485/1.483 | 1.485/1.483 | | SMPTE ST 424 | SDI 3G | 2.97/2.967 | 2.97/2.967 | | SMPTE ST 2081 | SDI 6G | 5.94/5.934 | 5.94/5.934 | | SMPTE ST 2082 | SDI 12G | 11.88/11.868 | 11.88/11.868 | | CPRI V7.0 | CPRI | 1.2288 | 1.2288 | | | CPRI | 2.4576 | 2.4576 | | | CPRI | 3.072 | 3.072 | | | CPRI | 4.9152 | 4.9152 | | | CPRI | 6.144 | 6.144 | | | CPRI | 8.1101 | 8.1101 | | | CPRI | 9.8304 | 9.8304 | | | CPRI | 10.1376 | 10.1376 | | | CPRI | - | 24.33024 | | JESD204B | JESD204B | up to 17.16 | up to 19.66 | | JESD204C | JESD204C | up to 17.16 | up to 28.1 | | DP 2.0 | DisplayPort 1.4 | 1.62 | 1.62 | | DP 2.0 | DisplayPort 1.4 | 2.7 | 2.7 | | DP 2.0 | DisplayPort 1.4 | 5.4 | 5.4 | | DP 2.0 | DisplayPort 1.4 | 8.1 | 8.1 |

| Specification/Clause | Protocol | Lane Rate (Gbps) | Lane Rate (Gbps) | |---------------------------------------------|-----------------|-------------------------|----------------------------------------| | Specification/Clause | Protocol | E-Series Device Group B | E-Series Device Group A, D-Series | | | DisplayPort 2.0 | 10 | 10 | | | DisplayPort 2.0 | 13.5 | 13.5 | | | DisplayPort 2.0 | - | 20 | | FC-PI-2 | Fiber Channel | 1.0625 | 1.0625 | | FC-PI-2 | Fiber Channel | 2.125 | 2.125 | | FC-PI-5 | Fiber Channel | 4.25 | 4.25 | | FC-PI-5 | Fiber Channel | 8.5 | 8.5 | | 10GFC | Fiber Channel | 10.518 | 10.518 | | FC-PI-5 | Fiber Channel | 14.025 | 14.025 | | FC-PI-6 | Fiber Channel | - | 28.05 | | FC-PI-6 | Fiber Channel | - | 4x28.05 | | Serial ATA revision 3.5a T10/BSR INCITS 519 | Sata Gen 3 | 1.5 - 6 | 1.5 - 6 | | Serial ATA revision 3.5a T10/BSR INCITS 519 | SAS | 1.5 - 12.0 | 1.5 - 22.5 | | G.984 | GPON/EPON | - | 1.244, 1.250, 2.488, 9.952, 10.313, 25 | | OIF-CEI-6G-SR | Interlaken | 6.25 | 6.25 | | OIF-CEI-11G-SR | Interlaken | 10.3125 | 10.3125 | | OIF-CEI-11G-SR+ | Interlaken | 12.5 | 12.5 | | OIF-28G MR (OIF-CEI 3.0) | Interlaken | - | 25.78125 | | HDMI 1.4 | HDMI | 3.4 | 3.4 | | HDMI 2.0 | HDMI | 6 | 6 | | HDMI 2.1 | HDMI | - | up to 12 | | SLVS-EC Specification Version 1.0 | SLVS-EC RX | 2.376 | 2.376 | | SLVS-EC Specification Version 2.0 | SLVS-EC RX | 5 | 5 | | continued... | continued... | continued... | continued... |

| Specification/Clause | Protocol | Lane Rate (Gbps) | Lane Rate (Gbps) | |--------------------------------------|---------------------|-------------------------|-----------------------------------| | | | E-Series Device Group B | E-Series Device Group A, D-Series | | SFF-8402 | SFP+ | 9.95 - 11.2 | 9.95 - 11.2 | | SFF-8431 4.1 | SFP+ | 9.95 - 11.2 | 9.95 - 11.2 | | SFF-8431 Rev 4.1 | SFP+ | 9.95 - 11.2 | 9.95 - 11.2 | | SFF-8418 | SFP+ | 9.95 - 11.2 | 9.95 - 11.2 | | USB 3.1, USB 3.2 | USB 3.1 Gen 1 | 5 | 5 | | USB 3.1, USB 3.2 | USB 3.2 Gen 2 (153) | - | 10 (153) | | RapidIO ™ Interconnect Specification | SRIO | 2 - 16 | 2 - 16 |

HPS Performance Specifications

This section provides hard processor system (HPS) specifications and timing.

HPS Clock Performance

Table 79. D-Series SoC Maximum HPS Clock Frequencies

For specification status, see the Data Sheet Status table

| Performance | V CCL_HPS (V) (154) | Cortex-A55 Core Frequency (MHz) | Cortex-A76 Core Frequency (MHz) | DSU (DynamIQ Shared Unit) Frequency (MHz) (mpu_free_clk) | L3 Frequency (MHz) (l3_main_free_clk) | DDR4/LPDDR4/ DDR5/LPDDR5 Clock (MHz) | |----------------|-----------------------|-----------------------------------|-----------------------------------|------------------------------------------------------------|-----------------------------------------|------------------------------------------------| | -1 speed grade | SmartVID | 1,500 | 1,800 | 1,200 | 400 | Refer to the Memory Standards Supported table. | | -2 speed grade | SmartVID | 1,333 | 1,600 | 1,066 | 400 | Refer to the Memory Standards Supported table. | | -3 speed grade | SmartVID | 1,250 | 1,400 | 933 | 400 | Refer to the Memory Standards Supported table. |

Table 80. E-Series SoC Maximum HPS Clock Frequencies

For specification status, see the Data Sheet Status table

| Performance | V CCL_HPS (V) (155) | Cortex-A55 Core Frequency (MHz) | Cortex-A76 Core Frequency (MHz) | DSU (DynamIQ Shared Unit) Frequency (MHz) (mpu_free_clk) | L3 Frequency (MHz) (l3_main_free_clk) | DDR4/LPDDR4/ DDR5/LPDDR5 Clock (MHz) | |----------------|-----------------------|-----------------------------------|-----------------------------------|------------------------------------------------------------|-----------------------------------------|------------------------------------------------| | -1 speed grade | SmartVID | 1,500 | 1,800 | 1,200 | 400 | Refer to the Memory Standards Supported table. | | -2 speed grade | SmartVID | 1,333 | 1,600 | 1,066 | 400 | Refer to the Memory Standards Supported table. | | -3 speed grade | SmartVID | 1,250 | 1,400 | 933 | 400 | Refer to the Memory Standards Supported table. | | -4 speed grade | Fixed: 0.8 | 1,250 | 1,400 | 933 | 400 | Refer to the Memory Standards Supported table. | | -5 speed grade | Fixed: 0.78 | 800 | 800 | 533 | 400 | Refer to the Memory Standards Supported table. | | -6 speed grade | Fixed: 0.75 | 800 | 800 | 533 | 400 | Refer to the Memory Standards Supported table. |

Related Information

HPS Power Supply Operating Conditions on page 34
Memory Standards Supported on page 91

HPS Internal Oscillator Frequency

Table 81. HPS Internal Oscillator Frequency

For specification status, see the Data Sheet Status table

| Description | Min | Typ | Max | Unit | |-------------------------------|-------|-------|-------|--------| | Internal oscillator frequency | 150 | 300 | 400 | MHz |

HPS PLL Specifications

Table 82. HPS PLL Input Requirements

The main HPS PLL receives its clock signals from the HPS_OSC_CLK pin. Refer to the Pin Connection Guidelines of this device for information about assigning this pin.

For specification status, see the Data Sheet Status table

| Description | Min | Typ | Max | Unit | |------------------------|-------|-------|-------|--------| | Clock input range | 25 | - | 125 | MHz | | Clock input accuracy | - | - | 50 | ppm | | Clock input duty cycle | 45 | 50 | 55 | % |

Table 83. HPS PLL Performance

For specification status, see the Data Sheet Status table

| Description | Min | Max | Unit | |---------------------------|-------|-------------|--------| | Main PLL VCO output | - | 4,000 (156) | MHz | | Peripheral PLL VCO output | - | 4,000 (156) | MHz | | h2f_user0_clk (157) | - | 500 | MHz | | h2f_user1_clk (157) | - | 500 | MHz |

HPS Cold Reset

Table 84. HPS Cold Reset

For specification status, see the Data Sheet Status table

| Symbol | Description | Min | Max | Unit | |----------|-------------------------------------------------|-------|-------|--------| | t RST0 | Minimum time for HPS_COLD_nRESET asserted (158) | 3 | - | ms |

HPS SPI Timing Characteristics

Table 85. SPI Master Timing Requirements

You can adjust the input delay timing by programming the rx_sample_dly register.

For specification status, see the Data Sheet Status table

| Symbol | Description | Min | Typ | Max | Unit | |---------------|--------------------------------------------------------------------------|--------------|--------------|--------------|--------------| | T spi_ref_clk | The period of the SPI internal reference clock, sourced from l4_main_clk | 2.5 | - | - | ns | | f clk | SPIM_CLK clock frequency | - | - | 60 | MHz | | T clk | SPIM_CLK clock period | 16.67 | - | - | ns | | T dutycycle | SPIM_CLK duty cycle | 45 | 50 | 55 | % | | T ck_jitter | SPIM_CLK output jitter | - | - | 2 | % | | T dio | Master-out slave-in (MOSI) output skew | -3 | - | 2 | ns | | continued... | continued... | continued... | continued... | continued... | continued... |

| Symbol | Description | Min | Typ | Max | Unit | |-----------------|------------------------------------------------------------|-----------------------------------------------|-------|-------|--------| | T dssfrst (159) | SPI_SS_N asserted to first SPIM_CLK edge | (1.5 × T clk ) - 2 | - | - | ns | | T dsslst (159) | Last SPIM_CLK edge to SPI_SS_N deasserted | T clk - 2 | - | - | ns | | T su (160) | SPIM_MISO setup time with respect to SPIM_CLK capture edge | 5.0 - ( rx_sample_dly x T spi_ref_clk ) (161) | - | - | ns | | T h (160) | Input hold in respect to SPIM_CLK capture edge | 1.3 + ( rx_sample_dly x T spi_ref_clk ) (161) | - | - | ns |

Figure 4. SPI Master Output Timing Diagram

scph* = 0

*Serial clock phase configuration bit, in the SPI controller's CTRLR0 register

Table 86. SPI Slave Timing Requirements

For specification status, see the Data Sheet Status table

| Symbol | Description | Min | Typ | Max | Unit | |---------------|--------------------------------------------------------------------------|--------------------------|-------|---------------------------|--------| | T spi_ref_clk | The period of the SPI internal reference clock, sourced from l4_main_clk | 2.5 | - | - | ns | | f clk | SPIM_CLK clock frequency | - | - | 33 | MHz | | T clk | SPIM_CLK clock period | 30 | - | - | ns | | T dutycycle | SPIM_CLK duty cycle | 45 | 50 | 55 | % | | T d | Master-in slave-out (MISO) output skew | (2 × T spi_ref_clk ) + 3 | - | (3 × T spi_ref_clk ) + 11 | ns | | T su | Master-out slave-in (MOSI) setup time | 4 | - | - | ns | | T h | Master-out slave-in (MOSI) hold time | 9 | - | - | ns | | T suss | SPI_SS_N asserted to first SPIM_CLK edge | T spi_ref_clk + 4.2 | - | - | ns | | T hss | Last SPIM_CLK edge to SPI_SS_N deasserted | T spi_ref_clk + 4.2 | - | - | ns |

Figure 6. SPI Slave Output Timing Diagram

*Serial clock phase configuration bit, in the SPI controller's CTRLR0 register

Figure 7. SPI Slave Input Timing Diagram

*Serial clock phase configuration bit, in the SPI controller's CTRLR0 register

HPS SD/eMMC Timing Characteristics

Table 87. HPS Secure Digital (SD)/Embedded MultiMediaCard (eMMC) Timing Requirements

Supports SD devices up to V6.1. Supports SDIO devices up to V4.1. Supports SD/eMMC devices up to V5.1.

These timings apply to SD, MMC, and eMMC cards operating at 1.8 V.

For specification status, see the Data Sheet Status table

| Symbol | Description | Description | Min | Typ | Max | Unit | |---------------------|---------------------------------------------------------|---------------------------------------------------------|-------|-------|-------|--------| | T sdmmc_cclk | SD SDMMC_CCLK clock period | Identification mode, 400 kHz | 2,500 | - | - | ns | | T sdmmc_cclk | SD SDMMC_CCLK clock period | SDR12, 25 MHz | 40 | - | - | ns | | T sdmmc_cclk | SD SDMMC_CCLK clock period | SDR25, 50 MHz | 20 | - | - | ns | | T sdmmc_cclk | SD SDMMC_CCLK clock period | SDR50, 100 MHz | 10 | - | - | ns | | T sdmmc_cclk | SD SDMMC_CCLK clock period | SDR104, <200 MHz | 5 | - | - | ns | | T sdmmc_cclk | SD SDMMC_CCLK clock period | DDR50, 50 MHz | 20 | - | - | ns | | T sdmmc_cclk | eMMC SDMMC_CCLK clock period | Legacy, 25MB/s, 25 MHz | 40 | - | - | ns | | T sdmmc_cclk | eMMC SDMMC_CCLK clock period | HS_SDR, 50MB/s, 50 MHz | 20 | - | - | ns | | T sdmmc_cclk | eMMC SDMMC_CCLK clock period | HS_DDR, 100MB/s, 50 MHz | 20 | - | - | ns | | T sdmmc_cclk | eMMC SDMMC_CCLK clock period | HS200, SDR, 200MB/s, 200 MHz | 5 | - | - | ns | | T sdmmc_cclk | eMMC SDMMC_CCLK clock period | HS400, DDR, 400MB/s, 200 MHz | 5 | - | - | ns | | T dutycycle | SDMMC_CCLK duty cycle | SDMMC_CCLK duty cycle | 45 | 50 | 55 | % | | T sdmmc_cclk_jitter | SDMMC_CCLK output jitter | SDMMC_CCLK output jitter | - | - | 2 | % | | T sdmmc_clk | Internal reference clock before division by 4 (200 MHz) | Internal reference clock before division by 4 (200 MHz) | 5 | - | - | ns |

None of the HPS I/Os supports 3 V mode, while SD/MMC cards must operate at 3 V at power on. eMMC devices can operate at 1.8 V at power on.

Note:

SD cards power up at 3 V. To support SD, your design must include a level shifter between the SD card and the HPS SD/MMC interface.

Table 88. SD Input Timing (SDR104, SDR50, SDR25, SDR12)

For specification status, see the Data Sheet Status table

| Symbol | Description | Min | Typ | Max | Unit | |----------|-------------------------------------------------|-------|-------|-------|--------| | T is | SDMMC_CMD/ SDMMC_DATA[7:0] input setup (SDR104) | 1.4 | - | - | ns | | T is | SDMMC_CMD/ SDMMC_DATA[7:0] input setup (SDR50) | 3 | - | - | ns | | T is | SDMMC_CMD/ SDMMC_DATA[7:0] input setup (SDR25) | 6 | - | - | ns | | T is | SDMMC_CMD/ SDMMC_DATA[7:0] input setup (SDR12) | 5 | - | - | ns | | T ih | SDMMC_CMD/ SDMMC_DATA[7:0] input hold (SDR104) | 0.8 | - | - | ns | | T ih | SDMMC_CMD/ SDMMC_DATA[7:0] input hold (SDR50) | 0.8 | - | - | ns | | T ih | SDMMC_CMD/ SDMMC_DATA[7:0] input hold (SDR25) | 2 | - | - | ns | | T ih | SDMMC_CMD/ SDMMC_DATA[7:0] input hold (SDR12) | 5 | - | - | ns |

Figure 8. SD Input (SDR104, SDR50, SDR25, SDR12) Timing Diagram

Table 89. SD Output Timing (SDR50, SDR25, SDR12)

For specification status, see the Data Sheet Status table

| Symbol | Description | Min | Typ | Max | Unit | |----------|--------------------------------------------------------|-------|-------|-------|--------| | T odly | SDMMC_CMD/ SDMMC_DATA[7:0] output delay (SDR50) | - | - | 7.5 | ns | | | SDMMC_CMD/ SDMMC_DATA[7:0] output delay (SDR25, SDR12) | - | - | 14 | ns | | T ohld | SDMMC_CMD/ SDMMC_DATA[7:0] output hold | 1.5 | - | - | ns |

Figure 9. SD Output (SDR50, SDR25, SDR12) Timing Diagram

Table 90. SD Output Timing (SDR104)

For specification status, see the Data Sheet Status table

| Symbol | Description | Min | Typ | Max | Unit | |----------|------------------------------------------------------------------------------------------|-------|-------|-------|--------| | T op | SDMMC_CMD/ SDMMC_DATA[7:0] output phase | 0 | - | 10 | ns | | ∆T op | SDMMC_CMD/ SDMMC_DATA[7:0] output delay variation due to temperature change after tuning | -350 | - | 1,550 | ps | | T odw | SDMMC_CMD/ SDMMC_DATA[7:0] output hold | 3 | - | - | ns |

Figure 10. SD Output (SDR104) Timing Diagram

Table 91. SD Timing (DDR50)

For specification status, see the Data Sheet Status table

| Symbol | Description | Min | Typ | Max | Unit | |--------------|------------------------|--------------|--------------|--------------|--------------| | T isu | SDMMC_CMD input setup | 6 | - | - | ns | | T ih | SDMMC_CMD input hold | 0.8 | - | - | ns | | T odly | SDMMC_CMD output delay | - | - | 13.7 | ns | | T oh | SDMMC_CMD output hold | 1.5 | - | - | ns | | continued... | continued... | continued... | continued... | continued... | continued... |

| Symbol | Description | Min | Typ | Max | Unit | |----------|------------------------------|-------|-------|-------|--------| | T isu2x | SDMMC_DATA[7:0] input setup | 3 | - | - | ns | | T ih2x | SDMMC_DATA[7:0] input hold | 0.8 | - | - | ns | | T odly2x | SDMMC_DATA[7:0] output delay | - | - | 7 | ns | | T odly2x | SDMMC_DATA[7:0] output hold | 1.5 | - | - | ns |

Figure 11. SD (DDR50) Timing Diagram

Table 92. eMMC Timing (Legacy, HS_SDR)

For specification status, see the Data Sheet Status table

| Symbol | Description | Min | Typ | Max | Unit | |----------|-------------------------------------|-------|-------|-------|--------| | T isu | EMMC_CMD_DATA input setup (Legacy) | 3 | - | - | ns | | T isu | EMMC_CMD_DATA input setup (HS_SDR) | 3 | - | - | ns | | T ih | EMMC_CMD DATA_input hold (Legacy) | 3 | - | - | ns | | T ih | EMMC_CMD DATA_input hold (HS_SDR) | 3 | - | - | ns | | T odly | EMMC_CMD_DATA output delay (Legacy) | - | - | 13.7 | ns | | T odly | EMMC_CMD_DATA output delay (HS_SDR) | - | - | 13.7 | ns | | T oh | EMMC_CMD_DATA output hold (Legacy) | 8.3 | - | - | ns | | T oh | EMMC_CMD DATA_output hold (HS_SDR) | 2.5 | - | - | ns |

Figure 12. eMMC (Legacy, HS_SDR) Timing Diagram

Data must always be sampled on the rising edge of the clock.

Table 93. eMMC Timing (HS_DDR)

For specification status, see the Data Sheet Status table

| Symbol | Description | Min | Typ | Max | Unit | |------------|--------------------------------------------------|-------|-------|-------|--------| | T isu_ddr | EMMC_CMD_DATA input setup | 2.5 | - | - | ns | | T ih_ddr | EMMC_CMD DATA_input hold | 2.5 | - | - | ns | | T odly_ddr | EMMC_CMD_DATA output delay (max=delay, min=hold) | 1.5 | - | 7 | ns |

Figure 13. eMMC (HS_DDR) Timing Diagram

Table 94. eMMC Timing (HS200)

For specification status, see the Data Sheet Status table

| Symbol | Description | Min | Typ | Max | Unit | |--------------|---------------------------|--------------|--------------|--------------|--------------| | T isu | EMMC_CMD_DATA input setup | 1.4 | - | - | ns | | T ih | EMMC_CMD DATA_input hold | 0.8 | - | - | ns | | continued... | continued... | continued... | continued... | continued... | continued... |

| Symbol | Description | Min | Typ | Max | Unit | |----------|------------------------------------------------------------------------------------------|-------|-------|-------|--------| | T ph | SDMMC_CMD/ SDMMC_DATA[7:0] output phase | 0 | - | 10 | ns | | ∆T ph | SDMMC_CMD/ SDMMC_DATA[7:0] output delay variation due to temperature change after tuning | -350 | - | 1,550 | ps | | T vw | SDMMC_CMD/ SDMMC_DATA[7:0] output hold | 3 | - | - | ns |

Figure 14. eMMC Input (HS200) Timing Diagram

Figure 15. eMMC Output (HS200) Timing Diagram

Table 95. eMMC Timing (HS400)

For specification status, see the Data Sheet Status table

| Symbol | Description | Min | Typ | Max | Unit | |-----------|------------------------------------------------------------------------------------------|--------|-------|-------|--------| | T isu_ddr | EMMC_CMD_DATA input setup | 0.4 | - | - | ns | | T ih_ddr | EMMC_CMD DATA_input hold | 0.4 | - | - | ns | | T rq | SDMMC_CMD/ SDMMC_DATA[7:0] output phase | 0 | - | 10 | ns | | ∆T rq | SDMMC_CMD/ SDMMC_DATA[7:0] output delay variation due to temperature change after tuning | -350 | - | 200 | ps | | T rqh | SDMMC_CMD/ SDMMC_DATA[7:0] output hold | 2 | - | - | ns |

Figure 16. eMMC Input (HS400) Timing Diagram

HPS USB 2.0 Timing Characteristics

Table 96. HPS USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) Low Pin Interface (ULPI) Timing Requirements

For specification status, see the Data Sheet Status table

| Symbol | Description | Min | Typ | Max | Unit | |-----------|-----------------------------------------------|-------|--------|-------|--------| | F usb_clk | USB_CLK clock frequency | - | 60 | - | MHz | | T usb_clk | USB_CLK clock period | - | 16.667 | - | ns | | T d | Clock to USB_STP/ USB_DATA[7:0] output delay | 2 | - | 7 | ns | | T su | Setup time for USB_DIR/ USB_NXT/USB_DATA[7:0] | 4 | - | - | ns | | T h | Hold time for USB_DIR/ USB_NXT/USB_DATA[7:0] | 1 | - | - | ns |

Figure 18. USB ULPI Timing Diagram

Note: The USB interface supports single data rate (SDR) timing only.

Note:

If you need to adjust the timings of certain signals, you can use the HPS registers Pin_Mux.io0_delay through Pin_Mux.io47_delay to allow software to set the delay chains in each of the dedicated I/Os. For example, to add output and input delay to the USB_DATA3 signal (HPS_IOA_8), program Pin_Mux.io7_delay.output_val_en = 1, and Pin_Mux.io7_delay.output_val = 15 to add approximately 1.4 ns output delay from the HPS, and program Pin_Mux.io7_delay.input_val_en = 3, and Pin_Mux.io7_delay.input_val = 30 to add approximately 2.8 ns input delay into the HPS. See HPS Programmable I/O Timing Characteristics for more information.

HPS USB 3.1 Timing Characteristics

Table 97. HPS USB 3.1 Transceiver Macrocell Interface Plus (UTMI+) Low Pin Interface (ULPI) Timing Requirements

For specification status, see the Data Sheet Status table

Figure 19. USB ULPI Timing Diagram

Note:

The USB interface supports single data rate (SDR) timing only.

Note:

HPS Ethernet Media Access Controller (EMAC) Timing Characteristics

Table 98. Reduced Gigabit Media Independent Interface (RGMII) TX Timing Requirements

For specification status, see the Data Sheet Status table

| Symbol | Description | Minimum | Typical | Maximum | Unit | |----------------------------|----------------------------------|-----------|-----------|-----------|--------| | T clk (1000Base-T) | TX_CLK clock period (125 MHz) | - | 8 | - | ns | | T clk (100Base-T) | TX_CLK clock period (25 MHz) | - | 40 | - | ns | | T clk (10Base-T) | TX_CLK clock period (2.5 MHz) | - | 400 | - | ns | | T dutycycle (1000Base-T) | TX_CLK duty cycle | 45 | 50 | 55 | % | | T dutycycle (10/100Base-T) | TX_CLK duty cycle | 40 | 50 | 60 | % | | T d (162) (163) | TXD/TX_CTL to TX_CLK output skew | -0.5 | - | 0.5 | ns |

Figure 20. RGMII TX Timing Diagram

Table 99. RGMII RX Timing Requirements

For specification status, see the Data Sheet Status table

| Symbol | Description | Minimum | Typical | Maximum | Unit | |----------------------------|----------------------------------|-----------|-----------|-----------|--------| | T clk (1000Base-T) | RX_CLK clock period (125 MHz) | - | 8 | - | ns | | T clk (100Base-T) | RX_CLK clock period (25 MHz) | - | 40 | - | ns | | T clk (10Base-T) | RX_CLK clock period (2.5 MHz) | - | 400 | - | ns | | T dutycycle (1000Base-T) | RX_CLK duty cycle | 45 | 50 | 55 | % | | T dutycycle (10/100Base-T) | RX_CLK duty cycle | 40 | 50 | 60 | % | | T su | RX_D/RX_CTL to RX_CLK setup time | 1 | - | - | ns | | T h (164) | RX_CLK to RX_D/RX_CTL hold time | 1 | - | - | ns |

Figure 21. RGMII RX Timing Diagram

Table 100. Management Data Input/Output (MDIO) Timing Requirements

For specification status, see the Data Sheet Status table

| Symbol | Description | Minimum | Typical | Maximum | Unit | |----------|-------------------------------|-----------|-----------|-----------|--------| | F clk | MDC clock frequency | - | - | 2.5 | MHz | | T clk | MDC clock period | 400 | - | - | ns | | T d | MDC to MDIO output data delay | 10 | - | 300 | ns | | T su | Setup time for MDIO data | 10 | - | - | ns | | T h | Hold time for MDIO data | 0 | - | - | ns |

Figure 22. MDIO Timing Diagram

SGMII Timing Requirements

SGMII operating mode is supported through FPGA fabric using SGMII PCS soft IP and LVDS SERDES FPGA IP. Refer to the LVDS SERDES Specifications section for timing specifications.

SGMII+ operating mode is supported through FPGA fabric using SGMII+ PCS soft IP and serial transceiver interface. Refer to the Transceiver Performance Specifications section for timing specifications.

Related Information

LVDS SERDES Specifications on page 80
GTS Transceiver Performance Specifications on page 96

HPS I 2 C Timing Characteristics

Table 101. HPS I 2 C Timing Requirements

For specification status, see the Data Sheet Status table

| Symbol | Description | Standard Mode | Standard Mode | Fast Mode | Fast Mode | Unit | |--------------|------------------------------------|-----------------|-----------------|--------------|--------------|--------------| | Symbol | Description | Min | Max | Min | Max | Unit | | F clk | Serial clock (SCL) clock frequency | - | 100 | - | 400 | KHz | | T clk | Serial clock (SCL) clock period | 10 | - | 2.5 | - | μs | | T clk_jitter | I 2 C clock output jitter | - | 2 | - | 2 | % | | T HIGH (165) | SCL high period | 4 (166) | - | 0.6 (167) | - | μs | | continued... | continued... | continued... | continued... | continued... | continued... | continued... |

| Symbol | Description | Standard Mode | Standard Mode | Fast Mode | Fast Mode | Unit | |-----------------------------|---------------------------------------------------|-----------------|-----------------|-------------|-------------|--------------| | Symbol | Description | Min | Max | Min | Max | Unit | | T LOW (168) | SCL low period | 4.7 (169) | - | 1.3 (170) | - | μs | | T SU_DAT | Setup time for serial data line (SDA) data to SCL | 0.25 | - | 0.1 | - | μs | | T HD_DAT (171) | Hold time for SCL to SDA data | 0 | 3.15 | 0 | 0.6 | μs | | T VD_DAT and T VD_ACK (172) | SCL to SDA output data delay | - | 3.45 (173) | - | 0.9 (174) | μs | | T SU_STA | Setup time for a repeated start condition | 4.7 | - | 0.6 | - | μs | | T HD_STA | Hold time for a repeated start condition | 4 | - | 0.6 | - | μs | | T SU_STO | Setup time for a stop condition | 4 | - | 0.6 | - | μs | | | | | | | | continued... |

| Symbol | Description | Standard Mode | Standard Mode | Fast Mode | Fast Mode | Unit | |---------------|------------------------------------------------|-----------------|-----------------|-------------|-------------|--------| | | | Min | Max | Min | Max | | | T BUF | SDA high pulse duration between STOP and START | 4.7 | - | 1.3 | - | μs | | T scl_r (175) | SCL rise time | - | 1,000 | 20 | 300 | ns | | T scl_f (175) | SCL fall time | - | 300 | 6.54 | 300 | ns | | T sda_r (175) | SDA rise time | - | 1,000 | 20 | 300 | ns | | T sda_f (175) | SDA fall time | - | 300 | 6.54 | 300 | ns |

Figure 23. I 2 C Timing Diagram

HPS I 3 C Timing Characteristics

Table 102. HPS I 3 C Timing Requirements When Communicating With I 2 C Legacy Devices

For specification status, see the Data Sheet Status table

| Symbol | Description | Fast Mode | Fast Mode | Fast Mode Plus | Fast Mode Plus | Unit | |--------------|---------------------------------------------------|------------------|-------------|------------------|------------------|--------------| | Symbol | Description | Min | Max | Min | Max | Unit | | f SCL | Serial clock (SCL) clock frequency | 0 | 0.4 | 0 | 1 | MHz | | T SCL | SCL clock period | 2.5 | - | 1 | - | μs | | T clk_jitter | I 3 C clock output jitter | - | 2 | - | 2 | % | | T HIGH | SCL high period | 600 | - | 260 | - | ns | | T DIG_H | SCL high period | T HIGH + T scl_r | - | T HIGH + T scl_r | - | ns | | T LOW | SCL low period | 1,300 | - | 500 | - | ns | | T DIG_L | SCL low period | T LOW + T scl_r | - | T LOW + T scl_r | - | ns | | T SU_DAT | Setup time for serial data line (SDA) data to SCL | 100 | - | 50 | - | ns | | T HD_DAT | Hold time for SCL to SDA data | - | - | - | - | - | | T SU_STA | Setup time for a repeated start condition | 600 | - | 260 | - | ns | | T HD_STA | Hold time for a repeated start condition | 600 | - | 260 | - | ns | | T SU_STO | Setup time for a stop condition | 600 | - | 260 | - | ns | | T BUF | SDA high pulse duration between STOP and START | 1.3 | - | 0.5 | - | μs | | T scl_r | SCL rise time | 20 | 300 | - | 120 | ns | | | | | | | | continued... |

| Symbol | Description | Fast Mode | Fast Mode | Fast Mode Plus | Fast Mode Plus | Unit | |----------|-----------------------------------------------------------|---------------------------------|-------------|---------------------------------|------------------|--------| | Symbol | Description | Min | Max | Min | Max | Unit | | T scl_f | SCL fall time | 20 × (V CCIO_HPS / 5.5 V) (176) | 300 | 20 × (V CCIO_HPS / 5.5 V) (176) | 120 | ns | | T sda_r | SDA rise time | 20 | 300 | - | 120 | ns | | T sda_f | SDA fall time | 20 × (V CCIO_HPS / 5.5 V) (176) | 300 | 20 × (V CCIO_HPS / 5.5 V) (176) | 120 | ns | | T SPIKE | Pulse width of spikes that the spike filter must suppress | 0 | 50 | 0 | 50 | ns |

Table 103. HPS I 3 C Open Drain Timing Requirements

For specification status, see the Data Sheet Status table

| Symbol | Description | Min | Max | Unit | |-------------------|---------------------------------------------------|---------------------------|------------------|--------------| | T HIGH | SCL high period | - | 41 | ns | | T DIG_H | SCL high period | - | T HIGH + T CF | ns | | T HIGH_INIT (177) | SCL high period (for First Broadcast Address) | 200 | - | ns | | T LOW_OD | SCL low period | 200 | - | ns | | T LOW_OD_L | SCL low period | T LOW_ODmin + T fDA_ODmin | - | ns | | T fDA_OD | SDA signal fall time | T CF | 12 | ns | | T SU_OD | Setup time for serial data line (SDA) data to SCL | 3 | - | ns | | T CAS (178) | Clock after START Condition | 38.4 ns | For ENTAS0: 1 μs | - | | continued... | continued... | continued... | continued... | continued... |

| Symbol | Description | Min | Max | Unit | |-------------|----------------------------------------------------------------|---------------|--------------------|--------| | | | | For ENTAS1: 100 μs | - | | | | | For ENTAS2: 2 ms | - | | | | | For ENTAS3: 50 ms | - | | T CBP | Clock before STOP Condition | T CASmin /2 | - | s | | T MMOverlap | Current master to secondary master overlap time during handoff | T DIG_OD_Lmin | - | ns | | T AVAL | Bus available condition | 1 | - | μs | | T IDLE | Bus IDLE condition | 200 | - | μs | | T MMLock | Time internal where new master not driving SDA Low | T AVALmin | - | μs |

Table 104. HPS I 3 C Push-Pull Timing Requirements for SDR Mode

For specification status, see the Data Sheet Status table

| Symbol | Description | Min | Typ | Max | Unit | |---------------|-------------------------------------------|--------------|--------------|--------------|--------------| | f SCL | Serial clock (SCL) clock frequency | 0.01 | 12.5 | 12.9 | MHz | | T CLK | SCL clock period | 77.5 ns | 80 ns | 100 μs | - | | T HIGH | SCL clock high period | 24 | - | - | ns | | T DIG_H | | 32 | - | - | ns | | T LOW | SCL clock low period | 24 | - | - | ns | | T DIG_L | | 32 | - | - | ns | | T HIGH_MIXED | SCL clock high period for mixed bus (179) | 24 | - | - | ns | | T DIG_H_MIXED | | 32 | - | 45 | ns | | continued... | continued... | continued... | continued... | continued... | continued... |

| Symbol | Description | Min | Typ | Max | Unit | |----------|----------------------------------------|-----------------------|-------|-----------------------------------|--------| | T SCO | Clock in to data out for slave | - | - | 12 | ns | | T CR | SCL rise time | - | - | 150e6 × 1/f SCL (capped at 60 ns) | ns | | T CF | SCL fall time | - | - | 150e6 × 1/f SCL (capped at 60 ns) | ns | | T HD_PP | Hold time for SCL to SDA data (master) | T CR + 3 and T CF + 3 | - | - | ns | | T HD_PP | Hold time for SCL to SDA data (slave) | 0 | - | - | ns | | T SU_PP | SDA signal data setup time | 3 | - | - | ns | | T CASr | Clock after repeated START (Sr) | T CASmin | - | - | ns | | T CBSr | Clock before repeated START (Sr) | T CASmin / 2 | - | - | ns | | C b | Capacitive load per bus Line (SDA/SCL) | - | - | 50 | pF |

Figure 24. I 3 C Legacy Mode Timing Diagram

Figure 25. TDIG_H and TDIG_L

Figure 26. I 3 C Start Condition Timing Diagram

Figure 27. I 3 C Stop Condition Timing Diagram

Figure 28. I 3 C Start Master Out Timing Diagram

Figure 29. I 3 C Slave Out Timing Diagram

Figure 30. Master SDR Timing Diagram

Related Information

HPS Power Supply Operating Conditions on page 34

HPS NAND Timing Characteristics

Table 105. HPS NAND SDR Timing Requirements

Compatible with the ONFI 1.x and 2.x specifications. Compatible with the Toggle 1.x and 2.x specifications. HPS I/O supports SDR, NV-DDR protocols up to 200 MT/s.

For specification status, see the Data Sheet Status table

| Symbol | Description | Min | Max | Unit | |--------------|--------------------------|--------------|--------------|--------------| | T WP (180) | Write enable pulse width | 10 | - | ns | | T WH (180) | Write enable hold time | 7 | - | ns | | continued... | continued... | continued... | continued... | continued... |

| Symbol | Description | Min | Max | Unit | |-------------|-------------------------------------------------|-------|-------|--------| | T RP (180) | Read enable pulse width | 10 | - | ns | | T REH (180) | Read enable hold time | 7 | - | ns | | T CLS (180) | Command latch enable to write enable setup time | 10 | - | ns | | T CLH (180) | Command latch enable to write enable hold time | 5 | - | ns | | T CS (180) | Chip enable to write enable setup time | 15 | - | ns | | T CH (180) | Chip enable to write enable hold time | 5 | - | ns | | T ALS (180) | Address latch enable to write enable setup time | 10 | - | ns | | T ALH (180) | Address latch enable to write enable hold time | 5 | - | ns | | T DS (180) | Data to write enable setup time | 7 | - | ns | | T DH (180) | Data to write enable hold time | 5 | - | ns | | T WB (180) | Write enable high to R/B low | - | 200 | ns | | T CEA | Chip enable to data access time | - | 100 | ns | | T REA | Read enable to data access time | - | 40 | ns | | T RHZ | Read enable to data high impedance | - | 200 | ns | | T RR | Ready to read enable low | 20 | - | ns |

Figure 31. NAND SDR Command Latch Timing Diagram

Figure 32. NAND SDR Address Latch Timing Diagram

Figure 33. NAND SDR Data Output Cycle Timing Diagram

Figure 34. NAND SDR Data Input Cycle Timing Diagram

Figure 35. NAND SDR Data Input Timing Diagram for Extended Data Output (EDO) Cycle

Figure 36. NAND SDR Read Status Timing Diagram

Figure 37. NAND SDR Read Status Enhanced Timing Diagram

Table 106. HPS NAND DDR Timing Requirements

Compatible with the ONFI 1.x and 2.x specifications. Compatible with the Toggle 1.x and 2.x specifications. HPS I/O supports SDR, NV-DDR protocols up to 200 MT/s.

For specification status, see the Data Sheet Status table

| Symbol | Description | 100 MHz (200 MT/s) | 100 MHz (200 MT/s) | 100 MHz (200 MT/s) | |--------------|-----------------------------------------------------------------------------------------|----------------------|----------------------|----------------------| | | | Min | Max | Unit | | t AC | Access window of DQ[7:0] from CLK | 3 | 25 | ns | | t ADL | Address cycle to data loading time | 400 | - | ns | | t CADf | Command, address, data delay (fast) (command to command, address to address, command to | 25 | - | ns | | continued... | continued... | continued... | continued... | continued... |

| Symbol | Description | 100 MHz (200 MT/s) | 100 MHz (200 MT/s) | 100 MHz (200 MT/s) | |-------------------------|--------------------------------------------------------------------------------------------------------------------------------------------------------|-----------------------------------------|----------------------------|----------------------| | | | Min | Max | Unit | | | address, address to command, command/address to start of data) | | | | | t CADs | Command, address, data delay (slow) (command to command, address to address, command to address, address to command, command/address to start of data) | 45 | - | ns | | t CAH | Command/address DQ hold time | 2 | - | ns | | t CALH | W/R_n, CLE, and ALE hold time | 2 | - | ns | | t CALS | W/R_n, CLE, and ALE setup time | 2 | - | ns | | t CAS | Command/address DQ setup time | 2 | - | ns | | t CEH | CE_n high hold time | 20 | - | ns | | t CH | CE_n hold time | 2 | - | ns | | t CK(avg) or t CK (181) | Average clock cycle time | 10 | - | ns | | t CK(abs) | Absolute clock period, measured from rising edge to the next consecutive rising edge | t CK(avg) + t JIT(per) min | t CK(avg) + t JIT(per) max | ns | | t CKH(abs) (182) | Clock cycle high | 0.43 | 0.57 | t CK | | t CKL(abs) (182) | Clock cycle low | 0.43 | 0.57 | t CK | | t CKWR | Data output end to W/R_n high | RoundUp{[t DQSCK(max) + t CK ] / t CK } | - | t CK | | | | | | continued... |

| Symbol | Description | 100 MHz (200 MT/s) | 100 MHz (200 MT/s) | 100 MHz (200 MT/s) | |---------------|-----------------------------------------------------------------------------------------------|----------------------|----------------------|----------------------| | Symbol | Description | Min | Max | Unit | | t CS3 | CE_n setup time for data input and data output after CE_n has been high for greater than 1 µs | 75 | - | ns | | t CS | CE_n setup time | 15 | - | ns | | t DH | Data hold time | 0.9 | - | ns | | t DPZ | Data input pause setup time | 1.5 | - | t DSC | | t DQSCK | Access window of DQS from CLK | 3 | 25 | ns | | t DQSD | W/R_n low to DQS/DQ driven by device | 0 | 18 | ns | | t DQSH (183) | DQS input high pulse width | 0.4 | 0.6 | t CK or t DSC4 | | t DQSHZ (184) | W/R_n high to DQS/DQ tri-state by device | - | 20 | ns | | t DQSL (183) | DQS input low pulse width | 0.4 | 0.6 | t CK or t DSC4 | | t DQSQ | DQS-DQ skew, DQS to last DQ valid, per access | - | 0.85 | ns | | t DQSS | Data input to first DQS latching transition | 0.75 | 1.25 | t CK | | t DS | Data setup time | 0.9 | - | ns | | t DSC | DQS cycle time | 10 | - | ns | | t DSH | DQS falling edge to CLK rising - hold time | 0.2 | - | t CK | | t DSS | DQS falling edge to CLK rising - setup time | 0.2 | - | t CK | | t DVW | Output data valid window | DVW = t QH - t DQSQ | DVW = t QH - t DQSQ | ns | | | | | | continued... |

| Symbol | Description | 100 MHz (200 MT/s) | 100 MHz (200 MT/s) | 100 MHz (200 MT/s) | |-----------------------|----------------------------------------------------------------------------------------|--------------------------|--------------------------|----------------------| | Symbol | Description | Min | Max | Unit | | t FEAT | Busy time for Set Features and Get Features | - | 1 | µs | | t HP | Half-clock period | HP = min(t CKL , t CKH ) | HP = min(t CKL , t CKH ) | ns | | t ITC | Interface and Timing Mode Change time | - | 1 | µs | | t JIT(per) | The deviation of a given t CK(abs) from t CK(avg) | -0.5 | 0.5 | ns | | t QH | DQ-DQS hold, DQS to first DQ to go non-valid, per access | QH = t HP - t QHS | QH = t HP - t QHS | ns | | t QHS | Data hold skew factor | - | 1 | ns | | t RHW | Data output cycle to command, address, or data input cycle | 100 | - | ns | | t RR | Ready to data output cycle (data only) | 20 | - | ns | | t RST (raw NAND) | Device reset time, measured from the falling edge of R/B_n to the rising edge of R/B_n | - | 15/30/500 | µs | | t RST (EZ NAND) (185) | Device reset time, measured from the falling edge of R/B_n to the rising edge of R/B_n | - | 150/150/500 | µs | | t WB | (WE_n high or CLK rising edge) to SR[6] low | - | 100 | ns | | t WHR | Command, address, or data input cycle to data output cycle | 80 | - | ns | | t WPRE | DQS write preamble | 1.5 | - | t CK | | continued... | continued... | continued... | continued... | continued... |

| Symbol | Description | 100 MHz (200 MT/s) | 100 MHz (200 MT/s) | 100 MHz (200 MT/s) | |----------|----------------------------------|----------------------|----------------------|----------------------| | | | Min | Max | Unit | | t WPST | DQS write postamble | 1.5 | - | t CK | | t WRCK | W/R_n low to data output cycle | 20 | - | ns | | t WW | WP_n transition to command cycle | 100 | - | ns |

Figure 38. NAND DDR Command Cycle Timing Diagram

Figure 39. NAND DDR Address Cycle Timing Diagram

Figure 40. NAND DDR Data Input Cycle Timing Diagram

Figure 41. NAND DDR Data Input Cycle Timing Diagram (CLK Stopped)

Figure 42. NAND DDR Data Input Cycle Timing Diagram (CLK Stopped with Data Pause)

Figure 43. NAND DDR Data Output Cycle Timing Diagram

Figure 44. NAND DDR W/R_n Timing Diagram

Figure 45. NAND DDR Read Status Including tWHR and tCAD Timing Diagram

HPS Trace Timing Characteristics

Table 107. Trace Timing Requirements

To increase the trace bandwidth, Altera recommends routing the trace interface to the FPGA in the HPS Platform Designer component. The FPGA trace interface offers a 64-bit single data rate path that can be converted to double data rate to minimize FPGA I/O usage.

Depending on the trace module that you connect to the HPS trace interface, you may need to include board termination to achieve the maximum sampling speed possible. Refer to your trace module data sheet for termination recommendations.

Most trace modules implement programmable clock and data skew to improve trace data timing margins. Alternatively, you can change the clock-to-data timing relationship with the HPS programmable I/O delay.

For specification status, see the Data Sheet Status table

| Symbol | Description | Minimum | Typical | Maximum | Unit | |--------------|-----------------------|--------------|--------------|--------------|--------------| | F clk | Trace clock frequency | - | - | 200 | MHz | | T clk | Trace clock period | 5 | - | - | ns | | continued... | continued... | continued... | continued... | continued... | continued... |

Figure 46. Trace Timing Diagram

| Symbol | Description | Minimum | Typical | Maximum | Unit | |--------------|-----------------------------------|-----------|-----------|-----------|--------| | T clk_jitter | Trace clock output jitter | - | - | 2 | % | | T dutycycle | Trace clock maximum duty cycle | 45 | 50 | 55 | % | | T d | T clk to D0-D15 output data delay | -0.5 | - | 1.3 | ns |

HPS GPIO Interface

The general-purpose I/O (GPIO) interface has debounce circuitry included to remove signal glitches. The debounce clock frequency ranges from 125 Hz to 32 kHz. The minimum pulse width is 1 debounce clock cycle and the minimum detectable GPIO pulse width is 62.5 µs (at 32 kHz).

If the external signal is driven into the GPIO for less than one clock cycle, the external signal is filtered. If the external signal is between one and two clock cycles, the external signal may or may not be filtered depending on the phase of the signal. If the external signal is more than two clock cycles, the external signal is not filtered.

The GPIO modules provided in the HPS include optional debounce capabilities. The external signal can be debounced to remove any spurious glitches that are less than one period of the external debouncing clock, gpio_db_clk .

HPS JTAG Timing Characteristics

Table 108. HPS JTAG Timing Requirements

For specification status, see the Data Sheet Status table

| Symbol | Description | Min | Typ | Max | Unit | |--------------|------------------------------------------|-------|-------|-------|--------| | F JCP | TCK clock frequency | - | - | 33.33 | MHz | | t JCP | TCK clock period | 30 | - | - | ns | | t JCH | TCK clock high time | 20 | - | - | ns | | t JCL | TCK clock low time | 20 | - | - | ns | | t JPSU (TDI) | TDI JTAG port setup time | 5 | - | - | ns | | t JPSU (TMS) | TMS JTAG port setup time | 5 | - | - | ns | | t JPH | JTAG port hold time | 0.5 | - | - | ns | | t JPCO | JTAG port clock to output | 0 | - | 8 | ns | | t JPZX | JTAG port high impedance to valid output | - | - | 10 | ns | | t JPXZ | JTAG port valid output to high impedance | - | - | 10 | ns |

Figure 47. HPS JTAG Timing Diagram

HPS Programmable I/O Timing Characteristics

Table 109. HPS Programmable I/O Delay (Output Path)

For specification status, see the Data Sheet Status table

| Name | output_val_en | output_val | Description | Min | Typ | Max | Unit | |--------------------|-----------------|--------------|-------------------------------------------------|-------|-------|-------|--------------| | ZERO_CHAIN_DEL AY | 0 | 0 | Intrinsic I/O delay. Bypasses the delay chain | - | 0 | - | ps | | CHAIN_DELAY | 1 | 0 | Intrinsic I/O delay + Minimum + 0 × Chain Delay | - | 0 | - | ps | | ONE_CHAIN_DELA Y | 1 | 1 | Intrinsic I/O delay + Minimum + 1 × Chain Delay | - | 208 | - | ps | | TWO_CHAIN_DELA Y | 1 | 2 | Intrinsic I/O delay + Minimum + 2 × Chain Delay | - | 353 | - | ps | | THREE_CHAIN_DEL AY | 1 | 3 | Intrinsic I/O delay + Minimum + 3 × Chain Delay | - | 413 | - | ps | | FOUR_CHAIN_DEL AY | 1 | 4 | Intrinsic I/O delay + Minimum + 4 × Chain Delay | - | 524 | - | ps | | FIVE_CHAIN_DELA Y | 1 | 5 | Intrinsic I/O delay + Minimum + 5 × Chain Delay | - | 623 | - | ps | | SIX_CHAIN_DELAY | 1 | 6 | Intrinsic I/O delay + Minimum + 6 × Chain Delay | - | 744 | - | ps | | SEVEN_CHAIN_DEL AY | 1 | 7 | Intrinsic I/O delay + Minimum + 7 × Chain Delay | - | 878 | - | ps | | EIGHT_CHAIN_DEL AY | 1 | 8 | Intrinsic I/O delay + Minimum + 8 × Chain Delay | - | 977 | - | ps | | | | | | | | | continued... |

| Name | output_val_en | output_val | Description | Min | Typ | Max | Unit | |------------------------|-----------------|--------------|--------------------------------------------------|-------|-------|--------------|--------------| | NINE_CHAIN_DELA Y | 1 | 9 | Intrinsic I/O delay + Minimum + 9 × Chain Delay | - | 1,067 | - | ps | | TEN_CHAIN_DELAY | 1 | 10 | Intrinsic I/O delay + Minimum + 10 × Chain Delay | - | 1,170 | - | ps | | ELEVEN_CHAIN_DE LAY | 1 | 11 | Intrinsic I/O delay + Minimum + 11 × Chain Delay | - | 1,309 | - | ps | | TWELVE_CHAIN_D ELAY | 1 | 12 | Intrinsic I/O delay + Minimum + 12 × Chain Delay | - | 1,366 | - | ps | | THIRTEEN_CHAIN_ DELAY | 1 | 13 | Intrinsic I/O delay + Minimum + 13 × Chain Delay | - | 1,499 | - | ps | | FOURTEEN_CHAIN _DELAY | 1 | 14 | Intrinsic I/O delay + Minimum + 14 × Chain Delay | - | 1,604 | - | ps | | FIFTEEN_CHAIN_D ELAY | 1 | 15 | Intrinsic I/O delay + Minimum + 15 × Chain Delay | - | 1,760 | - | ps | | - | 1 | [16:30] | INVALID | - | - | - | - | | - | 2 | - | INVALID | - | - | - | - | | - | 3 | [0:15] | INVALID | - | - | - | - | | SIXTEEN_CHAIN_D ELAY | 3 | 16 | Intrinsic I/O delay + Minimum + 16 × Chain Delay | - | 1,994 | - | ps | | SEVENTEEN_CHAIN DELAY | 3 | 17 | Intrinsic I/O delay + Minimum + 17 × Chain Delay | - | 2,038 | - | ps | | EIGHTEEN_CHAIN DELAY | 3 | 18 | Intrinsic I/O delay + Minimum + 18 × Chain Delay | - | 2,169 | - | ps | | | | | | | | continued... | continued... |

| Name | output_val_en | output_val | Description | Min | Typ | Max | Unit | |--------------------------|-----------------|--------------|--------------------------------------------------|-------|-------|-------|--------| | NINETEEN_CHAIN_ DELAY | 3 | 19 | Intrinsic I/O delay + Minimum + 19 × Chain Delay | - | 2,260 | - | ps | | TWENTY_CHAIN_D ELAY | 3 | 20 | Intrinsic I/O delay + Minimum + 20 × Chain Delay | - | 2,433 | - | ps | | TWENTYONE_CHAI N_DELAY | 3 | 21 | Intrinsic I/O delay + Minimum + 21 × Chain Delay | - | 2,476 | - | ps | | TWENTYTWO_CHAI N_DELAY | 3 | 22 | Intrinsic I/O delay + Minimum + 22 × Chain Delay | - | 2,645 | - | ps | | TWENTYTHREE_CH AIN_DELAY | 3 | 23 | Intrinsic I/O delay + Minimum + 23 × Chain Delay | - | 2,684 | - | ps | | TWENTYFOUR_CHA IN_DELAY | 3 | 24 | Intrinsic I/O delay + Minimum + 24 × Chain Delay | - | 2,858 | - | ps | | TWENTYFIVE_CHAI N_DELAY | 3 | 25 | Intrinsic I/O delay + Minimum + 25 × Chain Delay | - | 2,907 | - | ps | | TWENTYSIX_CHAIN _DELAY | 3 | 26 | Intrinsic I/O delay + Minimum + 26 × Chain Delay | - | 3,054 | - | ps | | TWENTYSEVEN_CH AIN_DELAY | 3 | 27 | Intrinsic I/O delay + Minimum + 27 × Chain Delay | - | 3,123 | - | ps | | TWENTYEIGHT_CH AIN_DELAY | 3 | 28 | Intrinsic I/O delay + Minimum + 28 × Chain Delay | - | 3,259 | - | ps | | TWENTYNINE_CHA IN_DELAY | 3 | 29 | Intrinsic I/O delay + Minimum + 29 × Chain Delay | - | 3,301 | - | ps | | THIRTY_CHAIN_DE LAY | 3 | 30 | Intrinsic I/O delay + Minimum + 30 × Chain Delay | - | 3,488 | - | ps |

Table 110. HPS Programmable I/O Delay (Input Path)

For specification status, see the Data Sheet Status table

| Name | input_val_en | input_val | Description | Min | Typ | Max | Unit | |--------------------|----------------|-------------|-------------------------------------------------|-------|-------|-------|--------------| | ZERO_CHAIN_DEL AY | 0 | 0 | Intrinsic I/O delay. Bypasses the delay chain | - | 0 | - | ps | | CHAIN_DELAY | 1 | 0 | Intrinsic I/O delay + Minimum + 0 × Chain Delay | - | 0 | - | ps | | ONE_CHAIN_DELA Y | 1 | 1 | Intrinsic I/O delay + Minimum + 1 × Chain Delay | - | 208 | - | ps | | TWO_CHAIN_DELA Y | 1 | 2 | Intrinsic I/O delay + Minimum + 2 × Chain Delay | - | 353 | - | ps | | THREE_CHAIN_DEL AY | 1 | 3 | Intrinsic I/O delay + Minimum + 3 × Chain Delay | - | 413 | - | ps | | FOUR_CHAIN_DEL AY | 1 | 4 | Intrinsic I/O delay + Minimum + 4 × Chain Delay | - | 524 | - | ps | | FIVE_CHAIN_DELA Y | 1 | 5 | Intrinsic I/O delay + Minimum + 5 × Chain Delay | - | 623 | - | ps | | SIX_CHAIN_DELAY | 1 | 6 | Intrinsic I/O delay + Minimum + 6 × Chain Delay | - | 744 | - | ps | | SEVEN_CHAIN_DEL AY | 1 | 7 | Intrinsic I/O delay + Minimum + 7 × Chain Delay | - | 878 | - | ps | | EIGHT_CHAIN_DEL AY | 1 | 8 | Intrinsic I/O delay + Minimum + 8 × Chain Delay | - | 977 | - | ps | | NINE_CHAIN_DELA Y | 1 | 9 | Intrinsic I/O delay + Minimum + 9 × Chain Delay | - | 1,067 | - | ps | | | | | | | | | continued... |

| Name | input_val_en | input_val | Description | Min | Typ | Max | Unit | |------------------------|----------------|-------------|--------------------------------------------------|-------|-------|-------|--------------| | TEN_CHAIN_DELAY | 1 | 10 | Intrinsic I/O delay + Minimum + 10 × Chain Delay | - | 1,170 | - | ps | | ELEVEN_CHAIN_DE LAY | 1 | 11 | Intrinsic I/O delay + Minimum + 11 × Chain Delay | - | 1,309 | - | ps | | TWELVE_CHAIN_D ELAY | 1 | 12 | Intrinsic I/O delay + Minimum + 12 × Chain Delay | - | 1,366 | - | ps | | THIRTEEN_CHAIN_ DELAY | 1 | 13 | Intrinsic I/O delay + Minimum + 13 × Chain Delay | - | 1,499 | - | ps | | FOURTEEN_CHAIN DELAY | 1 | 14 | Intrinsic I/O delay + Minimum + 14 × Chain Delay | - | 1,604 | - | ps | | FIFTEEN_CHAIN_D ELAY | 1 | 15 | Intrinsic I/O delay + Minimum + 15 × Chain Delay | - | 1,760 | - | ps | | - | 1 | [16:30] | INVALID | - | - | - | - | | - | 2 | - | INVALID | - | - | - | - | | - | 3 | [0:15] | INVALID | - | - | - | - | | SIXTEEN_CHAIN_D ELAY | 3 | 16 | Intrinsic I/O delay + Minimum + 16 × Chain Delay | - | 1,994 | - | ps | | SEVENTEEN_CHAIN DELAY | 3 | 17 | Intrinsic I/O delay + Minimum + 17 × Chain Delay | - | 2,038 | - | ps | | EIGHTEEN_CHAIN DELAY | 3 | 18 | Intrinsic I/O delay + Minimum + 18 × Chain Delay | - | 2,169 | - | ps | | NINETEEN_CHAIN DELAY | 3 | 19 | Intrinsic I/O delay + Minimum + 19 × Chain Delay | - | 2,260 | - | ps | | | | | | | | | continued... |

| Name | input_val_en | input_val | Description | Min | Typ | Max | Unit | |--------------------------|----------------|-------------|--------------------------------------------------|-------|-------|-------|--------| | TWENTY_CHAIN_D ELAY | 3 | 20 | Intrinsic I/O delay + Minimum + 20 × Chain Delay | - | 2,433 | - | ps | | TWENTYONE_CHAI N_DELAY | 3 | 21 | Intrinsic I/O delay + Minimum + 21 × Chain Delay | - | 2,476 | - | ps | | TWENTYTWO_CHAI N_DELAY | 3 | 22 | Intrinsic I/O delay + Minimum + 22 × Chain Delay | - | 2,645 | - | ps | | TWENTYTHREE_CH AIN_DELAY | 3 | 23 | Intrinsic I/O delay + Minimum + 23 × Chain Delay | - | 2,684 | - | ps | | TWENTYFOUR_CHA IN_DELAY | 3 | 24 | Intrinsic I/O delay + Minimum + 24 × Chain Delay | - | 2,858 | - | ps | | TWENTYFIVE_CHAI N_DELAY | 3 | 25 | Intrinsic I/O delay + Minimum + 25 × Chain Delay | - | 2,907 | - | ps | | TWENTYSIX_CHAIN _DELAY | 3 | 26 | Intrinsic I/O delay + Minimum + 26 × Chain Delay | - | 3,054 | - | ps | | TWENTYSEVEN_CH AIN_DELAY | 3 | 27 | Intrinsic I/O delay + Minimum + 27 × Chain Delay | - | 3,123 | - | ps | | TWENTYEIGHT_CH AIN_DELAY | 3 | 28 | Intrinsic I/O delay + Minimum + 28 × Chain Delay | - | 3,259 | - | ps | | TWENTYNINE_CHA IN_DELAY | 3 | 29 | Intrinsic I/O delay + Minimum + 29 × Chain Delay | - | 3,301 | - | ps | | THIRTY_CHAIN_DE LAY | 3 | 30 | Intrinsic I/O delay + Minimum + 30 × Chain Delay | - | 3,488 | - | ps |

You can program the number of delay steps by adjusting the I/O Delay register ( io0_delay through io47_delay for I/Os 0 through 47).

Configuration Specifications

General Configuration Timing Specifications

Table 111. General Configuration Timing Specifications

For specification status, see the Data Sheet Status table

| Symbol | Description | Requirement | Requirement | Unit | |-----------------|-------------------------------------------------------------------------------------------|---------------|---------------|--------| | | | Min | Max | | | t CF12ST1 | nCONFIG high to nSTATUS high | - | 20 | ms | | t CF02ST0 (186) | nCONFIG low to nSTATUS low | - | 400 | ms | | t ST0 | nSTATUS low pulse during configuration error | 0.5 | 10 | ms | | t CD2UM (187) | CONF_DONE high to user mode | - | 5 | ms | | t ST12CF0 | Minimum time to drive nCONFIG from high to low after nSTATUS transitions from low to high | 0 | - | ms | | t ST02CF1 | Minimum time to drive nCONFIG from low to high after nSTATUS transitions from high to low | 0 | - | ms |

Figure 48. General Configuration Timing Diagram

POR Specifications

Power-on reset (POR) delay is defined as the delay between the last power rail monitored by the POR circuitry from Group 2B to reach the minimum operating condition voltage to the time your device is ready to begin configuration.

Table 112. POR Delay Specifications

For specification status, see the Data Sheet Status table

| POR Delay | Minimum | Maximum | Unit | |-------------------------------------|-----------|-----------|--------| | AS (Normal mode), AVST ×8, AVST ×16 | 11.5 | 20.2 | ms | | AS (Fast mode) | 1.5 | 7.6 | ms |

External Configuration Clock Source Requirements

Table 113. External Configuration Clock Source (OSC_CLK_1) Clock Input Requirements

For specification status, see the Data Sheet Status table

| Description | External Clock Source | Minimum | Typical | Maximum | Unit | |--------------------------------------------------|-------------------------|------------|------------|------------|--------| | Clock input frequency (188) | Powered by V CCIO_SDM | 25/100/125 | 25/100/125 | 25/100/125 | MHz | | Clock input peak-to-peak period jitter tolerance | Powered by V CCIO_SDM | - | - | 2 | % | | Clock input duty cycle | Powered by V CCIO_SDM | 45 | 50 | 55 | % |

JTAG Configuration Timing

Table 114. JTAG Timing Parameters and Values

For specification status, see the Data Sheet Status table

| Symbol | Description | Requirement | Requirement | Unit | |--------------------|--------------------------|---------------|---------------|--------------| | | | Minimum | Maximum | | | t JCP | TCK clock period | 30 | - | ns | | t JCH | TCK clock high time | 14 | - | ns | | t JCL | TCK clock low time | 14 | - | ns | | t JPSU (TDI) (189) | TDI JTAG port setup time | 2 | - | ns | | t JPSU (TMS) (189) | TMS JTAG port setup time | 3 | - | ns | | t JPH (189) | JTAG port hold time | 5 | - | ns | | continued... | continued... | continued... | continued... | continued... |

Figure 49. JTAG Timing Diagram

| Symbol | Description | Requirement | Requirement | Unit | |----------|------------------------------------------|---------------|---------------|--------| | | | Minimum | Maximum | | | t JPCO | JTAG port clock to output | - | 7 (190) | ns | | t JPZX | JTAG port high impedance to valid output | - | 14 | ns | | t JPXZ | JTAG port valid output to high impedance | - | 14 | ns |

AS Configuration Timing

Table 115. AS Timing Parameters

Altera recommends performing trace length matching for nCSO and AS_DATA pins to AS_CLK to minimize the skew.

For specification status, see the Data Sheet Status table

| Symbol | Description | Minimum | Typical | Maximum | Unit | |--------------|---------------------|--------------|--------------|--------------|--------------| | T clk (191) | AS_CLK clock period | - | 6.02 | - | ns | | T dutycycle | AS_CLK duty cycle | 45 | 50 | 55 | % | | continued... | continued... | continued... | continued... | continued... | continued... |

| Symbol | Description | Minimum | Typical | Maximum | Unit | |-------------------------------|------------------------------------------------|--------------|--------------|--------------|--------------| | T dcsfrs | AS_nCSO[3:0] asserted to first AS_CLK edge | 8.5 (192) | - | - | ns | | T dcslst | Last AS_CLK edge to AS_nCSO[3:0] deasserted | 6.8 (192) | - | - | ns | | T do (193) | AS_DATA[3:0] output delay | -0.6 | - | 0.6 | ns | | T ext_delay (194) (195) (196) | Total external propagation delay on AS signals | - | - | 13.5 | ns | | continued... | continued... | continued... | continued... | continued... | continued... |

Tsu = Tclk/2 - Tdo(max) + Tbd_clk - Tbd_data(max)
Tho = Tclk/2 + Tdo(min) - Tbd_clk + Tbd_data(min)
(194) Text_delay = Tbd_clk + Tco + Tbd_data + Tadd
Tbd_clk: Propagation delay for AS_CLK between FPGA and flash device.
Tco: Output hold time and clock low to output valid of flash device. This delay must be used to ensure Text_delay is within the minimum and maximum specification values.
Tbd_data: Propagation delay for AS_DATA bus between FPGA and flash device.
Tadd: Propagation delay for active/passive components on AS_DATA interfaces.
(195) Text_delay specification is based on AS_CLK = 166 MHz. The value can be larger at lower AS_CLK frequency.
(196) Meeting Text_delay timing specifications indicates that the AS_DATA setup/hold timing is met.

| Symbol | Description | Minimum | Typical | Maximum | Unit | |---------------------------|------------------------------------------------------------------------------|-------------------------------------------------------------------------------------------------|-------------------------------------------------------------------------------------------------|-------------------------------------------------------------------------------------------------|--------| | T dcsb2b | Minimum delay of slave select deassertion between two back-to-back transfers | 62 | - | - | ns | | Skew ( AS_CLK - AS_nCSO ) | Maximum skew tolerance between nCSO and AS_CLK | T su_ncso - T dcsfrs < Skew ( AS_CLK - AS_nCSO ) < AS_CLK /2 + T dcslst T ho_ncso (197) | T su_ncso - T dcsfrs < Skew ( AS_CLK - AS_nCSO ) < AS_CLK /2 + T dcslst T ho_ncso (197) | T su_ncso - T dcsfrs < Skew ( AS_CLK - AS_nCSO ) < AS_CLK /2 + T dcslst T ho_ncso (197) | ns | | Skew ( AS_CLK - AS_DATA ) | Maximum skew tolerance between AS_CLK and AS_DATA | - AS_CLK /2 + T do(max) + T su < Skew ( AS_CLK - AS_DATA ) < AS_CLK /2 + T do(min) - T ho (197) | - AS_CLK /2 + T do(max) + T su < Skew ( AS_CLK - AS_DATA ) < AS_CLK /2 + T do(min) - T ho (197) | - AS_CLK /2 + T do(max) + T su < Skew ( AS_CLK - AS_DATA ) < AS_CLK /2 + T do(min) - T ho (197) | ns |

Figure 50. AS Configuration Serial Output Timing Diagram

Figure 51. AS Configuration Serial Input Timing Diagram

Avalon Streaming Configuration Timing

Table 116. Avalon Streaming Timing Parameters for ×8 and ×16 Configurations

For specification status, see the Data Sheet Status table

| Symbol | Description | Minimum | Unit | |--------------|------------------------------------------------------|-----------|--------| | t ACLKH | AVST_CLK high time | 3.6 | ns | | t ACLKL | AVST_CLK low time | 3.6 | ns | | t ACLKP | AVST_CLK period | 8 | ns | | t ADSU (198) | AVST_DATA setup time before rising edge of AVST_CLK | 2.1 | ns | | t ADH (198) | AVST_DATA hold time after rising edge of AVST_CLK | 0.1 | ns | | t AVSU | AVST_VALID setup time before rising edge of AVST_CLK | 2.1 | ns | | t AVDH | AVST_VALID hold time after rising edge of AVST_CLK | 0 | ns |

Figure 52. Avalon Streaming Configuration Timing Diagram

Configuration Bit Stream Sizes

Table 117. Configuration Bit Stream Sizes

Configuration bit stream sizes shown in this table are based on worst-case scenarios. The sizes are typically substantially smaller because of the use of the bit stream compression. The bit stream compression efficiency has dependency on your design complexity.

128 Mb quad SPI flash size is adequate to store the periphery image.

For specification status, see the Data Sheet Status table

| Variant | Compressed Configuration Bit Stream Size (Mbits) | |---------------------------|----------------------------------------------------| | A5E 005, A5E 007 | 38 | | A5E 008, A5E 013 | 62 | | A5E 043, A5E 052, A5E 065 | 193 | | A5D 051, A5D 064 | 255 |

I/O Timing

I/O timing data is typically used prior to designing the FPGA to get an estimate of the timing budget as part of the timing analysis. You may generate the I/O timing report manually using the Timing Analyzer.

The Quartus Prime Timing Analyzer provides a more accurate and precise I/O timing data based on the specifics of the design after you complete place-and-route.

Programmable IOE Delay

Table 118. Programmable IOE Delay Specifications

For specification status, see the Data Sheet Status table

| Parameter | Maximum Offset | Minimum Offset | Fast Model | Slow Model | Slow Model | Slow Model | Slow Model | Slow Model | Slow Model | Unit | |----------------------------------------------------------|------------------|------------------|--------------|--------------|--------------|--------------|--------------|--------------|------------------------|--------| | Parameter | Maximum Offset | Minimum Offset | Fast Model | -E1V, -I1V | -E2V, -I2V | -E3V, -I3V | -E4S, -I4S | -E5S, -I5S | -E6S, -I6S, -E6X, -I6X | Unit | | Input Delay Chain (INPUT_DELA Y_CHAIN) | 63 | 0 | 1.798 | 2.965 | 3.449 | 4.495 | 4.479 | 4.906 | 6.304 | ns | | Output Delay Chain (OUTPUT_DE LAY_CHAIN) | 15 | 0 | 0.435 | 0.743 | 0.84 | 1.109 | 1.1 | 1.204 | 1.554 | ns | | Output Enable Delay Chain (OUTPUT_EE NABLE_DELA Y_CHAIN) | 15 | 0 | 0.436 | 0.743 | 0.842 | 1.108 | 1.099 | 1.204 | 1.553 | ns |

Glossary

Table 119. Glossary

| Term | Definition | |--------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | t C | V IH(DC) V REF V OH V OL V CCIO V SS V IL(DC) V IH(AC) V IL(AC) | | | High-speed receiver/transmitter input and output clock period. | | TCCS (channel-to-channel-skew) | The timing difference between the fastest and slowest output edges, including the t CO variation and clock skew, across channels driven by the same PLL. The clock is included in the TCCS measurement (refer to the Timing Diagram figure under SW in this table). | | t DUTY | LVDS SERDES block-duty cycle on high-speed transmitter output clock. | | t FALL | Signal high-to-low transition time (80-20%). | | t INCCJ | Cycle-to-cycle jitter tolerance on the PLL clock input. | | t OUTPJ_IO | Period jitter on the GPIO driven by a PLL. | | t OUTPJ_DC | Period jitter on the dedicated clock output driven by a PLL. | | t RISE | Signal low-to-high transition time (20-80%). | | Timing Unit Interval (TUI) | The timing budget allowed for skew, propagation delays, and the data sampling window. (TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = t C /w). | | V CM(DC) | DC Common mode input voltage. | | V ICM | Input Common mode voltage-the common mode of the differential signal at the receiver. | | V ICM(DC) | V CM(DC) DC Common mode input voltage. | | V ID | Input differential voltage swing-the difference in voltage between the positive and complementary conductors of a differential transmission at the receiver. | | V DIF(AC) | AC differential input voltage-minimum AC input differential voltage required for switching. | | continued... | continued... |

| Term | Definition | |-----------|-----------------------------------------------------------------------------------------------------------------------------------------------------------------------| | V DIF(DC) | DC differential input voltage-minimum DC input differential voltage required for switching. | | V IH | Voltage input high-the minimum positive voltage applied to the input which is accepted by the device as a logic high. | | V IH(AC) | High-level AC input voltage. | | V IH(DC) | High-level DC input voltage. | | V IL | Voltage input low-the maximum positive voltage applied to the input which is accepted by the device as a logic low. | | V IL(AC) | Low-level AC input voltage. | | V IL(DC) | Low-level DC input voltage. | | V OCM | Output Common mode voltage-the common mode of the differential signal at the transmitter. | | V OD | Output differential voltage swing-the difference in voltage between the positive and complementary conductors of a differential transmission line at the transmitter. | | V SWING | Differential input voltage. | | V OX | Output differential cross point voltage. | | V IX(AC) | V IX Input differential cross point voltage. | | W | LVDS SERDES block-Clock Boost Factor. |

Document Revision History for the Agilex 5 FPGAs and SoCs Device Data Sheet

| Document Version | Changes | |--------------------|-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | 2025.08.11 | • Updated the minimum V IL and maximum V IN specifications for 2.5 V LVCMOS, 2.5 V LVTTL, 3.3 V LVCMOS, and 3.3 V LVTTL IO standards in the HVIO Single-Ended I/O Standards Specifications table. • Added description to the System PLL Reference Clock (Using HVIO) Specifications table. • Added Input clock or external feedback clock input duty cycle (t EINDUTY ) parameter in the I/O PLL Specifications table. • Updated the specifications for TCK clock frequency (F JCP ) and TCK clock period (t JCP ) in the HPS JTAG Timing Requirements table. • Updated the specifications in the Programmable IOE Delay Specifications table. • Revised the HPS and SDM DC Characteristics and HPS and SDM I/O Standard Specifications , organizing them into individual sections: ○ HPS I/O DC Characteristics ○ SDM I/O DC Characteristics ○ HPS I/O Standard Specifications ○ SDM I/O Standard Specifications • Updated the maximum specifications for Clock Frequency f HSCLK_in (input clock frequency) SLVS400 I/O Standards in the D-Series and E-Series Device Group A FPGAs LVDS SERDES Specifications and E-Series Device Group B FPGAs LVDS SERDES Specifications tables. • Updated the conditions of Tri-stated pin to V O in the HVIO Pin Leakage Current table. • Added footnote about receiver compliance to the V OH in the D-Series FPGAs MIPI D-PHY Low-Power I/O Standards Specifications and E-Series FPGAs MIPI D-PHY Low-Power I/O Standards Specifications tables. • Added POD12 and POD11 parameters for GPIO and PHYLITE modes in the HSIO Single-Ended SSTL, HSTL, HSUL, POD, and LVSTL I/O Reference Voltage Specifications table. • Added LVSTL700 V REF specifications in the HSIO Single-Ended SSTL, HSTL, HSUL, POD, and LVSTL I/O Reference Voltage Specifications table. • Added footnote about POD EMIF Interface to refer to eye mask estimator guidelines in the HSIO Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications and HSIO Differential POD I/O Standards Specifications tables. • Added notes to the True Differential Signaling-1.3 V (LVDS compatible Transmitter and Receiver) specifications in the HSIO Differential I/O Standards Specifications table. • Removed mentions of SLVS in the HSIO OCT Calibration Accuracy Specifications table. • Added SLVS400 I/O standard to the HSIO OCT Without Calibration Resistance Tolerance Specifications table. • Updated the description about overshooting values when using True Differential Signaling I/O standard at V CCIO_PIO at 1.3 V in the Maximum Allowed Overshoot and Undershoot Voltage section. • Updated the HDMI 2.1 specifications lane rate in the Electrical Compliance List table. • Added OIF-CEI-28G VSR/SR/MR and OIF-CEI-25G protocols to the CEI 4.0 Specification in the Electrical Compliance List table. | | 2025.04.07 | • Updated the footnote and removed LP mode (HS) label for M20K block in the D-Series FPGAs Memory Block Performance Specifications (M20K Block) and E-Series FPGAs Memory Block Performance Specifications (M20K Block) tables. • Updated the transmitter t x Jitter and T CCS specifications in the D-Series and E-Series Device Group A FPGAs LVDS SERDES Specifications and E-Series Device Group B FPGAs LVDS SERDES Specifications tables. • Updated V OD (V) to V OD (DC)(V) in the D-Series FPGAs MIPI D-PHY High-Speed I/O Standards Specifications and E-Series FPGAs MIPI D-PHY High- Speed I/O Standards Specifications tables. • Removed QDR-IV XP memory standard in the D-Series FPGAs Memory Standards Supported table. continued... |

| Document Version | Changes | |--------------------|----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | | • Updated the configuration bit stream sizes for A5E005 and A5E007 variants in the Configuration Bit Stream Sizes table. • Updated specifications for the HPS and SDM I/O Pin Leakage Current table. • Removed Max and Typ specifications for the HPS and SDM I/O Hysteresis Specifications for Schmitt Trigger Input table. • Added notes to the HSIO Single-Ended LVSTL I/O Standards Specifications and HSIO Differential LVSTL I/O Standards Specifications tables. • Added footnote for AC input voltage V i (AC) in the Maximum Allowed Overshoot During Transitions for 1.8 V, 2.5V and 3.3 V in HVIO Bank table. • Added note about voltage sensor accuracy specifications in the Voltage Sensor Specifications table. • Added SPIM_CLK frequency in the SPI Master Timing Requirements and SPI Slave Timing Requirements tables. • Added USB_CLK clock frequency in the following tables: ○ HPS USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) Low Pin Interface (ULPI) Timing Requirements ○ HPS USB 3.1 Transceiver Macrocell Interface Plus (UTMI+) Low Pin Interface (ULPI) Timing Requirements • Added Serial Clock (SCL) frequency in the HPS I 2 C Timing Requirements table. • Added Trace clock frequency and updated clock period in the Trace Timing Requirements table. • Added TCK clock frequency in the HPS JTAG Timing Requirements table. • Updated specifications in the HPS Programmable I/O Delay (Output Path) and HPS Programmable I/O Delay (Input Path) tables. • Added footnote for V CO in the -5 and -6 speed grade in the HPS PLL Performance table. • Added MDC clock frequency in the Management Data Input/Output (MDIO) Timing Requirements table. • Updated SCL clock period (T CLK ) specifications in the HPS I 3 C Push-Pull Timing Requirements for SDR mode table. • Added SCL high period (for First Broadcast Address) specification in the HPS I 3 C Open Drain Timing Requirements table. • Updated the description of V in the Recommended Operating Conditions and Absolute Maximum Ratings tables. | | 2025.01.23 | • Updated the 9x9 and 27x27 specifications in the D-Series FPGAs DSP Block Performance Specifications for Multiple DSP Blocks and E-Series FPGAs DSP Block Performance Specifications for Multiple DSP Blocks) tables. • Updated Internal VREF specifications for LVSTL700, LVSTL105 and LVSTL11 I/O standards in the HSIO Single-Ended SSTL, HSTL, HSUL, POD, and LVSTL I/O Reference Voltage Specifications table. • Updated the maximum data rate for True Differential Signaling I/O standards - f HSDR (data rate) when using LVDS SERDES factor J=1 and J=2 in the D-Series and E-Series Device Group A FPGAs LVDS SERDES Specifications and E-Series Device Group B FPGAs LVDS SERDES Specifications tables. • Added the configuration bit stream sizes for A5D 051 and A5D 064 variants in Configuration Bit Stream Sizes table. | | 2024.11.25 | • Updated the minimum value of T ext_delay symbol in the AS Timing Parameters table. • Update the maximum data rate for LVDS SERDES Receiver specifications in the D-Series and E-Series Device Group A FPGAs LVDS SERDES Specifications and D-Series and E-Series Device Group B FPGAs LVDS SERDES Specifications tables. • Minor update on the description in the HVIO Hysteresis Specifications for Schmitt Trigger Input table. • Updated the maximum frequency of DDR4 SDRAM Memory Standards in the D-Series FPGAs Memory Standards Supported and E-Series Device Group B FPGAs Memory Standards Supported tables. • Minor update in the footnote for the Voltage Sensor Specifications table. continued... |

| Document Version | Changes | |--------------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | 2024.08.05 | • Updated the f HSDR data rate (without DPA) in SERDES factor J = 4 and 8 specifications in the D-Series and E-Series Device Group A FPGAs LVDS SERDES Specifications and D-Series and E-Series Device Group B FPGAs LVDS SERDES Specifications tables. • Updated the clause used to IEEE 802.3by for 25GAUI-C2C/C2M in the Electrical Compliance List table. • Updated the Hold time for USB_DIR/USB_NXT/USB_DATA[7:0] (T h ) specifications in the HPS USB UPLI Timing Characteristics table. | | | • Added note on 100 ohm for V CCIO_PIO in HSIO OCT Without Calibration Resistance Tolerance Specifications table. • Updated the minimum timing parameters for t ADSU and t AVSU symbols in Avalon Streaming Timing Parameters for x8 and x16 Configurations table. • Updated the specifications in HVIO I/O Pin Leakage Current table. • Updated the specifications in HVIO Internal Weak Pull-Up and Pull Down Resistor Value table. • Updated the specifications in D-Series FPGAs MIPI D-PHY Low-Power I/O Standards Specifications and E-Series FPGAs MIPI D-PHY Low-Power I/O Standards Specifications tables. • Updated the specifications in the -E6S, -I6S, -E6X and -I6X speed grade in Programmable IOE Delay Specifications table. • Updated the LPDDR5 SDRAM Memory Standard parameters in E-Series Device Group B FPGAs Memory Standards Supported table. • Added footnote for Receiver DPA mode with J-factor 4 and 8 for all speed grade at maximum corner data rates in the following tables: ○ D-Series and E-Series Device Group A FPGAs LVDS SERDES Specifications ○ E-Series Device Group B FPGAs LVDS SERDES Specifications • Updated the Typical values in the HPS Programmable I/O Delay (Output Path) and HPS Programmable I/O Delay (Input Path) tables. • Updated t INCCJ specifications to ±750 ps in I/O PLL Specifications table. • Added CML and HSCL as the supported I/O standards in GTS Transceiver and System PLL Reference Clock Input Specifications table. | | 2024.04.01 | Initial release. | | 2023.08.11 | • Updated the D-Series FPGAs Absolute Maximum Ratings table. ○ Updated the symbol from V CCLHPS_ADC_SDM to V CCL_ADC_SDM and updated description. ○ Added V CCIO_PIO specifications for V CCIO_PIO = 1.0 V. ○ Updated V I specifications and footnote. ○ Updated I OUT specifications and added footnote. • Updated the E-Series FPGAs Absolute Maximum Ratings table. ○ Updated -6L to -6X speed grade. ○ Updated the symbol from V CCLHPS_ADC_SDM to V CCL_ADC_SDM and updated description. ○ Added V CCIO_PIO specifications for V CCIO_PIO = 1.0 V. ○ Updated V I specifications and footnote. ○ Updated I OUT specifications and added footnote. • Updated the description in the Maximum Allowed Overshoot and Undershoot Voltage section and added the following tables: ○ Maximum Allowed Overshoot During Transitions for 1.0 V I/O in HSIO Bank ○ Maximum Allowed Overshoot During Transitions for 1.3 V I/O in HSIO Bank continued... |

| Document Version | Changes | |--------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | | • Updated the D-Series FPGAs Recommended Operating Conditions table. ○ Updated V CCIO_PIO_SDM specifications. ○ Updated the symbol from V CCLHPS_ADC_SDM to V CCL_ADC_SDM and updated description. ○ Updated V CCIO_PIO specifications and footnote. ○ Updated V I specifications and footnote. ○ Added V O specifications for V CCIO_PIO = 1.0 V. ○ Updated t RAMP footnote. • Updated the E-Series FPGAs Recommended Operating Conditions table. ○ Updated -6L to -6X speed grade. ○ Updated V CCH_SDM , V CCIO_PIO_SDM , and V CC_IO_SDM specifications. ○ Updated the symbol from V CCLHPS_ADC_SDM to V CCL_ADC_SDM and updated description. ○ Updated V CCIO_PIO specifications and footnote. ○ Updated V I specifications and footnote. ○ Added V O specifications for V CCIO_PIO = 1.0 V. ○ Updated t RAMP footnote. • Added footnote to maximum value column in the D-Series FPGAs GTS Transceiver Power Supply Operating Conditions table. • Updated the E-Series FPGAs GTS Transceiver Power Supply Operating Conditions table. ○ Added footnote to maximum value column. ○ Updated -6L to -6X speed grade. • Updated the HSIO OCT Calibration Accuracy Specifications table. ○ Removed 50-Ω R S specification. ○ Added footnote to R S and R T . ○ Removed DPHY11 I/O standards support. • Updated the HSIO OCT Without Calibration Resistance Tolerance Specifications table. ○ Added 34-Ω and 40-Ω R S specifications for 1.0 V LVCMOS and 1.3 V LVCMOS I/O standards. ○ Added footnote to R S and R T . • Added specifications for V CCIO_PIO = 1.0 ±5% and V CCIO_PIO = 1.3 ±5% in the HSIO Internal Weak Pull-Up Resistor table. • Updated I I and I OZ specifications for V I = 0 V to V CCIO_HVIO = 2.5 V in the HVIO I/O Pin Leakage Current table. • Updated C IO specification in the HVIO Pin Capacitance table. • Updated V HYS specification for V CCIO_HVIO = 3.3 V in the HVIO Hysteresis Specifications for Schmitt Trigger Input table. • Added specifications for 1.0 V LVCMOS and 1.3 V LVCMOS I/O standards in the HSIO Single-Ended I/O Standards Specifications table. • Updated POD11 and POD12 specifications in the HSIO Single-Ended SSTL, HSTL, HSUL, and POD I/O Reference Voltage Specifications table. • Updated LVSTL11, LVSTL105, and LVSTL700 specifications in the HSIO Single-Ended LVSTL I/O Standards Specifications table. • Added footnote to SSTL-12, HSTL-12, and HSUL-12 in the HSIO Differential SSTL, HSTL, and HSUL I/O Standards Specifications table. • Updated POD11 and POD12 specifications in the HSIO Differential POD I/O Standards Specifications table. | | | continued... |

Metadata

SourceAgilex 5 FPGAs and SoCs Device Data Sheet

Tokens108,904

Chunks205

Chunks (205)

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## Contents 813918 2026.01.05 | Agilex ™ 5 FPGAs and SoCs Device Data Sheet......................................................................................................................

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## Agilex ™ 5 FPGAs and SoCs Device Data Sheet This data sheet describes the electrical characteristics, switching characteristics, configuration specifications, and timing. Until the data sheet st...

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## Table 2. Device Grades, Core Speed Grades, and Power Options Supported For specification status, see the Data Sheet Status table | Series | Device Group | Temperature Grade | Speed Grade ...

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## Operating Conditions Agilex ™ 5 FPGAs and SoCs Device Overview The devices are rated according to a set of defined parameters. To maintain the highest possible performance and reliability of ...

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## Absolute Maximum Ratings This section defines the maximum operating conditions. The values are based on experiments conducted with the devices and theoretical modeling of breakdown and damage mech...

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## Caution: Conditions outside the range listed in the following table may cause permanent damage to the device. Additionally, device operation at the absolute maximum ratings for extended periods of...

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## Table 3. D-Series FPGAs Absolute Maximum Ratings For specification status, see the Data Sheet Status table | Symbol | Description | Condition | Minimum...

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## Table 3. D-Series FPGAs Absolute Maximum Ratings | Symbol | Description ...

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## Table 4. E-Series FPGAs Absolute Maximum Ratings For specification status, see the Data Sheet Status table | Symbol | Description | Condition ...

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## Table 4. E-Series FPGAs Absolute Maximum Ratings | Symbol | Description | Co...

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## Table 4. E-Series FPGAs Absolute Maximum Ratings | Symbol | Description ...

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## Table 4. E-Series FPGAs Absolute Maximum Ratings | Symbol | Description | Conditi...

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## Maximum Allowed Overshoot and Undershoot Voltage - Recommended Operating Conditions on page 22 - I/O Standard Specifications on page 45 - General-Purpose I/O User Guide: Agilex ™ 5 FPGAs and SoCs...

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## Table 5. Maximum Allowed Overshoot During Transitions for 1.0 V I/O in HSIO Bank This table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percent...

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## Table 6. Maximum Allowed Overshoot During Transitions for 1.05 V I/O in HSIO Bank This table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percen...

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## Table 7. Maximum Allowed Overshoot During Transitions for 1.1 V I/O in HSIO Bank This table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percent...

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## Table 8. Maximum Allowed Overshoot During Transitions for 1.2 V I/O in HSIO Bank This table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percent...

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## Table 9. Maximum Allowed Overshoot During Transitions for 1.3 V I/O in HSIO Bank This table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percent...

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## Table 10. Maximum Allowed Overshoot During Transitions for 1.8 V I/O in HPS and SDM I/O Banks This table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage...

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## Table 11. Maximum Allowed Overshoot During Transitions for 1.8 V, 2.5 V, and 3.3 V in HVIO Bank This table lists the maximum allowed input overshoot voltage and the duration of the overshoot volta...

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## Table 12. D-Series FPGAs Recommended Operating Conditions This section lists the functional operation limits for the AC and DC parameters. This table lists the steady-state voltage values ...

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## Table 13. E-Series FPGAs Recommended Operating Conditions This table lists the steady-state voltage values expected. Power supply ramps must all be strictly monotonic, without plateaus. For speci...

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## Table 13. E-Series FPGAs Recommended Operating Conditions | Symbol | Description ...

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## Table 13. E-Series FPGAs Recommended Operating Conditions - (51) For LVCMOS pin utilization of equal to or less than 25 pins within a bank, the VI(DC) for the LVCMOS input can go up to VCCIO\_PIO ...

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## Table 14. D-Series FPGAs GTS Transceiver Power Supply Operating Conditions I/O Standard Specifications on page 45 For specification status, see the Data Sheet Status table | Symbol ...

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## Table 15. E-Series FPGAs GTS Transceiver Power Supply Operating Conditions For specification status, see the Data Sheet Status table | Symbol | Description ...

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## Table 16. D-Series FPGAs HPS Power Supply Operating Conditions This table lists the steady-state voltage and current values expected for system-on-a-chip (SoC) devices with Arm*-based hard process...

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## Table 17. E-Series FPGAs HPS Power Supply Operating Conditions This table lists the steady-state voltage and current values expected for system-on-a-chip (SoC) devices with Arm-based hard processo...

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## Table 17. E-Series FPGAs HPS Power Supply Operating Conditions | Symbol | Description | Condition | Minimum ...

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## Supply Current and Power Consumption - Recommended Operating Conditions on page 22 Provides the steady-state voltage values for the FPGA portion of the device. - HPS Clock Performance on page 107 ...

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## Table 19. HSIO OCT Calibration Accuracy Specifications If you enable on-chip termination (OCT) calibration, calibration is automatically performed at power up for I/Os connected to the calibration...

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## Table 20. HSIO OCT Without Calibration Resistance Tolerance Specifications This table lists the GPIO OCT without calibration resistance tolerance to PVT changes. For specification status, see the...

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## Table 21. HSIO Pin Capacitance For specification status, see the Data Sheet Status table | Symbol | Description | Maximum | Unit | |----------|---------------------...

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## Table 22. HSIO Internal Weak Pull-Up Resistor All I/O pins in GPIO bank have an option to enable weak pull-up when using 1.0 V, 1.05 V, 1.1 V, 1.2 V, and 1.3 V LVCMOS I/O standards. For specific...

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## Table 24. HVIO Pin Capacitance For specification status, see the Data Sheet Status table | Symbol | Description | Maximum | Unit | |----------|---------------------...

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## Table 25. HVIO Internal Weak Pull-Up and Pull-Down Resistor Values Only input and bidirectional pins in HVIO bank have an option to enable weak pull-up and pull-down when using LVCMOS I/O standard...

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## Table 26. HVIO Hysteresis Specifications for Schmitt Trigger Input This device supports built-in Schmitt trigger input that always enabled on HVIO I/O bank. A Schmitt trigger feature introduces hy...

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## Table 28. HPS I/O Pin Capacitance For specification status, see the Data Sheet Status table | Symbol | Description | Maximum | Unit | |----------|------------------...

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## Table 29. HPS Internal Weak Pull-Up Resistor The I/O pins in HPS bank are supported with weak pull-up and weak pull-down options. For specification status, see the Data Sheet Status table | Sym...

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## Table 30. HPS I/O Hysteresis Specifications for Schmitt Trigger Input This device supports Schmitt trigger input on HPS I/O bank. A Schmitt trigger feature introduces hysteresis to the input signa...

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## Table 32. SDM I/O Pin Capacitance For specification status, see the Data Sheet Status table | Symbol | Description | Maximum | Unit | |----------|------------------...

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## Table 33. SDM I/O Internal Weak Pull-Up Resistor The I/O pins in SDM bank are supported with weak pull-up and weak pull-down feature. The weak pull-up and weak pull-down feature is pre-configured ...

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## Table 34. SDM I/O Hysteresis Specifications for Schmitt Trigger Input This device supports Schmitt trigger input on SDM I/O bank. A Schmitt trigger feature introduces hysteresis to the input signa...

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## HSIO I/O Standard Specifications Tables in this section list the supported input voltage (VIH and VIL), output voltage (VOH and VOL), and current drive characteristics (IOH and IOL) for various I/...

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## Table 35. HSIO Single-Ended I/O Standards Specifications Recommended Operating Conditions on page 22 For specification status, see the Data Sheet Status table | I/O Standard | V CCIO_PIO (V) ...

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## Table 36. HSIO Single-Ended SSTL, HSTL, HSUL, POD, and LVSTL I/O Reference Voltage Specifications For specification status, see the Data Sheet Status table | I/O Standard | V CCIO_PI...

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## Table 37. HSIO Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications For specification status, see the Data Sheet Status table | I/O Standard | V IL(DC) (V) | V IH(DC) (V...

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## Note: For output voltage swing calculation example, refer to the General-Purpose I/O User Guide for this device. Differential voltage referenced I/O standard uses two single-ended outputs with sec...

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## Note: For eye height position estimation in EMIF interfaces, refer to the PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex ™ 5 FPGAs and SoCs . The eye mask est...

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## Related Information - General-Purpose I/O User Guide: Agilex ™ 5 FPGAs and SoCs - PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex ™ 5 FPGAs and SoCs Provid...

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## Table 38. HSIO Single-Ended LVSTL I/O Standards Specifications For specification status, see the Data Sheet Status table | I/O Standard | V CCIO_PIO (V) | V CCIO_PIO (V) | V CCIO_PIO (V) ...

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## Related Information PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex ™ 5 FPGAs and SoCs (74) Each sub-bank can only support a single voltage tolerance. The VCC...

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## Table 39. HSIO Differential SSTL, HSTL, and HSUL I/O Standards Specifications For specification status, see the Data Sheet Status table | I/O Standard | V CCIO_PIO (V) | V CCIO_PIO (V) | V ...

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## Table 41. HSIO Differential LVSTL I/O Standards Specifications PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex ™ 5 FPGAs and SoCs Provides eye mask estimation ...

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## Table 42. HSIO Differential I/O Standards Specifications PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex ™ 5 FPGAs and SoCs For specification status, see the...

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## Related Information - General-Purpose I/O User Guide: Agilex ™ 5 FPGAs and SoCs - LVDS SERDES User Guide: Agilex ™ 5 FPGAs and SoCs - AN 555: True Differential Signaling Termination and Biasing ...

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## Table 43. D-Series FPGAs MIPI D-PHY Low-Power I/O Standards Specifications For specification status, see the Data Sheet Status table | I/O Standard | Note ...

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## Table 44. D-Series FPGAs MIPI D-PHY High-Speed I/O Standards Specifications For specification status, see the Data Sheet Status table | I/O Standa rd | Conditi on | V CCIO...

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## Table 45. E-Series FPGAs MIPI D-PHY Low-Power I/O Standards Specifications For specification status, see the Data Sheet Status table | I/O Standar | Device Group | Note | V CCI...

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## Table 45. E-Series FPGAs MIPI D-PHY Low-Power I/O Standards Specifications | I/O Standar d | Device Group | Note | V CCIO_PIO...

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## Table 46. E-Series FPGAs MIPI D-PHY High-Speed I/O Standards Specifications For specification status, see the Data Sheet Status table | I/O Standa rd | Condition | Condition ...

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## Table 47. HVIO Single-Ended I/O Standards Specifications Recommended Operating Conditions on page 22 For specification status, see the Data Sheet Status table | I/O Standard | V...

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## HPS I/O Standard Specifications Tables in this section list the supported input voltage (VIH and VIL), output voltage (VOH and VOL), and current drive characteristics (IOH and IOL) for various I/O...

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## SDM I/O Standard Specifications Tables in this section list the supported input voltage (VIH and VIL), output voltage (VOH and VOL), and current drive characteristics (IOH and IOL) for various I/O...

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## Table 50. D-Series FPGAs Clock Tree Performance Specifications This section provides the performance characteristics of core and periphery blocks. For specification status, see the Data Sheet St...

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## Table 51. E-Series FPGAs Clock Tree Performance Specifications For specification status, see the Data Sheet Status table | Parameter | Performance | Performance | Performance...

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## Table 52. D-Series FPGAs I/O PLL Specifications For specification status, see the Data Sheet Status table | Symbol | Parameter ...

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## Table 52. D-Series FPGAs I/O PLL Specifications | Symbol | Parameter | Condition ...

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## Table 52. D-Series FPGAs I/O PLL Specifications | Symbol | Parameter | Condition | Minim...

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## Table 53. E-Series FPGAs I/O PLL Specifications For specification status, see the Data Sheet Status table | Symbol | Parameter ...

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## Table 53. E-Series FPGAs I/O PLL Specifications | Symbol | Parameter | Condition ...

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## Table 53. E-Series FPGAs I/O PLL Specifications | Symbol | Parameter | Condition ...

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## Related Information Memory Output Clock Jitter Specifications on page 93 Provides more information about the external memory interface clock output jitter specifications. (107) External memory i...

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## Table 54. D-Series FPGAs DSP Block Performance Specifications for Single DSP Block For specification status, see the Data Sheet Status table | Mode ...

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## Table 55. D-Series FPGAs DSP Block Performance Specifications for Multiple DSP Blocks For specification status, see the Data Sheet Status table | Mode |...

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## Table 56. E-Series FPGAs DSP Block Performance Specifications for Single DSP Block For specification status, see the Data Sheet Status table | Mode ...

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## Table 57. E-Series FPGAs DSP Block Performance Specifications for Multiple DSP Blocks For specification status, see the Data Sheet Status table | Mode |...

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## Memory Block Specifications To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on-chip PLL and set to 50% output duty cycle. ...

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## Table 58. D-Series FPGAs Memory Block Performance Specifications For specification status, see the Data Sheet Status table | Memory | Mode ...

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## Table 59. E-Series FPGAs Memory Block Performance Specifications For specification status, see the Data Sheet Status table | Memory | Mode ...

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## Remote Temperature Diode Specifications Recommended Operating Conditions on page 22 Note the following for the remote temperature diode specifications: - The temperature diode characteristics i...

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## Table 61. Remote Temperature Diode Specifications (Core Fabric TSD) For specification status, see the Data Sheet Status table | Description | Min | Typ | Max | Unit ...

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## Table 62. Voltage Sensor Specifications For specification status, see the Data Sheet Status table | Parameter | Minimum | Typical | M...

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## Periphery Performance Specifications This section describes the periphery performance, LVDS SERDES, and external memory interface. Actual achievable frequency depends on design and system specifi...

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## Table 63. D-Series and E-Series Device Group A FPGAs LVDS SERDES Specifications LVDS serializer/deserializer (SERDES) block supports SERDES factor J = 4 and 8. DDR registers support SERDES factor...

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## Table 63. D-Series and E-Series Device Group A FPGAs LVDS SERDES Specifications | Parameter | Symbol | Condition ...

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## Table 63. D-Series and E-Series Device Group A FPGAs LVDS SERDES Specifications | continued... ...

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## Table 63. D-Series and E-Series Device Group A FPGAs LVDS SERDES Specifications | Parameter | Symbol | Condition ...

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## Table 63. D-Series and E-Series Device Group A FPGAs LVDS SERDES Specifications | Parameter | Symbol | Condition | -1 Speed ...

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## Table 64. E-Series Device Group B FPGAs LVDS SERDES Specifications LVDS serializer/deserializer (SERDES) block supports SERDES factor J = 4 and 8. DDR registers support SERDES factor J = 1 and 2....

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## Table 64. E-Series Device Group B FPGAs LVDS SERDES Specifications | Parameter | Symbol | Condition |...

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## Table 64. E-Series Device Group B FPGAs LVDS SERDES Specifications | Parameter | Symbol | Condition ...

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## Table 64. E-Series Device Group B FPGAs LVDS SERDES Specifications | continued... | ...

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## Table 64. E-Series Device Group B FPGAs LVDS SERDES Specifications | Parameter | Symbol | Condition |...

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## Table 65. DPA Lock Time Specifications The DPA lock time is for one channel. One data transition is defined as a 0-to-1 or 1-to-0 transition. For specification status, see the Data Sheet Status t...

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## LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications Figure 2. LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications for a Data Rate Equal to 1.6 Gbps Table 66. LVDS SERDES...

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## Table 67. D-Series FPGAs Memory Standards Supported This table lists the overall capability of External Memory Interface supported by D-Series FPGAs. For specific details, refer to the External Me...

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## Table 68. E-Series Device Group A FPGAs Memory Standards Supported This table lists the overall capability of External Memory Interface supported by E-Series Device Group A. For specific details, ...

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## Table 69. E-Series Device Group B FPGAs Memory Standards Supported This table lists the overall capability of External Memory Interface supported by E-Series Device Group B. For specific details, ...

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## Memory Output Clock Jitter Specifications External Memory Interface (EMIF) Spec Estimator The clock jitter specification applies to the memory output clock pins clocked by an I/O PLL, or generat...

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## Table 70. D-Series FPGAs MIPI D-PHY Performance For specification status, see the Data Sheet Status table | Parameter | Symbol | Condition ...

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## Table 71. E-Series FPGAs MIPI D-PHY Performance For specification status, see the Data Sheet Status table | Paramete r | Device Group | Symbol | Con...

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## Table 72. Transmitter and Receiver Data Rate Performance For specification status, see the Data Sheet Status table | Symbol/Description | Transceiver Speed | ...

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## Table 73. GTS Transceiver and System PLL Reference Clock Input Specifications For specification status, see the Data Sheet Status table | Symbol | Description ...

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## Table 74. System PLL Reference Clock (Using HVIO) Specifications For specifications on the I/O PLL using HVIO pin, refer to D-Series FPGAs I/O PLL Specifications or E-Series FPGAs I/O PLL Specific...

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## Table 75. GTS Transceiver Reference Clock Output Driver Specifications For specification status, see the Data Sheet Status table | Symbol | Description ...

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## Table 76. Transmitter Electrical Specifications For specification status, see the Data Sheet Status table | Parameter | Symbol | Description ...

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## Table 77. Receiver Electrical Specifications For specification status, see the Data Sheet Status table | Parameter | Symbol | Description ...

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## Table 77. Receiver Electrical Specifications | Parameter | Symbol | Description | Condition ...

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## Table 78. Electrical Compliance List For specification status, see the Data Sheet Status table | Specification/Clause | Protocol | Lane Rate (Gbps) | Lane Rate ...

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## Table 78. Electrical Compliance List | Specification/Clause | Protocol | Lane Rate (Gbps) | Lane Rate (Gbps) | |--------------------------|------------------...

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## Table 79. D-Series SoC Maximum HPS Clock Frequencies This section provides hard processor system (HPS) specifications and timing. For specification status, see the Data Sheet Status table | Per...

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## Table 80. E-Series SoC Maximum HPS Clock Frequencies For specification status, see the Data Sheet Status table | Performance | V CCL_HPS (V) (155) | Cortex-A55 Core Frequency (MHz) | Corte...

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## Table 81. HPS Internal Oscillator Frequency - HPS Power Supply Operating Conditions on page 34 - Memory Standards Supported on page 91 For specification status, see the Data Sheet Status table ...

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## Table 82. HPS PLL Input Requirements The main HPS PLL receives its clock signals from the HPS\_OSC\_CLK pin. Refer to the Pin Connection Guidelines of this device for information about assigning t...

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## Table 83. HPS PLL Performance For specification status, see the Data Sheet Status table | Description | Min | Max | Unit | |---------------------------|-------|---------...

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## Table 84. HPS Cold Reset For specification status, see the Data Sheet Status table | Symbol | Description | Min | Max | Unit | |----------|------------...

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## Table 85. SPI Master Timing Requirements You can adjust the input delay timing by programming the rx\_sample\_dly register. For specification status, see the Data Sheet Status table | Symbol ...

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## Table 86. SPI Slave Timing Requirements For specification status, see the Data Sheet Status table | Symbol | Description | Min ...

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## Table 87. HPS Secure Digital (SD)/Embedded MultiMediaCard (eMMC) Timing Requirements Supports SD devices up to V6.1. Supports SDIO devices up to V4.1. Supports SD/eMMC devices up to V5.1. These t...

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## Table 88. SD Input Timing (SDR104, SDR50, SDR25, SDR12) For specification status, see the Data Sheet Status table | Symbol | Description | Min | Typ | Ma...

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## Table 89. SD Output Timing (SDR50, SDR25, SDR12) For specification status, see the Data Sheet Status table | Symbol | Description | Min | Typ | Ma...

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## Table 90. SD Output Timing (SDR104) For specification status, see the Data Sheet Status table | Symbol | Description ...

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## Table 91. SD Timing (DDR50) For specification status, see the Data Sheet Status table | Symbol | Description | Min | Typ | Max | Unit | |------...

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## Table 92. eMMC Timing (Legacy, HS\_SDR) For specification status, see the Data Sheet Status table | Symbol | Description | Min | Typ | Max | Unit | |----------|-...

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## Table 93. eMMC Timing (HS\_DDR) For specification status, see the Data Sheet Status table | Symbol | Description | Min | Typ | Max | Unit | |-----...

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## Table 94. eMMC Timing (HS200) For specification status, see the Data Sheet Status table | Symbol | Description | Min | Typ | Max | Unit | |-...

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## Table 95. eMMC Timing (HS400) For specification status, see the Data Sheet Status table | Symbol | Description | ...

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## Table 96. HPS USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) Low Pin Interface (ULPI) Timing Requirements For specification status, see the Data Sheet Status table | Symbol | Description...

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## Note: If you need to adjust the timings of certain signals, you can use the HPS registers Pin\_Mux.io0\_delay through Pin\_Mux.io47\_delay to allow software to set the delay chains in each of the ...

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## Table 97. HPS USB 3.1 Transceiver Macrocell Interface Plus (UTMI+) Low Pin Interface (ULPI) Timing Requirements For specification status, see the Data Sheet Status table | Symbol | Description...

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## Table 98. Reduced Gigabit Media Independent Interface (RGMII) TX Timing Requirements For specification status, see the Data Sheet Status table | Symbol | Description ...

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## SGMII Timing Requirements SGMII operating mode is supported through FPGA fabric using SGMII PCS soft IP and LVDS SERDES FPGA IP. Refer to the LVDS SERDES Specifications section for timing specific...

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## Table 101. HPS I 2 C Timing Requirements - LVDS SERDES Specifications on page 80 - GTS Transceiver Performance Specifications on page 96 For specification status, see the Data Sheet Status table...

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## Table 102. HPS I 3 C Timing Requirements When Communicating With I 2 C Legacy Devices For specification status, see the Data Sheet Status table | Symbol | Description ...

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## Table 103. HPS I 3 C Open Drain Timing Requirements For specification status, see the Data Sheet Status table | Symbol | Description | Min ...

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## Table 104. HPS I 3 C Push-Pull Timing Requirements for SDR Mode For specification status, see the Data Sheet Status table | Symbol | Description | Min ...

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## Table 105. HPS NAND SDR Timing Requirements HPS Power Supply Operating Conditions on page 34 Compatible with the ONFI 1.x and 2.x specifications. Compatible with the Toggle 1.x and 2.x specifica...

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## Table 106. HPS NAND DDR Timing Requirements Compatible with the ONFI 1.x and 2.x specifications. Compatible with the Toggle 1.x and 2.x specifications. HPS I/O supports SDR, NV-DDR protocols up to...

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## Table 106. HPS NAND DDR Timing Requirements | Symbol | Description ...

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## Table 106. HPS NAND DDR Timing Requirements | Symbol | Description | 100 MHz (200 MT/s) | 100 MHz (200 MT...

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## Table 106. HPS NAND DDR Timing Requirements | Symbol | Description | 100 MHz (200 MT/s) | 100 MHz (2...

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## Table 107. Trace Timing Requirements To increase the trace bandwidth, Altera recommends routing the trace interface to the FPGA in the HPS Platform Designer component. The FPGA trace interface off...

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## HPS GPIO Interface The general-purpose I/O (GPIO) interface has debounce circuitry included to remove signal glitches. The debounce clock frequency ranges from 125 Hz to 32 kHz. The minimum pulse ...

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## Table 108. HPS JTAG Timing Requirements For specification status, see the Data Sheet Status table | Symbol | Description | Min | Typ | Max | Unit | |---...

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## Table 109. HPS Programmable I/O Delay (Output Path) For specification status, see the Data Sheet Status table | Name | output_val_en | output_val | Description ...

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## Table 110. HPS Programmable I/O Delay (Input Path) For specification status, see the Data Sheet Status table | Name | input_val_en | input_val | Description ...

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## Table 111. General Configuration Timing Specifications For specification status, see the Data Sheet Status table | Symbol | Description ...

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## POR Specifications Power-on reset (POR) delay is defined as the delay between the last power rail monitored by the POR circuitry from Group 2B to reach the minimum operating condition voltage to t...

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## Table 113. External Configuration Clock Source (OSC\_CLK\_1) Clock Input Requirements For specification status, see the Data Sheet Status table | Description ...

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## Table 115. AS Timing Parameters Altera recommends performing trace length matching for nCSO and AS\_DATA pins to AS\_CLK to minimize the skew. For specification status, see the Data Sheet Status ...

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## Table 116. Avalon Streaming Timing Parameters for ×8 and ×16 Configurations For specification status, see the Data Sheet Status table | Symbol | Description ...

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## Table 117. Configuration Bit Stream Sizes Configuration bit stream sizes shown in this table are based on worst-case scenarios. The sizes are typically substantially smaller because of the use of ...

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## I/O Timing I/O timing data is typically used prior to designing the FPGA to get an estimate of the timing budget as part of the timing analysis. You may generate the I/O timing report manually usi...

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## Table 118. Programmable IOE Delay Specifications For specification status, see the Data Sheet Status table | Parameter | Maximum Offset | Minimum ...

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## Glossary Table 119. Glossary | Term | Definition ...

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## Glossary | | continued... ...

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## Glossary | Term | Definition | |----...

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## Document Revision History for the Agilex 5 FPGAs and SoCs Device Data Sheet | Document Version | Changes ...

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## Document Revision History for the Agilex 5 FPGAs and SoCs Device Data Sheet | Document Version | Changes ...

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## Document Revision History for the Agilex 5 FPGAs and SoCs Device Data Sheet ------------------------------------------------------------------------------------------------------------------------...

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## Document Revision History for the Agilex 5 FPGAs and SoCs Device Data Sheet • Added description to the System PLL Reference Clock (Using HVIO) Specifications table. • Added Input clock or extern...

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## Document Revision History for the Agilex 5 FPGAs and SoCs Device Data Sheet ...

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## Document Revision History for the Agilex 5 FPGAs and SoCs Device Data Sheet | Document Version | Changes ...

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## Document Revision History for the Agilex 5 FPGAs and SoCs Device Data Sheet • Added USB_CLK clock frequency in the following tables: ○ HPS USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) Low ...

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## Document Revision History for the Agilex 5 FPGAs and SoCs Device Data Sheet ...

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## Document Revision History for the Agilex 5 FPGAs and SoCs Device Data Sheet | Document Version | Changes ...

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## Document Revision History for the Agilex 5 FPGAs and SoCs Device Data Sheet • Updated the specifications in D-Series FPGAs MIPI D-PHY Low-Power I/O Standards Specifications and E-Series FPGAs MIPI...

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## Document Revision History for the Agilex 5 FPGAs and SoCs Device Data Sheet | Document Version | Changes ...

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## Document Revision History for the Agilex 5 FPGAs and SoCs Device Data Sheet --------------------------------------------------------------------------------------------| | | • U...

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## Document Revision History for the Agilex 5 FPGAs and SoCs Device Data Sheet ...

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## Document Revision History for the Agilex 5 FPGAs and SoCs Device Data Sheet | Document Version | Changes ...

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## Document Revision History for the Agilex 5 FPGAs and SoCs Device Data Sheet • Updated the E-Series FPGAs DSP Block Performance Specifications for Multiple DSP Blocks table. ○ Updated -6L to -6X ...

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## Document Revision History for the Agilex 5 FPGAs and SoCs Device Data Sheet | Document Version | Changes ...