Sources / AN 307: Altera FPGA Design Flow for Xilinx Users / AN 307: Altera ® FPGA Design Flow for AMD* Xilinx* Users

AN 307: Altera ® FPGA Design Flow for AMD* Xilinx* Users

Content

AN 307: Altera ® FPGA Design Flow for AMD* Xilinx* Users

Updated for Quartus ® Prime Design Suite: 24.1

| 1. Introduction to Altera FPGA Design Flow for AMD* Xilinx* Users................................. |--------------------------------------------------------------------------------------------------------------- | 2. Technology Comparison..................................................................................................5 | 2.1. Altera FPGA and SoC Devices.................................................................................. | 2.2. Altera-AMD Xilinx Device Comparison.......................................................................6 | 2.3. Altera FPGA Device Features................................................................................... | 3. FPGA Tools Comparison................................................................................................ | 3.1. Hardware and Software Tools for FPGA Design.........................................................10 | 3.2. FPGA Design Flow Using Command Line Scripting.....................................................11 | 3.2.1. Command-Line Executable Equivalents....................................................... | 3.2.2. Programming and Configuration File Support in the Quartus Prime Pro Edition Software................... | 3.3. FPGA Design Flow Using Tools with GUIs.................................................................18 | 3.3.1. Project Creation.......................................................................................20 | 3.3.2. Design Entry........................................................................................... | 3.3.3. IP Status................................................................................................ | 3.3.4. Design Constraints...................................................................................25 | 3.3.5. Synthesis................................................................................................27 | 3.3.6. Design Implementation.............................................................................28 | 3.3.7. Finalize Pinout.........................................................................................29 | 3.3.8. Viewing and Editing Design Placement........................................................ | 3.3.9. Static Timing Analysis...............................................................................32 | 3.3.10. Generation of Device Programming Files....................................................33 | 3.3.11. Power Analysis.......................................................................................34 | 3.3.12. Simulation.............................................................................................34 | 3.3.13. Hardware Verification..............................................................................36 | 3.3.14. View Netlist...........................................................................................42 | 3.3.15. Design Optimization............................................................................... | 3.3.16. Techniques to Improve Productivity.......................................................... | 3.3.17. Partial Reconfiguration............................................................................47 | 3.3.18. Cross-Probing in the Quartus Prime Pro Edition Software............................. | 3.4. Additional Quartus Prime Pro Edition Features..........................................................48 | 3.4.1. Scripting with Tcl in the Quartus Prime Pro Edition Software...........................49 | 4. AMD Xilinx to Altera FPGA Design Conversion...............................................................52 | 4.1. Replacing AMD Xilinx Primitives............................................................................. | 4.1.1. Converting I/O Buffers..............................................................................53 | 4.1.2. Changing Default I/O Standard for | 4.1.3. Converting Registers................................................................................ | 4.2. Converting IP Cores............................................................................................. | 4.2.1. Converting Memory Blocks........................................................................ | 4.2.2. Converting Mixed-Mode Clock Manager (MMCM) to Phase-Locked Loop | 4.2.3. Converting Multipliers...............................................................................75 | 4.3. Setting Equivalent AMD Xilinx Design Constraints.....................................................79 | 4.3.1. Device Constraints................................................................................... | 4.3.2. Placement Constraints..............................................................................83 | 4.3.3. Timing Constraints...................................................................................86 | 4 | --------------------------------------------------------------------|---------------------------------------------------------------| | | | 5 | | | | 7 | | 10 | | | | | | 13 | ................................................................... | 18 | | | | | | 21 | | 24 | | | | | | | | | | 31 | | | | | | | | | | | | | | 44 | | 45 | | | | 48 | | | | | | | | 52 | | | | Pins.......................................................56 | | 56 | | 56 | | 56 | | (PLL)... 71 | | | | | | 79 | | | | |

| 4.3.4. Retimer Constraints..................................................................................87 | |-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | 4.4. Setting Up the Simulation Environment...................................................................87 | | 4.4.1. Simulation Levels.....................................................................................88 | | 4.4.2. HDL Support for EDA Simulators................................................................88 | | 4.4.3. Value Change Dump (VCD) Support............................................................89 | | 4.4.4. Simulating Altera FPGA IP Cores................................................................ 89 | | 5. Conclusion.................................................................................................................... 90 | | 6. AN 307: Altera FPGA Design Flow for AMD Xilinx Users Archives.................................. 91 7. Document Revision History for Altera FPGA Design Flow for AMD Xilinx Users............. 92 |

1. Introduction to Altera ® FPGA Design Flow for AMD* Xilinx* Users

Designing for Altera ® FPGA devices is similar in concept and practice to designing for AMD* Xilinx* FPGA devices. In most cases, you can import your register transfer level (RTL) into the Quartus ® Prime Pro Edition software and begin compiling your design to the target device.

This document is intended for AMD Xilinx designers who are familiar with the AMD Xilinx Vivado* software and want to convert existing Vivado designs to the Quartus Prime Pro Edition software environment.

This application note starts with a description of the current AMD Xilinx and Altera FPGA technologies and compares devices available for three different process technologies. It further highlights unique features of Agilex ™ 3, Agilex 7, Stratix ® 10, Arria ® 10, and Cyclone ® 10 GX devices supported in the latest edition of the Quartus Prime Pro Edition software.

The next chapter draws a parallel between the design flows in the Quartus Prime Pro Edition software and AMD Xilinx Vivado software, comparing features whenever possible.

The following chapter provides guidelines to convert Vivado designs to the Quartus Prime Pro Edition software, including AMD Xilinx IP Catalog modules and instantiated primitives. The last part of the chapter demonstrates how to translate device and design constraints.

This application note uses the latest information available for the Quartus Prime Pro Edition software version 21.3 and AMD Xilinx Vivado Design Suite version 2020.2, supporting the latest programmable chips.

© Altera Corporation. Altera, the Altera logo, the 'a' logo, and other Altera marks are trademarks of Altera Corporation. Altera reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

*Other names and brands may be claimed as the property of others.

2. Technology Comparison

2.1. Altera FPGA and SoC Devices

Altera FPGA devices are ideal for a wide variety of applications, from prototyping state-of-the-art new products all the way through to high-volume production. Altera has several FPGA families that cover high-end, mid-range, and low-cost markets. Each family includes different features such as embedded memory, digital signal processing (DSP) blocks, high-speed transceivers, and general purpose I/O pins. These features help cover a broad range of application requirements.

Altera SoC devices bring high-integration and advanced system, power, and security management capabilities to the Altera product portfolio. These devices are supported by industry-standard Arm* tools, along with a broad ecosystem of operating systems and development tools.

Altera FPGA and SoC devices are available in the following device families:

Cyclone 10 GX FPGA devices are built to meet your low-power, cost-sensitive, design needs in a broad range of markets such as industrial, broadcast and telecommunications.
Agilex 5 FPGA devices extend the innovations of Agilex devices to midrange FPGA applications. Agilex 5 devices serve a broad range of applications that require high performance, lower power, smaller form factors and lower logic densities.
Agilex 7 FPGA and SoC devices deliver on average 50% higher core performance, or up to 40% lower power over previous generation high-end, high-performance FPGAs. Fabricated using the Altera 10 nm SuperFin technology, these FPGAs and SoCs accelerate your delivery of the most advanced bandwidth-intensive applications.
Arria 10 FPGA and SoC devices are ideal for your high-performance, powersensitive midrange applications in diverse markets. The power efficiency of these devices is achieved through a comprehensive set of power-saving technologies.
Stratix 10 FPGA and SoC devices feature several groundbreaking innovations, including the Altera Hyperflex ™ core architecture. This device family enables you to meet the demand for ever-increasing transceiver and processing performance in your most advanced applications, while meeting your power budget.

Table 1. Altera FPGA Family Technologies and Architectures

| Altera FPGA Family | Technology | Architecture | |--------------------------------|----------------|----------------| | Agilex 5 E-Series and D-Series | Altera 7 | Fabric | | Agilex 7 F-Series and I-Series | 10 nm SuperFin | Fabric + Tiles | | Agilex 7 M-Series | Altera 7 | Fabric + Tiles | | continued... | continued... | continued... |

| Altera FPGA Family | Technology | Architecture | |----------------------|--------------|----------------| | Arria 10 | 20 nm Planar | Monolithic | | Cyclone 10 GX | 20 nm Planar | Monolithic | | Stratix 10 | 14 nm FinFet | Fabric + Tiles |

The latest Agilex 7 and Stratix 10 FPGA and SoC devices are built using heterogeneous 3D system-in-package (SiP) technology. This technology enables in-package integration of a range of component tiles such as transceivers, memory, and analog, while maintaining a monolithic FPGA fabric. Various tile die from different process nodes can be integrated in the same package, the tiles being connected to the FPGA fabric die using the Altera Embedded Multi-die Interconnect Bridge (EMIB) packaging technology.

For more information about the Altera SiP technology, refer to the Enabling NextGeneration Platforms Using Altera's 3D System-in-Package Technology white paper.

To understand the advantages of a monolithic FPGA fabric compared to alternative silicon interposer-based schemes used in competitive FPGA and SoC devices, refer to the Achieving the Highest Levels of Integration in Programmable Logic white paper.

Related Information

Enabling Next-Generation Platforms Using Altera's 3D System-in-Package Technology

White Paper

Achieving the Highest Levels of Integration in Programmable Logic White Paper

2.2. Altera-AMD Xilinx Device Comparison

The following table lists comparable devices from both Altera and Xilinx and can be used as a starting point when converting from AMD Xilinx devices to Altera devices.

Table 2. Device Family Comparison

| Application | Xilinx Devices | Altera Devices | |---------------------|------------------------------------------------------------------|-------------------------------------------------------------------------------------------------------------------------| | Highest performance | • Versal* HBM • Versal Prime • Versal Premium | • Agilex 7 F-Series • Agilex 7 I-Series • Agilex 7 M-Series | | High performance | • Virtex* UltraScale+* • Kintex* UltraScale+ • Zynq* UltraScale+ | • Agilex 7 F-Series • Agilex 7 I-Series • Stratix 10 GX • Stratix 10 SX • Stratix 10 TX • Stratix 10 MX • Stratix 10 DX | | Mid-range | • Virtex UltraScale* • Kintex UltraScale • Zynq-7000 | • Agilex 5 D-Series • Agilex 5 E-Series • Arria 10 GX • Arria 10 SX | | continued... | continued... | continued... |

2. Technology Comparison

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| Application | Xilinx Devices | Altera Devices | |---------------|---------------------------------------------------------------------------------|------------------| | | • Zynq UltraScale+ (lower densities) • Artix* UltraScale+ • Spartan UltraScale+ | | | Low cost | • Artix-7 | • Cyclone 10 GX |

Related Information

Altera Product Performance: FPGA - Performance Index

2.3. Altera FPGA Device Features

Agilex 7 Device Features

Table 3. Agilex 7 Device Features

| Performance (1) | Built on Altera 10nm SuperFin technology with second generation Hyperflex ® architecture with enhanced fabric resources, high-speed routing, and improved clocking infrastructure, Agilex 7 devices average 50% higher performance compared to the previous generation Stratix 10 FPGA and SoC devices. | |---------------------------|----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | Power (1) | With metal stack optimizations specific for FPGAs, a lower minimum voltage, and extensive transistor-level tuning, Agilex delivers up to 40% lower power compared to Stratix 10 devices. | | Transceivers | The Agilex 7 FPGA and SoC family delivers accelerated transceiver innovation with data rates up to 116Gbps and support for PCI Express* up to Gen 5. Agilex 7 FPGA and SoC devices come with a comprehensive portfolio of transceiver tiles. | | Floating-point operations | The Agilex 7 FPGA and SoC family offers a configurable DSP engine which features hardened support for both floating-point and fixed-point operations such as single-precision FP32, half-precision FP16, BFLOAT16, and INT8 calculations. This programmability, coupled with the innovations in the DSP blocks is ideal for evolving AI workloads. | | Processor | Highly efficient quad-core Arm Cortex*-A53 processor cluster optimized for ultra-high performance per watt. | | Applications | Agilex 7 FPGAs and SoCs enable next-generation, high-performance applications in the data center, networking, and the edge. |

Stratix 10 Device Features

Table 4. Stratix 10 Device Features

| Performance | Built on the Altera 14 nm Tri-Gate process, Stratix 10 devices deliver 2X core performance gains over previous-generation, high-performance FPGAs. (2) | |---------------------------|-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | Power | Reduced IP size, enabled by the Hyperflex FPGA Architecture allows the consolidation of designs that span multiple devices into a single device, reducing power by up to 70% versus previous-generation high-performance FPGAs. (2) | | Transceivers | Stratix 10 FPGA and SoC devices take advantage of heterogeneous 3D system-in-package (SiP) technology to integrate a monolithic FPGA core fabric with 3D SiP transceiver tiles and other advanced components in a single package. | | Floating-point operations | The hardened floating-point operators within each DSP block, initially introduced in the Arria 10 device family, are extended to deliver an order of magnitude greater throughput in Stratix 10 FPGA and SoC devices. | | continued... | continued... |

| | Digital signal processing (DSP) designs can achieve up to 10 tera floating point operations per second (TFLOPS) of IEEE 754 single-precision floating-point operations. | |--------------|----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | Processor | Next-generation hard processor system (HPS), quad-core Arm Cortex-A53 processor cluster that results in high-perfomance and power-efficient SoC devices. (2) | | Applications | Address challenges in high-performance systems in the most demanding applications including communications, data center acceleration, high-performance computing, radar processing, ASIC prototyping, and many more. |

Arria 10 Device Features

Table 5. Arria 10 Device Features

| Performance | A speed grade faster core performance and up to a 20% fMAX advantage compared to the competition, using publicly-available Altera FPGA IP Evaluation Mode designs. | |-----------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | Power | Arria 10 FPGAs and SoCs are up to 40 percent lower power than previous generation FPGAs and SoCs | | Industry's only | • Hard floating-point digital signal processing (DSP) blocks with speeds up to 1.5 tera floating-point operations per second (TFLOPS) (3) • 20 nm ARM-based SoC | | Applications | FPGAs and SoCs deliver the integration needed to address a wide range of applications for many industries, including communications, defense, broadcast, high-performance computing, test, and medical |

Cyclone 10 GX Device Features

Table 6. Cyclone 10 GX Device Features

| Industry's first | Low-cost FPGA with IEEE 754-compliant hard floating-point DSP blocks | |--------------------|--------------------------------------------------------------------------------------------------------------------------| | Applications | Optimized for high-bandwidth, performance applications such as Industrial Vision, Robotics, and Automotive Infotainment. |

(2) Comparison based on Stratix V vs. Stratix 10 using Quartus Prime Pro Edition 16.1 Early Beta. Stratix V Designs were optimized using 3 step optimization process of Hyper-Retiming, HyperPipelining, and Hyper-Optimization in order to utilize Stratix 10 architecture enhancements of distributed registers in core fabric. Designs were analyzed using Quartus Prime Pro Fast Forward Compile performance exploration tool. For more details, refer to HyperFlex FPGA Architecture Overview White Paper: https://www.intel.com/content/dam/www/ programmable/us/en/pdfs/literature/wp/wp-01220-hyperflex-architecture-fpga-socs.pdf. Actual performance users achieve varies based on level of design optimization applied. Tests measure performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration affect actual performance. Consult other sources of information to evaluate performance as you consider a purchase. For more complete information about performance and benchmark results, visit https://intel.com/ performanceindex.
(3) Tests measure performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase. For more complete information about performance and benchmark results, visit https://intel.com/ performanceindex. Performance comparison methodology and detailed results documented in the Arria 10 Performance Benchmarking Methodology and Results white paper available at the The Altera FPGAs and Programmable Devices Arria 10 Performance page .

2. Technology Comparison

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Related Information

Altera FPGA Products Overview
Altera SoC Products Overview
Arria 10 Performance Benchmarking Methodology and Results

3. FPGA Tools Comparison

The Quartus Prime design software delivers the highest performance, optimum logic utilization, and fastest compile times for high-end FPGA designs. New algorithms and technologies enable the Quartus Prime Pro Edition software to scale the range of densities and features that next-generation FPGAs offer.

The Quartus Prime Pro Edition software allows you to implement a FPGA design either by using command-line executables and scripting, or by using the Quartus Prime GUI.

3.1. Hardware and Software Tools for FPGA Design

The Quartus Prime Pro Edition software provides tools similar to those found in the AMD Xilinx Vivado software. The following table shows AMD Xilinx tool suites and the Altera FPGA tool targeting similar design needs:

Table 7. Hardware and Software Tools Available

| AMD Xilinx | Altera | Description | |------------------------------------------------------------------------------------|------------------------------------------------------------------------------------------------------------------|-----------------------------------------------------------------------------------------------------------------------------| | Vivado HL Design Edition • Versal • UltraScale • UltraScale+ • 7 Series | Quartus Prime Pro Edition • Agilex 7, Stratix 10, Arria 10, Cyclone 10 GX | Optimized to support the advanced features in next generation FPGAs and SoCs. | | ISE* Design Suite for: • Spartan-6 • Virtex-6 • CoolRunner* • Previous generations | Quartus Prime Standard Edition for: • Stratix IV, V • Arria series • Cyclone IV, V, Cyclone 10 LP • MAX ® series | Supports older generation device families. Note: Altera recommends using newer version of Quartus Prime for new designs. | | Vitis* | Altera oneAPI Base toolkit Altera FPGA Add-on for oneAPI Base Toolkit | High-level platform application development software. | | Vivado HL WebPACK Edition | Quartus Prime Lite Edition | • Do not require license • Provide limited device and feature support | | SDAccel Environment • Selected UltraScale and 7 Series devices. | Intel ® FPGA SDK for OpenCL ™ • Agilex 7,Stratix 10, Arria 10, Cyclone V SoC | Development environment for OpenCL | | SDSoC Environment | Altera SoC FPGA Embedded Development Suite | Comprehensive tool suite for embedded software development on SoCs. You can code, build, debug, and optimize in single IDE. | | continued... | continued... | continued... |

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| AMD Xilinx | Altera | Description | |------------------------------|----------------------------------------------------------------------------------|------------------------------------------------------------------------------------------------------------------------------| | Software Development Kit | Nios ® II Embedded Design Suite (EDS) | Comprehensive development package to develop and debug code for SoCs | | System Generator (4) for DSP | DSP Builder for Intel FPGAs (5)(6) | DSP Design Tool | | Vivado High-Level Synthesis | Altera HLS Compiler Agilex 7, Stratix 10, Arria 10, Cyclone 10 GX, Cyclone V SoC | High-Level synthesis tool that takes in untimed software code as input and generates register-transfer level code for FPGAs. |

Related Information

Altera FPGA Development Tools
AMD Xilinx Vivado Design Suite

3.2. FPGA Design Flow Using Command Line Scripting

Automating the FPGA design process saves time and increases productivity. The Vivado software and the Quartus Prime Pro Edition software provide the tools necessary to automate your FPGA design flow.

The compilation flow is the sequence and methods by which the software translates design files, maps the translated design to device-specific elements, places and routes the design in the device, and generates programming files. The Quartus Prime Pro Edition software performs these functions through stages such as Analysis and Synthesis, Fitter, Assembler, and Timing Analyzer. If you are familiar with the command-line flow in the Vivado software, you can detect parallels with the Quartus Prime Pro Edition software.

The following figure shows the typical stages of the compilation flow and the corresponding AMD Xilinx Vivado and Altera FPGA Quartus Prime Pro Edition command line instructions for each stage.

(4) To use System Generator for DSP in Vivado, you must buy the Vivado HL System Edition, which supports all features of the Vivado HL Design Edition plus System Generator for DSP.

(5) The Quartus Prime Pro Edition software includes the DSP Builder for Altera FPGAs.

(6) Available for Arria 10, Stratix V, Arria V, and Cyclone V devices.

The Hyper-Aware Design Flow

The Hyper-Aware Design Flow allows you to take full advantage of the Hyperflex architecture provided on Agilex 7 and Stratix 10 devices. This flow combines automated register retiming (Hyper-Retiming), with implementation of target timing closure recommendations (Fast Forward compilation), to maximize use of HyperRegisters and drive the highest performance for your Agilex 7 and Stratix 10 designs:

Hyper-Retiming:

A key innovation of the Hyperflex architecture is the addition of multiple HyperRegisters in every routing segment and block input. Maximizing the use of HyperRegisters improves design performance. The prevalence of Hyper-Registers improves balance of time delays between registers and mitigates critical path delays.

Fast Forward Compilation:

If you require optimization beyond Hyper-Retiming, run Fast Forward compilation to generate timing closure recommendations that break key performance bottlenecks. Fast Forward compilation shows precisely where to make the most impact with RTL changes, and reports the performance benefits you can expect from each change.

Related Information

Altera Hyperflex Architecture High-Performance Design Handbook
Quartus Prime Pro Edition User Guide: Design Compilation
Quartus Prime Pro Edition User Guide: Scripting
Quartus Prime Pro Edition User Guide: Debug Tools

3.2.1. Command-Line Executable Equivalents

The table and following sections describe and compare the two software flows using command line executables. The examples belong to the fir_filter design, included in the Quartus Prime Pro Edition installation.

Table 8. Command-Line Executable Equivalents

| AMD Xilinx Vivado Software | AMD Xilinx Vivado Software | Quartus Prime Pro Edition Software | Description | |----------------------------------|------------------------------|--------------------------------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | Non-Project Mode | Project Mode | | | | read_ip | add_files import_files | quartus_ipgenerate | IP generation | | synth_design opt_design | launch_runs synth_1 | quartus_syn | Elaboration checks for design files and project errors. Translates project design files (for example, RTL or EDA netlist), and maps design elements to device resources. | | place_design phys_opt_design (7) | launch_runs impl_1 | quartus_fit (full compile) OR | Places and routes the device resources into the FPGA. | | continued... | continued... | continued... | continued... |

3. FPGA Tools Comparison

| AMD Xilinx Vivado Software | AMD Xilinx Vivado Software | Quartus Prime Pro Edition Software | Description | |------------------------------------|------------------------------------|-----------------------------------------------------------------------------------|-------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | Non-Project Mode | Project Mode | Quartus Prime Pro Edition Software | Description | | route_design phys_opt_design (7) | | quartus_fit --plan quartus_fit --place quartus_fit --route quartus_fit --finalize | | | Not Available | Not Available | quartus_fit --retime (8) | Enabled by default, and runs before finalizing. Moves existing registers into Hyper-Registers for fine-grained performance improvement. | | Not Available | Not Available | quartus_fit --fastforward (8) | Disabled by default. Runs after retime but before finalize. Generates detailed reports that estimate performance gains achievable by making specific RTL modifications. | | report_timing | report_timing | quartus_sta | Performs a static timing analysis on the design. | | write_bitstream | write_bitstream | quartus_asm | Generates programming file from post-place-and-route design. | | report_power | report_power | quartus_pow | Performs power estimation on the design. | | write_sdf write_verilog write_vhdl | write_sdf write_verilog write_vhdl | quartus_eda | Generates output netlist files for use with other EDA tools. | | write_checkpoint | write_checkpoint | quartus_cdb | Saves the snapshot of the design database. | | Not Available | Not Available | quartus_sh --flow compile | Automates the compilation flow. |

For command line help on any of the Quartus Prime executables, type <commandline executable> --help at the command prompt. A GUI-enabled help browser is also available that covers all Quartus Prime command-line executables.

(8) Retime and Fast-Forward Compilation available only for Agilex 7 and Stratix 10 devices.

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Figure 2. Command-Line Help

Start this browser by typing quartus_sh --qhelp at the command prompt.

3.2.1.1. synth_design

In the Quartus Prime Pro Edition command-line flow, the quartus_syn executable performs both synthesis ( synth_design ) and mapping of design elements to device resources ( opt_design ).

The following command runs logic synthesis and technology mapping of a design named filtref:

quartus_syn filtref --rev=<revision-name>

For command line help, type quartus_syn --help at the command prompt.

Note:

3.2.1.2. place_design/route_design

Depending on the use mode, the Vivado software provides different commands to place and route device resources into the FPGA device. In Project Mode, the launch_runs impl 1 executable performs place and route, and the equivalent Quartus Prime Pro Edition executable is quartus_fit . In Non-Project Mode, the Vivado software provides the place_design and route_design executables. The Quartus Prime Pro Edition software allows you perform place and route stages separately in the quartus_fit executable through arguments.

The Quartus Prime Pro Edition Fitter includes the following stages:

Plan-places all periphery elements (such as I/Os and PLLs) and determines a legal clock plan, without core placement or routing.
Place-places all core elements in a legal location.
Route-creates all routing between the elements in the design.

Retime (9) -performs register retiming and moves existing registers into HyperRegisters to increase performance by removing retiming restrictions and eliminating critical paths.
Finalize-for Arria 10 and Cyclone 10 GX devices, converts unnecessary tiles to High-Speed or Low-Power. For Stratix 10 devices, performs post-route.
Fast Forward (9) -generates detailed reports that estimate performance gains achievable by making specific RTL modifications.

You can run each Fitter stage standalone by providing the appropriate argument to the quartus_fit executable. For more information, run quartus_fit --help .

The following example performs place-and-route by fitting the logic of the Quartus Prime Pro Edition filtref project:

quartus_fit filtref

For command line help, type quartus_fit --help at the command prompt.

3.2.1.3. report_timing

In place of the report_timing_summary executable that the Vivado software provides for performing a static timing analysis on your design, the Quartus Prime Pro Edition software provides the quartus_sta executable.

To specify timing constrains, the Quartus Prime Pro Edition software uses the industry standard Synopsys* Design Constraint (SDC) file format. The AMD Xilinx's Design Constraint File ( .xdc ) constraint format is based on the SDC format. For details on converting XDC to SDC files, refer to the Timing Constraints section.

This example performs timing analysis on the filtref project using the SDC timing constraints file, filtref.sdc , to determine whether the design meets the timing requirements:

quartus_sta filtref --sdc=filtref.sdc

For command line help, type quartus_sta --help at the command prompt.

Related Information

Timing Constraints on page 86
Create Timing Constraints with the Timing Analyzer Text Editor on page 27

3.2.1.4. write_bitstream

The Vivado software provides the write_bitstream executable to generate FPGA programming files. The Quartus Prime software provides the quartus_asm executable to generate programming files for FPGA configuration.

The following example creates the filtref.sof programming file for the filtref project:

quartus_asm filtref

(9) Retime and Fast-Forward Compilation available only for Agilex 7 and Stratix 10 devices.

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For command line help, type quartus_asm --help at the command prompt.

3.2.1.5. write_sdf/write_verilog/write_vhdl

In Vivado, the write_sdf executable reads data from design files, and writes timing delays in .sdf files. The write_verilog executable uses this output and generates the netlists for third-party tools. Similarly, the Quartus Prime Pro Edition software provides the quartus_eda executable to generate netlists and other output files for use with third-party EDA tools.

The following example creates the filtref.vo simulation Verilog HDL netlist file, that you can use to simulate the filtref project with ModelSim*:

quartus_eda filtref --simulation=on --format=verilog --tool=modelsim

For command line help, type quartus_eda --help at the command prompt.

3.2.1.6. report_power

The report_power executable provides power and thermal estimates after place and route to estimate a design's power consumption. Similarly, quartus_pow estimates the thermal dynamic and thermal static power that a design consumes.

The following example uses a .vcd file as input to perform power analysis and filter glitch on the filtref project:

quartus_pow filtref --input_vcd=<vcd filename> --vcd_filter_glitches=on

For command line help, type quartus_pow --help at the command prompt.

Related Information

Value Change Dump (VCD) Support on page 89

3.2.1.7. write_checkpoint

In Vivado, the write_checkpoint command allows you to save a project at any point in the design process. In the Quartus Prime Pro Edition software, you can export a synthesized or final snapshot of the compile by using the quartus_cdb executable.

In addition, you can use the quartus_cdb executable to import and export versioncompatible databases. This ability simplifies design migration between versions of the Quartus Prime Pro Edition software; you can import a database from a version of the Quartus Prime Pro Edition into another version of the software, without the need of full compilation. After import, you need to rerun only timing analysis or simulation with the updated timing models.

Related Information

Design Optimization on page 44
Exporting Compilation Results in Quartus Prime Pro Edition User Guide: Design Compilation
Partition Snapshot Preservation and Reuse

3.2.1.8. Run Complete Design Flow

The Quartus Prime Pro Edition shell ( quartus_sh ) provides the --flow option, that allows you to perform complete compilation of a design project, including synthesis, implementation, timing analysis and bitfile generation. The AMD Xilinx Vivado software does not have a similar command.

The following example runs compilation, timing analysis, and programming file generation with a single command:

quartus_sh --flow compile filtref

You can also use the -start and -stop options of the the quartus_sh --flow command to start and stop a compilation flow at specific compilation tasks.

For command line help, type quartus_sh --help=flow at the command prompt.

Related Information

Quartus Prime Pro Edition User Guide: Scripting

3.2.2. Programming and Configuration File Support in the Quartus Prime Pro Edition Software

The Quartus Prime Pro Edition software requires different programming and configuration files based on the type of device and configuration mode.

Use the quartus_pgm command to access the Quartus Prime Pro Edition Programmer functionality and for scripting programming file generation.

Refer to the Quartus Prime Pro Edition User Guide: Programmer for information on programming file generation and how to use the Quartus Prime Pro Edition Programmer.

Related Information

Quartus Prime Pro Edition User Guide: Programmer

3.3. FPGA Design Flow Using Tools with GUIs

The Quartus Prime Pro Edition and the Vivado software GUIs address the major FPGA design steps in different ways.

Table 9. GUI Feature Equivalents

| GUI Feature | AMD Xilinx Vivado Software | Quartus Prime Pro Edition Software | |------------------|------------------------------|--------------------------------------| | Project Creation | New Project | New Project Wizard | | Design Entry | HDL Editor | HDL Editor | | Design Entry | EDA Netlist | EDA Netlist | | Design Entry | - | Schematic/Block Editor | | Design Entry | - | State Machine Editor | | Design Entry | - | State Machine Viewer | | continued... | continued... | continued... |

3. FPGA Tools Comparison

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| GUI Feature | AMD Xilinx Vivado Software | Quartus Prime Pro Edition Software | |----------------------------------------|---------------------------------------------------------------------------------------------|------------------------------------------------------------------------------------------------------------------------------------------| | GUI Feature | IP Catalog | IP Catalog and Parameter Editor | | GUI Feature | IP Integrator | Platform Designer System Integration Tool | | GUI Feature | IP Packager | Platform Designer Component Editor | | IP Status | Report IP Status | Upgrade IP Components | | Design Constraints | Device, Physical and Timing Constraints window | Assignment Editor, Timing Analyzer Text Editor | | Synthesis | Synthesis | Analysis and Synthesis | | Synthesis | Third-Party EDA Synthesis | Third-Party EDA Synthesis | | Design Implementation | Implementation | Fitter (Plan, Place, Route, Retime (11) and Finalize) | | Finalize Pinout | Byte Planner for memory banks Device Window and Package Window in I/O Planning View Layout | Interface Planner Tile Interface Planner Pin Planner | | Viewing and Editing Design Placement | Device Window (in I/O Planner View Layout) Package Window (in I/O Planner View Layout) | Chip Planner | | Static Timing Analysis | Report Timing | Timing Analyzer | | Generation of Device Programming Files | Hardware Manager | Assembler | | Power Analysis | AMD Xilinx Power Estimator (XPE) Report Power | Power and Thermal Calculator (PTC) Early Power Estimation (EPE) Power Analyzer | | Simulation | Vivado Simulator | Questa* - Altera FPGA Starter Edition | | | Third-Party Simulation Tools | Third-Party Simulation Tools | | Hardware verification | Hardware Manager | System Console | | | Integrated Logic Analyzer (ILA) and System ILA IP | Signal Tap Logic Analyzer | | | AMD Xilinx Virtual Input Output (VIO) | In-System Sources and Probes | | | JTAG-to-AXI Master | System Console | | | IBERT IP and Serial I/O Analyzer Tool | Transceiver Toolkit | | | Memory Calibration Debug Tool | EMIF Debug Toolkit EMIF Debug GUI | | | Remote Debug using AMD Xilinx Virtual Cable (XVC) | Remote Debug using existing TCP/IP connection | | | - | Signal Probe In-System Memory Content Editor Logic Analyzer Interface (LAI) | | View Netlist | Schematic Window (Elaborated) Schematic Window (Synthesized) Schematic Window (Implemented) | RTL Viewer (Post Synthesis) Technology Map Viewer (Post-Mapping) Technology Map Viewer (Post-Fitting) Fast Forward Viewer (Post-Fitting) |

| GUI Feature | AMD Xilinx Vivado Software | Quartus Prime Pro Edition Software | |------------------------------------|------------------------------|--------------------------------------| | Design Optimization | - | Hyper-Aware Design Flow (10) | | Design Optimization | Physical Optimization | Physical Synthesis Optimization | | Techniques to improve productivity | Incremental Compile | Block-Based Design Flows | | Techniques to improve productivity | Hierarchical Design | Block-Based Design Flows | | Techniques to improve productivity | - | Design Space Explorer II (DSE) | | Techniques to improve productivity | Design Rule Checking | Design Assistant | | Techniques to improve productivity | Intermediate Design | Snapshot Viewer | | Partial Reconfiguration | Yes | Yes | | Output Products | Design Checkpoints | Export Design Partitions | | Add-On Development Tools | Vivado High-Level Synthesis | High-Level Synthesis Compiler |

3.3.1. Project Creation

Table 10. IP Status Comparison

Similar to the New Project command in the Vivado software, the Quartus Prime Pro Edition software provides the New Project Wizard tool ( File ➤ New Project Wizard ), which guides you through specifying a project name and directory, top-level design entity, any EDA tools you are using, and a target device.

Comparison

After creating a new project, the Quartus Prime Pro Edition software automatically generates the following project files necessary for successful compilation:

Table 11. Project Files Comparison

| | AMD Xilinx Vivado | AMD Xilinx Vivado | Quartus Prime Pro Edition | Quartus Prime Pro Edition | |------------------|---------------------------------------------|--------------------------------------------------------------------------------------------|--------------------------------------|-------------------------------------------------------------------------------------------------| | | File Type | Description | File Type | Description | | Project File | AMD Xilinx Project File ( .xpr ) | XML file with list of files. Contains the information about target device or design files. | Quartus Prime Project File ( .qpf ) | Project and revision name | | Project Settings | AMD Xilinx Design Constraints File ( .xdc ) | Contains Synthesis, placement and timing constraints | Quartus Prime Settings File ( .qsf ) | Lists design files, entity settings, target device, synthesis directives, placement constraints |

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Features

You can modify the compiler settings by changing the assignments through the GUI or directly on the .qsf file.

Note:

Avoid modifying assignments through the .qsf file and through the GUI simultaneously.

3.3.2. Design Entry

The Quartus Prime software supports all the design entry methods that the Vivado software supports.

Table 12. Design Entry Methods Comparison

| GUI Feature | AMD Xilinx Vivado Software | Quartus Prime Pro Edition Software | |---------------|------------------------------|-------------------------------------------| | Design Entry | HDL Editor | HDL Editor | | Design Entry | EDA Netlist | EDA Netlist | | Design Entry | - | Schematic/Block Editor | | Design Entry | - | State Machine Editor | | Design Entry | - | State Machine Viewer | | Design Entry | IP Catalog | IP Catalog and Parameter Editor | | Design Entry | IP Integrator | Platform Designer System Integration Tool | | Design Entry | IP Packager | Platform Designer Component Editor |

Managing Project Files

In the AMD Xilinx Vivado software, you use the Add Source dialog box to add or remove existing design files. To add or remove existing design files from a project in the Quartus Prime software:

Click Assignments ➤ Settings to open the Settings dialog box.
In the Category list, select Files to open the Files page. This page allows you to add or remove files.

3.3.2.1. HDL Editor

In the Vivado software you create a new HDL design file using the New Source Wizard on the Project menu. To create a new HDL design file in the Quartus Prime Pro Edition software, click File ➤ New , and then select the type of file you want to create.

To assist you in creating HDL designs, the Quartus Prime software provides design example templates for VHDL and Verilog HDL, including language constructs examples to help you get started on a design.
The Quartus Prime Text Editor offers syntax coloring for highlighting HDL reserved words and comments.

Related Information

Quartus Prime Pro Edition User Guide: Design Recommendations

3.3.2.2. Schematic/Block Editor

In the Quartus Prime Pro Edition software, you can use Altera FPGA-supplied design elements, such as Boolean gates and registers, or you can create your own symbols from HDL or EDA netlist design entities.

To create a block design file from a VHDL or Verilog HDL design file, click File ➤ Create/Update , and click Create Symbol Files for Current File .
To create a new schematic file ( *.bdf ) in the Quartus Prime Pro Edition software, point to File ➤ New and select the Block Diagram/Schematic File .
To insert block symbols into the schematic, double-click the schematic file and choose the appropriate block symbols.

Figure 3. Schematic File

3.3.2.3. State Machine Editor

The Quartus Prime Pro Edition software supports graphical state machine entry. To create a new finite state machine (FSM) design:

Click File ➤ New .
In the New dialog box, expand the Design Files list, and then select State Machine File .

3.3.2.4. IP Catalog and Parameter Editor

Use the IP Catalog to generate Altera FPGA equivalents for AMD Xilinx primitives and IP Catalog cores. To display the IP Catalog in the Quartus Prime Pro Edition software, click View ➤ IP Catalog .

Features of the IP Catalog

Allows you to create custom IP cores that are optimized for the design's target device.
Altera provides a library-of parameterized-modules (LPM). This library offers architecture-independent functions for all devices that the Quartus Prime Pro Edition supports.
The IP Catalog is also available from Platform Designer. The Platform Designer IP Catalog includes exclusive system interconnect, video and image processing, and other system-level IPs that are available only if you access the IP Catalog from Platform Designer. To open Platform Designer from the Quartus Prime Pro Edition software, click Tools ➤ Platform Designer . To display the IP Catalog from Platform Designer, click View ➤ IP Catalog .

Related Information

IP Catalog and Parameter Editor in Quartus Prime Pro Edition Help
Altera FPGA IP Cores/LPM in Quartus Prime Pro Edition Help

3.3.2.5. Platform Designer System Integration Tool

Similar to AMD Xilinx's Vivado IP Integration tool, Altera FPGA provides the Platform Designer System Integration tool ( Tools ➤ Platform Designer ).

Features

Platform Designer enables the use of processors (such as the Altera FPGA Nios II embedded processor), interfaces to off-chip processors, standard peripherals, IP cores, on-chip memory, off-chip memory, and user-defined logic into a custom system module.

Platform Designer generates a single system module that instantiates these components and automatically generates the necessary interconnect logic to bind them together.

Migration

When migrating from AMD Xilinx to Altera FPGA, one of the main differences to consider while creating systems is the standard bus interface:

AMD Xilinx uses AMBA* AXI as the standard bus interface for communication between IPs. Consequently, custom IPs that you build with Vivado software use the AMBA 4 AXI protocol.
Even though Altera FPGA uses Avalon ® as the standard bus interface, Platform Designer supports multiple AMBA AXI interfaces. For details about interface support, refer to Quartus Prime Pro Edition User Guide: Platform Designer .

Alternatively, Platform Designer makes the migration easier by allowing conversion from Avalon to AMBA AXI interface via AMBA AXI Agents and AMBA AXI translators.

For more information about system design with Platform Designer and AMBA AXI Protocol Support in Platform Designer, refer to Quartus Prime Pro Edition User Guide: Platform Designer .

Related Information

Creating a System with Platform Designer in Quartus Prime Pro Edition User Guide: Platform Designer
Platform Designer Transformations in Quartus Prime Pro Edition User Guide: Platform Designer
Platform Designer Interface Support in Quartus Prime Pro Edition User Guide: Platform Designer

3.3.2.6. Platform Designer Component Editor

In the Vivado software, you can use the IP Packager to add custom IPs to the IP catalog. In the Quartus Prime Pro Edition software, you create and package IP components with the Platform Designer Component Editor.

To create a new component using the Component Editor, in the Platform Designer main window click File ➤ New Component .
When you define a component with the Component Editor, Platform Designer writes the information to an _hw.tcl file. This file contains the component's description, interfaces, and HDL files.
If the component requires custom features that the Platform Designer Component Editor does not support, for example, an elaboration callback, you can use the Component Editor to create the _hw.tcl file, and then manually edit the file to complete the component definition.

Related Information

Creating Platform Designer Components in Quartus Prime Pro Edition User Guide: Platform Designer

3.3.3. IP Status

When migrating a project in the Vivado software, the Report IP Status window displays the list of IPs and the recommendation for upgrading, among other information. The Quartus Prime Pro Edition software uses the Upgrade IP Components window.

Table 13. IP Status Tools Comparison

When you open a project containing outdated IP, the Project Navigator displays a banner indicating the IP upgrade status. Click Launch IP Upgrade Tool or Project ➤ Upgrade IP Components to upgrade outdated IP cores.

Icons in the Upgrade IP Components dialog box indicate when IP upgrade is required, optional, or unsupported for IP cores in your design. You must upgrade IP cores that require upgrade before you can compile the IP variation in the current version of the Quartus Prime Pro Edition software. The upgrade process preserves the original IP variation file in the project directory as <my_variant>_BAK.qsys

Related Information

Upgrade IP Components Dialog Box (Project Menu) in Quartus Prime Pro Edition Help

3.3.4. Design Constraints

The Vivado software provides GUI editors (Device/Physical/Timing windows) to create and edit design constraints. AMD Xilinx designs store all the constraints and attributes in AMD Xilinx Design Constraint ( .xdc ) files, including timing and device constraints. You can also edit .xdc files with a text editor.

Altera FPGA designs use separate files for device ( .qsf ) and timing ( .sdc ) constraints, and stores timing constraints in Synopsys Design Constraints (SDC) format. To view and edit pin assignments, device options, and logic options, use the Assignment Editor. To view and edit timing constraints, use the Text Editor in the Timing Analyzer GUI.

Table 14. Design Constraint Comparison

| GUI Feature | AMD Xilinx Vivado Software | Quartus Prime Pro Edition Software | |--------------------|------------------------------------------------|------------------------------------------------| | Design Constraints | Device, Physical and Timing Constraints window | Assignment Editor, Timing Analyzer Text Editor |

Features

The table summarizes the file format and assignment types that the tools in the Quartus Prime Pro Edition software set.

Table 15. Quartus Prime Pro Edition Assignment Tools

| Assignment Type | File Format | Tools to Make Assignments | |-------------------|---------------|--------------------------------| | Timing | SDC | Timing Analyzer | | I/O-related | TCL | Timing Analyzer | | | QSF | Pin Planner, Interface Planner | | Others | | Assignment Editor |

With separate constraint files, you avoid searching for timing constraints among other device constraints. Additionally, you can modify the timing constraints and check for validity without recompiling. In place of the I/O Planning in the Vivado software, Quartus Prime Pro Edition software offers the Interface Planner to plan interfaces and device periphery, and the Pin Planner to edit, validate, and export pin assignments.

For equivalence between design constraints, refer to the Set Equivalent AMD Xilinx Design Constraints section.

Related Information

Quartus Prime Pro Edition User Guide: Design Constraints

3.3.4.1. Assignment Editor

The Quartus Prime Assignment Editor ( Assignments ➤ Assignment Editor ) allows you to add device and placement constraints to a design. The Assignment Editor provides a spreadsheet-like interface for assigning all instance-specific settings and constraints.

The Quartus Prime software dynamically validates changes that you make through the editor, and issues errors or warnings for invalid assignments.

The System tab of the Quartus Prime message window acknowledges adding or changing assignments.

Figure 4. Quartus Prime Assignment Editor

Related Information

Assignment Editor (Assignments Menu) in Quartus Prime Pro Edition Help

3.3.4.2. Create Timing Constraints with the Timing Analyzer GUI

To create timing constraints with the Timing Analyzer GUI:

Create a timing netlist by clicking Netlist ➤ Create Timing Netlist .
Click File ➤ New SDC File to open a new SDC file.
From the Constraints menu, select the constraint you want to add..

The selected constraint's dialog box opens, and allows you to set the constraint's parameters.

Figure 5. Example: Create Clock Dialog Box

Enter the values in the dialog box, and click Insert to insert the SDC command into the open SDC file.
Save the updated SDC file.

The constraints are available on the Constraint menu are:

3. FPGA Tools Comparison

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Create Clock
Create Generated Clock
Set Clock Latency
Set Clock Uncertainty
Set Clock Groups
Remove Clock
Set Input Delay
Set Output Delay

Related Information

Constraints in Quartus Prime Pro Edition Help

3.3.4.3. Create Timing Constraints with the Timing Analyzer Text Editor

The Quartus Prime Timing Analyzer ( Tools ➤ Timing Analyzer ) reads and writes timing constrains in the industry-standard Synopsys Design Constraint (SDC) format. The Timing Analyzer provides a GUI interface that allows you to manually create and modify timing constraints.

Note:

Ensure that the project is open before using the Timing Analyzer.

To create a new SDC file from the Timing Analyzer, click File ➤ New SDC File .
To apply templates for SDC constraints, click Edit ➤ Insert Template command. The Timing Analyzer Text Editor uses syntax coloring for SDC reserved words and comments.

Figure 6. Timing Analyzer Text Editor

Related Information

Timing Analyzer Cookbook
Quartus Prime Pro Edition User Guide: Timing Analyzer

3.3.5. Synthesis

The Quartus Prime Pro Edition Synthesis provides full support for VHDL, Verilog HDL, SystemVerilog, and Block Design File ( .bdf ) schematic entry.

Derive PLL Clocks
Derive Clock Uncertainty
Set False Path
Set Multicycle Path
Set Maximum Delay
Set Minimum Delay
Set Net Delay

Table 16. Synthesis Comparison

Features

The Quartus Prime Pro Edition Synthesis engine enforces strict industry-standard HDL structures.

Synthesis supports Verilog Quartus Mapping ( .vqm ) files generated by third-party EDA tools. It can also generate a .vqm netlist with quartus_eda that can be used with other EDA tools.

At the end of synthesis, the Compiler generates an atom netlist, which is a database of the atom elements that design synthesis requires to implement the design in silicon. The Analysis & Synthesis module of the Compiler creates one or more project databases for each design partition. You can specify various settings that affect synthesis processing.

Access

The Assignments ➤ Settings ➤ IP Settings dialog box allows you to control the IP regeneration stage for synthesis or simulation

The Assignments ➤ Settings ➤ Compiler Settings ➤ Advanced Settings (Synthesis) dialog box allows you to set options that affect the analysis and synthesis stage of the compilation flow. These options include Optimization Technique, State Machine Processing, Restructure Multiplexers, and others.

Related Information

Design Synthesis in Quartus Prime Pro Edition User Guide: Design Compilation
Quartus Prime Pro Edition User Guide: Third-party Synthesis
Generating a VQM Netlist for other EDA Tools in Quartus Prime Pro Edition User Guide: Design Compilation

3.3.6. Design Implementation

The implementation flow in the Vivado software places and routes the netlist onto the FPGA device resources based on the constraints of the design. The Finalize flow in the Quartus Prime Pro Edition software consists of the Plan, Place, Route, Retime (11) , and Finalize compilation stages. Start the Finalize flow by clicking Fitter in the Compilation Dashboard.

Table 17. Design Implementation Comparison

| GUI Feature | AMD Xilinx Vivado Software | Quartus Prime Pro Edition Software | |-----------------------|------------------------------|-------------------------------------------------------| | Design Implementation | Implementation | Fitter (Plan, Place, Route, Retime (11) and Finalize) |

Features

The Quartus Prime Pro Edition Compiler offers unique features, such as:

Snapshot Viewer-analyze the results of a compilation snapshot to evaluate the design before running the next stage, or running a full compilation. Compiler snapshots can be used to isolate potential problems.
Incremental Fitter Optimizations-run and optimize Fitter stages incrementally. Each Fitter stage generates detailed reports. You can view detailed report data and analyze the timing of each stage while downstream stages are still running.
Hyper-Aware Design Flow-use Hyper-Retiming and Fast Forward compilation for the highest performance in Agilex 7 and Stratix 10 devices.

You can start each phase in the compilation flow independently either from GUI or from the command line. The Compilation Dashboard allows you to use the tools and features of the software and monitor progress from a flow-based layout.

Access

The Assignments ➤ Settings ➤ Compiler Settings ➤ Advanced Settings (Fitter) dialog box allows you customize the place and route of the compilation flow.

Limitations

DSP register packing in Quartus Prime Pro Edition is subject to limitations. For a list of reasons that prevent DSP register packing, refer to the 'Fixed Point DSP Register Packing Summary and Fixed Point DSP Register Packing Details' section of 'Fitter Feature Specific Reports' in the Quartus Prime Pro Edition Help at the following URL:

https://www.intel.com/content/www/us/en/programmable/quartushelp/current/ report/rpt/rpt_file_fit_feature_specific.htm

Related Information

Compilation Dashboard in Quartus Prime Pro Edition Help
Fitter Settings Reference in Quartus Prime Pro Edition User Guide: Design Compilation
Concurrent Analysis During Synthesis or Fitting in Quartus Prime Pro Edition User Guide: Design Compilation

3.3.7. Finalize Pinout

In the Vivado software, you can use the I/O Planning View Layout to finalize the pinout. For I/O planning of Memory Interfaces, the Vivado software uses the Memory Bank/Byte Planner.

Quartus Prime Pro Edition Software provides the Interface Planner and the Pin Planner to help you with the I/O Planning.

Table 18. Finalize Pinout Comparison

| GUI Feature | AMD Xilinx Vivado Software | Quartus Prime Pro Edition Software | |-----------------|--------------------------------------------------------------------------------------------|------------------------------------------------------| | Finalize Pinout | Byte Planner for memory banks Device Window and Package Window in I/O Planning View Layout | Interface Planner Tile Interface Planner Pin Planner |

3.3.7.1. Pin Planner

The Quartus Prime Pro Edition Pin Planner provides a graphical package view, allowing you to validate I/O assignments by performing legality checks on a design's I/O pins and surrounding logic. With the Pin Planner, you can identify I/O banks, VREF groups, and differential pin pairings to help you with the I/O planning process. To access the Pin Planner, click Assignments ➤ Pin Planner .

Note:

Modifications that you make in the Pin Planner affect the .qsf file.

Figure 7. Quartus Prime Pro Edition Pin Planner

To invoke the Pin Planner, click Assignments ➤ Pin Planner

Related Information

Managing Device I/O Pins in Quartus Prime Pro Edition User Guide: Design Constraints

3.3.7.2. Interface Planner

The Vivado software supports I/O exploration and assignment via the I/O Planning View Layout.

In the Quartus Prime Pro Edition software, the Interface Planner tool ( Tools ➤ Interface Planner ) simplifies the planning of accurate constraints for physical implementation after synthesis, with features such as:

Prototype interface implementations
Plan clocks
Rapidly define a legal device floorplan

AN 307: Altera ® FPGA Design Flow for AMD* Xilinx* Users

Figure 8. Interface Planner GUI

Related Information

Interface Planning in Quartus Prime Pro Edition User Guide: Design Constraints

3.3.7.3. Tile Interface Planner

Tile Interface Planner helps quickly place component IP in legal tile locations on the FTile available in some Agilex 7 devices.

Related Information

Using Tile Interface Planner in Quartus Prime Pro Edition User Guide: Design Constraints

3.3.8. Viewing and Editing Design Placement

The Vivado software provides the Device Window for floorplanning and design analysis. In the Quartus Prime Pro Edition software, the Chip Planner simplifies floorplan analysis by providing visual display of chip resources.

Table 19. Design Placement Methods Comparison

| GUI Feature | AMD Xilinx Vivado Software | Quartus Prime Pro Edition Software | |--------------------------------------|----------------------------------------------------------------------------------------|--------------------------------------| | Viewing and Editing Design Placement | Device Window (in I/O Planner View Layout) Package Window (in I/O Planner View Layout) | Chip Planner |

With the Chip Planner, you can view post-compilation placement, connections, and routing paths. You can also make assignment changes, such as creating and deleting resource assignments.

Figure 9. Chip Planner

To open the Chip Planner, click Tools ➤ Chip Planner .

3.3.9. Static Timing Analysis

The Report Timing Summary in Vivado generates the Post-Place and Post-Route Static Timing Report. Similarly, the Altera FPGA Timing Analyzer analyzes and reports the performance of all logic in your design, allowing you to determine all the critical paths that limit your design's performance.

Table 20. Static Timing Analysis Methods Comparison

| GUI Feature | AMD Xilinx Vivado Software | Quartus Prime Pro Edition Software | |------------------------|------------------------------|--------------------------------------| | Static Timing Analysis | Report Timing | Timing Analyzer |

The Altera FPGA Timing Analyzer is an easy-to-use, second-generation, ASIC-strength static timing analyzer that supports the industry-standard Synopsys Design Constraints (SDC) format.

3. FPGA Tools Comparison

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Figure 10. Timing Analyzer GUI

The major difference between performing timing analysis with the Report Timing Summary in Vivado and the Altera FPGA Timing Analyzer is that in the Vivado software, a change in timing constraint triggers a recompile. In contrast, the Timing Analyzer GUI allows you to experiment with timing constraints and timing model without recompiling.

Access

Static timing analysis with the Timing Analyzer is part of the full compilation flow, but you can also run the module separately.

To run the Timing Analyzer over a post-fit netlist, click Processing ➤ Start ➤ Start Timing Analyzer .

To open the Timing Analyzer GUI, click Tools ➤ Timing Analyzer .

Related Information

Timing Analyzer Cookbook
Quartus Prime Pro Edition User Guide: Timing Analyzer

3.3.10. Generation of Device Programming Files

Similar to the Hardware Manager in the AMD Xilinx Vivado software, the Assembler in the Quartus Prime Pro Edition software generates files that the Programmer can use to program or configure a device with Altera FPGA programming hardware.

Table 21. Methods to Generate Programming Files Comparison

| GUI Feature | AMD Xilinx Vivado Software | Quartus Prime Pro Edition Software | |----------------------------------------|------------------------------|--------------------------------------| | Generation of Device Programming Files | Hardware Manager | Assembler |

Features

The Assembler converts the Fitter's device, logic cell, and pin assignments into a programming image for the device, in the form of one or more Programmer Object Files ( .pof ) or SRAM Object Files ( .sof ) for the target device. You use a .sof file to program Altera FPGA devices and a .pof file to configure Altera FPGA CPLD devices.

Assembler is a stage of the Quartus Prime Pro Edition full compilation flow. You can also run Assembler separately, by clicking Processing ➤ Start ➤ Start Assembler .

Related Information

Quartus Prime Pro Edition User Guide: Programmer

3.3.11. Power Analysis

Similar to the AMD Xilinx Power Estimator and Report Power tool, Altera provides tools that allow you to estimate power consumption from early design concept trough design implementation.

Table 22. Power Analysis Comparison

| GUI Feature | AMD Xilinx Vivado Software | Quartus Prime Pro Edition Software | |----------------|-----------------------------------------------|--------------------------------------------------------------------------------| | Power Analysis | AMD Xilinx Power Estimator (XPE) Report Power | Power and Thermal Calculator (PTC) Early Power Estimation (EPE) Power Analyzer |

For Agilex 7 and Stratix 10 devices, the Altera FPGA Power and Thermal Calculator (PTC) is integrated with Quartus Prime software to help you estimate power consumption and preliminary thermal assessments of your design. Run the PTC by selecting Tools ➤ Power and Thermal Calculator in the Quartus Prime GUI. You can also download a standalone version from the Power Estimators (EPE) and Power Analyzer page of the Altera FPGA Support Resources website.

For other device families, use the Early Power Estimation (EPE) tool. The EPE tool is a spreadsheet tool that helps you estimate power consumption at early design concept. Download the EPE tool from the Power Estimators (EPE) and Power Analyzer page on the Altera FPGA Support Resources website.

The Quartus Prime Pro Edition Power Analyzer tool performs post-fitting power analysis and generates a report that details power consumption of the design by block type and entity. To open the Power Analyzer tool, click Processing ➤ Power Analyzer Tool .

Related Information

Power Estimators and Power Analyzer
Quartus Prime Pro Edition User Guide: Power Analysis and Optimization
Altera FPGA Power and Thermal Calculator User Guide

3.3.12. Simulation

Both the AMD Xilinx Vivado and the Quartus Prime Pro Edition software support integration with third-party EDA simulation tools.

Table 23. Simulation Support Comparison

| GUI Feature | AMD Xilinx Vivado Software | Quartus Prime Pro Edition Software | |---------------|------------------------------|--------------------------------------| | Simulation | Vivado Simulator | Questa - Altera FPGA Starter Edition | | | Third-Party Simulation Tools | Third-Party Simulation Tools |

For a list of third-party EDA simulation tools supported by Quartus Prime Pro Edition software, refer to EDA Interface Information in the Quartus Prime Pro Edition Release Notes.

Access

To specify third-party simulation tools in the Quartus Prime Pro Edition software:

Click Assignments ➤ Settings .
In Category , click EDA Tool Settings .
Under Simulation select the simulation tool.

You can also specify third-party simulation tools in the New Project Wizard.

Related Information

EDA Interface Information in Quartus Prime Pro Edition Software and Device Support Release Notes

3.3.12.1. Simulation Models for Designs Containing LPMs or IP Cores

Functional Simulation

The Quartus Prime Pro Edition software provides functional simulation models that allow you to perform functional/behavioral simulation on designs containing LPMs or IP cores.

Table 24. Simulation Model Files

| | Verilog HDL | VHDL | |----------|---------------|----------------------------------------| | LPM | 220model.v | 220pack.vhd 220model.vhd | | IP cores | altera_mf.v | altera_mf.vhd altera_mf_components.vhd |

Gate-level Functional Simulation

To perform gate-level functional simulation on a design, the Quartus Prime Pro Edition software generates output netlist files containing information about how the design was placed into device-specific architectural blocks.

Table 25. Generated Output Files

| | Extension | |-------------------------|-------------| | Verilog HDL output file | .vo | | VHDL output file | .vho |

You can perform simulations with pre-compiled model libraries by using the Questa Altera FPGA Starter Edition simulator included in the Quartus Prime Pro Edition software. You can also compile your own selection of model libraries with the Simulation Library Compiler tool in the Quartus Prime Pro Edition software.

3.3.13. Hardware Verification

AMD Xilinx offers solutions for hardware debugging that have equivalent tools in Altera FPGA software. In contrast, not all Altera FPGA debug solutions have an equivalent AMD Xilinx tool.

Table 26. Hardware Verification Tools Comparison

| GUI Feature | AMD Xilinx Vivado Software | Quartus Prime Pro Edition Software | |-----------------------|---------------------------------------------------|-----------------------------------------------------------------------------| | Hardware verification | Hardware Manager | System Console | | Hardware verification | Integrated Logic Analyzer (ILA) and System ILA IP | Signal Tap Logic Analyzer | | Hardware verification | AMD Xilinx Virtual Input Output (VIO) | In-System Sources and Probes | | Hardware verification | JTAG-to-AXI Master | System Console | | Hardware verification | IBERT IP and Serial I/O Analyzer Tool | Transceiver Toolkit | | Hardware verification | Memory Calibration Debug Tool | EMIF Debug Toolkit EMIF Debug GUI | | Hardware verification | Remote Debug using AMD Xilinx Virtual Cable (XVC) | Remote Debug using existing TCP/IP connection | | Hardware verification | - | Signal Probe In-System Memory Content Editor Logic Analyzer Interface (LAI) |

3.3.13.1. System Console

AMD Xilinx Vivado software's Hardware Manager provides a TCL console to interact with the debug IP on the hardware. Similarly, in the Quartus Prime software, you can perform the same tasks using the System Console.

Table 27. System Console Features and Usage

| Features | Typical Usage | |--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | • Provides real-time in-system debugging capabilities using available debugging toolkits. • Allows you to read from and write to memory mapped components in a system without a processor or additional software. • Communicates with hardware modules in a design through a Tcl interpreter. • Allows you to take advantage of all the features of the Tcl scripting language. • Supports JTAG and TCP/IP connectivity. | • Perform system-level debugging. • Debug or optimize signal integrity of a board layout even before finishing the design. • Debug external memory interfaces. • Debug an Ethernet IP interface in real time. • Debug a PCI Express* link at the Physical, Data Link, and Transaction layers. • Debug and optimize high-speed serial links in your board design. |

Related Information

Analyzing and Debugging Designs with System Console in Quartus Prime Pro Edition User Guide: Debug Tools

3.3.13.2. Signal Tap Logic Analyzer

The Vivado software includes the Integrated Logic Analyzer (ILA) feature to debug post-implemented designs on a FPGA. Similarly, the Quartus Prime provides the Signal Tap logic analyzer; a multiple-input, digital acquisition instrument that captures and stores signal activity from any internal device node or nodes. The Signal Tap logic analyzer helps debug an FPGA design by probing the state of the internal signals in the design without using external equipment.

Table 28. Signal Tap Logic Analyzer Features and Usage

Related Information

Design Debugging with the Signal Tap Logic Analyzer in Quartus Prime Pro Edition User Guide: Debug Tools

3.3.13.3. In-System Sources and Probes

The Vivado software provides the Virtual Input/Output (VIO) debug feature to monitor and drive internal FPGA signals in real time. The equivalent in Altera FPGA software is the In-System Sources and Probes utility.

Table 29. In-System Sources and Probes Features and Usage

Related Information

Design Debugging Using In-System Sources and Probes in Quartus Prime Pro Edition User Guide: Debug Tools

3.3.13.4. Toolkit Explorer

For designs with debug-enabled IP, the Toolkit Explorer automatically lists the toolkits available for the IP in the design, including the transceiver toolkits.

You can access Toolkit Explorer in the GUI by selecting Tools ➤ System Debugging Tools ➤ System Debugging Toolkits or by going to the Toolkit Explorer pane in the System Console.

The following toolkits are available to launch from the System Console Toolkit Explorer in the current version of the Quartus Prime software:

External Memory Interfaces (EMIF) toolkits
Ethernet toolkit
PCI Express (PCIe) debug toolkits
Serial Lite IV IP toolkit
Transceiver PHY toolkits

External Memory Interfaces (EMIF) Toolkits

For external memory interfaces, the following toolkits are available:

EMIF Debug Toolkit

This toolkit helps you to debug external memory interfaces by accessing calibration data obtained during memory calibration. The analysis tools can evaluate the stability of the calibrated interface and assess hardware conditions.

EMIF Efficiency Monitor Toolkit

This toolkit helps you to debug external memory interfaces by measuring efficiency on the Avalon interface in real time. The generated EMIF design example can include the Efficiency Monitor block.

EMIF Traffic Generator Configuration Toolkit

This toolkit helps you to debug external memory interfaces by sending sample traffic through the external memory interface to the memory device. The generated EMIF design example includes a traffic generator block with control and status registers.

Table 30. Available EMIF Toolkits

| Toolkit | Supported Device Families | Documentation | |----------------------------------------------|---------------------------------------|------------------------------------------------------------------------------| | EMIF Debug Toolkit | Agilex 3 | External Memory Interfaces IP User Guide: Agilex 3 FPGAs and SoCs | | EMIF Debug Toolkit | Agilex 5 | External Memory Interfaces IP User Guide: Agilex 5 FPGAs and SoCs | | EMIF Debug Toolkit | Agilex 7 | External Memory Interfaces Agilex 7 M-Series FPGA IP User Guide | | EMIF Debug Toolkit | Agilex 7 | External Memory Interfaces Agilex 7 F-Series and I-Series FPGA IP User Guide | | EMIF Debug Toolkit | Arria 10 | External Memory Interfaces Arria 10 FPGA IP User Guide | | EMIF Debug Toolkit | Cyclone 10 GX | External Memory Interfaces Cyclone 10 GX FPGA IP User Guide | | EMIF Debug Toolkit | Stratix 10 | External Memory Interfaces Stratix 10 FPGA IP User Guide | | EMIF Efficiency Monitor Toolkit | Agilex 7 (F-Series and I-Series only) | External Memory Interfaces Agilex 7 F-Series and I-Series FPGA IP User Guide | | EMIF Efficiency Monitor Toolkit | Stratix 10 | External Memory Interfaces Stratix 10 FPGA IP User Guide | | EMIF Traffic Generator Configuration Toolkit | Agilex 7 (F-Series and I-Series only) | External Memory Interfaces Agilex 7 F-Series and I-Series FPGA IP User Guide | | EMIF Traffic Generator Configuration Toolkit | Stratix 10 | External Memory Interfaces Stratix 10 FPGA IP User Guide |

Ethernet Toolkit

The Ethernet Toolkit is a TCL-based debugging tool that allows you to interact with an Ethernet Altera FPGA IP in real time.

Table 31. Available Ethernet Toolkits

| Toolkit | Supported Device Families | Documentation | |------------------|------------------------------------------------------------------------------------------------------------------------------------------------|-----------------------------| | Ethernet Toolkit | For a list of supported Ethernet IPs, Tiles, and devices, refer to Supported Ethernet IP Cores and Devices in the Ethernet Toolkit User Guide. | Ethernet Toolkit User Guide |

PCI Express Debug Toolkits

The PCI Express (PCIe) debug toolkits are System Console-based tools that provide real-time control, monitoring, and debugging of the PCIe links at the Physical, Data Link, and Transaction layers.

Table 32. Available PCIe Debug Toolkits

| Toolkit Name | Supported Device Families | Documentation | |---------------------------------------------|-----------------------------|-------------------------------------------------------------------------------------------------------------------------------------------| | Agilex 5 Debug Toolkit | Agilex 5 | Overview of the Agilex ™ 5 Debug Toolkit | | F-Tile Debug Toolkit | Agilex 7 | Overview of the F-Tile Debug Toolkit | | P-Tile Debug Toolkit | Agilex 7 Stratix 10 | Overview of the P-Tile Debug Toolkit (Avalon Memory-mapped interfaces) Overview of the P-Tile Debug Toolkit (Avalon streaming interfaces) | | R-Tile Debug Toolkit | Agilex 7 | Overview of the R-Tile Debug Toolkit | | Multi Channel DMA IP for PCIe Debug Toolkit | Agilex 7 Stratix 10 | Overview of the Multi Channel DMA IP for PCIe Debug Toolkit | | Scalable Switch IP Debug Toolkit | Agilex 7 Stratix 10 | Scalable Switch FPGA IP for PCI Express* User Guide |

Serial Lite IV IP Toolkit

The Serial Lite IV IP Toolkit is an inspection tool that monitors the status of a Serial Lite IV IP link and provides a step-by-step guide for the IP link initialization sequences.

Table 33. Available Serial Lite IV IP Toolkits

| Toolkit Name | Supported Device Families | Documentation | |---------------------------|-----------------------------|--------------------------------------| | Serial Lite IV IP Toolkit | Agilex 7 | Agilex 7 Serial Lite IV IP Toolkit | | Serial Lite IV IP Toolkit | Stratix 10 | Stratix 10 Serial Lite IV IP Toolkit |

Transceiver PHY Toolkits

Transceiver PHY toolkits help you to optimize high-speed serial links in your board design by providing real-time control, monitoring, and debugging of the transceiver links that run on your board.

| Toolkit Name | Supported Device Families | Documentation | |-------------------------------------------|-----------------------------|----------------------------------------------| | Arria ® 10 Transceiver PHY Toolkit | Arria 10 | Arria 10 Debugging Transceiver Toolkit | | Cyclone 10 GX Transceiver PHY Toolkit | Cyclone 10 GX | Enable the Cyclone 10 GX Transceiver Toolkit | | E-Tile Transceiver PHY Toolkit | Agilex 7 | E-Tile Transceiver Toolkit Overview | | E-Tile Transceiver PHY Toolkit | Stratix 10 | E-Tile Transceiver Toolkit Overview | | F-Tile Transceiver PHY Toolkit | Agilex 7 | F-Tile Transceiver Toolkit Overview | | GTS Transceiver PHY Toolkit | Agilex 5 | GTS Transceiver Toolkit | | L-Tile and H-Tile Transceiver PHY Toolkit | Stratix 10 | L-Tile and H-Tile Transceiver Toolkit |

Related Information

in System Console in Quartus Prime Pro Edition User Guide: Debug Tools
External Memory Interfaces IP User Guide: Agilex 3 FPGAs and SoCs
External Memory Interfaces IP User Guide: Agilex 5 FPGAs and SoCs
External Memory Interfaces Agilex 7 M-Series FPGA IP User Guide
External Memory Interfaces Agilex 7 F-Series and I-Series FPGA IP User Guide
External Memory Interfaces Arria 10 FPGA IP User Guide
External Memory Interfaces Cyclone 10 GX FPGA IP User Guide
External Memory Interfaces Stratix 10 FPGA IP User Guide
Ethernet Toolkit User Guide
GTS AXI Streaming IP for PCI Express* User Guide
F-Tile Avalon Streaming IP for PCI Express* User Guide
P-Tile Avalon Memory Mapped IP for PCI Express* User Guide
P-Tile Avalon Streaming IP for PCI Express* User Guide
R-Tile Avalon Streaming IP for PCI Express* User Guide
Multi Channel DMA FPGA IP for PCI Express* User Guide
Scalable Switch FPGA IP for PCI Express* User Guide
Serial Lite IV Agilex 7 FPGA IP Design Example User Guide
Serial Lite IV Stratix 10 FPGA IP Design Example User Guide
Arria 10 Transceiver PHY User Guide
Cyclone 10 GX Transceiver PHY User Guide
E-Tile Transceiver PHY User Guide
F-Tile Architecture and PMA and FEC Direct PHY IP User Guide
GTS Transceiver PHY User Guide: Agilex 5 FPGAs and SoCs
L- and H-Tile Transceiver PHY User Guide

3. FPGA Tools Comparison

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Ethernet Link Inspector User Guide for Stratix 10 Devices
Stratix 10 Configuration User Guide

3.3.13.4.1. Transceiver Toolkit

The Vivado software uses IBERT IP along with the serial I/O analyzer tool to evaluate and monitor the transceivers in UltraScale devices. In the Quartus Prime Pro Edition software, the Transceiver Toolkit allows you to check and improve signal integrity of high-speed serial links in Altera FPGAs.

Table 34. Transceiver Toolkit Features and Usage

Related Information

in System Console in Quartus Prime Pro Edition User Guide: Debug Tools

3.3.13.4.2. EMIF Debug Toolkit

In the Vivado software, the Memory Calibration Debug tool allows you to debug calibration or data errors in UltraScale memory interfaces. In the Quartus Prime Pro Edition software, the External Memory Interface (EMIF) Debug Toolkit allows you to run custom traffic patterns, diagnose and debug calibration problems, and produce margining reports for the external memory interface.

Table 35. EMIF Debug Toolkit Features and Usage

| Features | Typical Usage | |--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|-------------------------------------------------------------------------------------------| | • Tcl-based graphical user interface. • Provides access to memory calibration data gathered by the Nios II sequencer, via a JTAG connection. • Allows you to mask ranks for calibration and to request recalibration of the interface. • The Driver Margining feature of the toolkit allows you to measure margins on the memory interface using a driver with arbitrary traffic patterns. • The EMIF Toolkit can communicate with several different memory interfaces on the same device, but only one at a time. | You want to debug hardware failures by accessing information gathered during calibration. |

Related Information

in System Console in Quartus Prime Pro Edition User Guide: Debug Tools

3.3.13.5. Remote Debugging

You can perform remote debugging of a system with the Quartus Prime software via the System Console. This feature allows you to debug equipment deployed in the field through an existing TCP/IP connection.

For information about setting up a Nios II system with the System Console to perform remote debugging, refer to Application Note 624.

Related Information

Analyzing and Debugging Designs with System Console in Quartus Prime Pro Edition User Guide: Debug Tools
Application Note 624: Debugging with System Console over TCP/IP

3.3.13.6. Other Altera FPGA Debugging Tools

These Altera FPGA tools do not have a Xilinx tools to compare with.

Signal Probe

Table 36. Signal Probe Features and Usage

| Features | Typical Usage | |-------------------------------------------------------------------------------------------------------------------|--------------------------------------------------------------------------------------------------------------------------------------------------------| | Incrementally routes internal signals to I/O pins while preserving results from the last place-and-routed design. | You have spare I/O pins and you want to check the operation of a small set of control pins using either an external logic analyzer or an oscilloscope. |

Logic Analyzer Interface

Table 37. Logic Analyzer Interface Features and Usage

In-System Memory Content Editor

Table 38. In-System Memory Content Editor Features and Usage

| Features | Typical Usage | |-------------------------------------------------|----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | Displays and allows you to edit on-chip memory. | You want to view and edit the contents of on-chip memory that is not connected to a Nios II processor. You can also use the tool when you do not want to have a Nios II debug core in your system. |

Related Information

Quick Design Verification with Signal Probe in Quartus Prime Pro Edition User Guide: Debug Tools
In-System Debugging Using External Logic Analyzers in Quartus Prime Pro Edition User Guide: Debug Tools
In-System Modification of Memory and Constants in Quartus Prime Pro Edition User Guide: Debug Tools

3.3.14. View Netlist

Similar to the Netlist Window and Schematic Window features available in the Vivado software to generate logical or physical hierarchy, the Quartus Prime Pro Edition RTL Viewer and Technology Map Viewer provide powerful ways to view initial and fully mapped synthesis results during the debugging, optimization, and constraint entry processes.

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Table 39. View Netlist Methods Comparison

| GUI Feature | AMD Xilinx Vivado Software | Quartus Prime Pro Edition Software | |---------------|---------------------------------------------------------------------------------------------|------------------------------------------------------------------------------------------------------------------------------------------| | View Netlist | Schematic Window (Elaborated) Schematic Window (Synthesized) Schematic Window (Implemented) | RTL Viewer (Post Synthesis) Technology Map Viewer (Post-Mapping) Technology Map Viewer (Post-Fitting) Fast Forward Viewer (Post-Fitting) |

The Technology Map Viewer can display netlists at different fitter snapshots of the design by using Snapshot Viewer.

Related Information

Snapshot Viewer on page 47

3.3.14.1. RTL Viewer

To run the RTL Viewer for an Quartus Prime Pro Edition project:

Click Processing ➤ Start ➤ Start Analysis & Elaboration to generate a RTL netlist
To open the RTL Viewer, click Tools ➤ Netlist Viewers (RTL Viewer) .

Alternatively, you can perform a full compilation on any Quartus Prime Pro Edition flow that includes the initial Analysis and Elaboration stage.

Related Information

RTL Viewer Overview in Quartus Prime Pro Edition User Guide: Design Optimization

3.3.14.2. Technology Map Viewer

The Technology Map Viewer is a detached window that provides a graphical representation of the schematic. To run the Technology Map Viewer for an Quartus Prime Pro Edition project:

Click Processing ➤ Start ➤ Start Analysis & Synthesis to synthesize and map the design to the target technology.
Click Tools ➤ Netlist Viewers ➤ Technology Map Viewer (Post-Mapping) to view the post mapping netlist.
Click Processing ➤ Start ➤ Start Fitter .

After completing the Fitter stage, the Technology Map Viewer displays how the Fitter modified the netlist as a result of optimizations. After completing the Timing Analysis stage, you can locate timing paths from the Timing Analyzer report in the Technology Map Viewer.

Click Tools ➤ Netlist Viewers ➤ Technology Map Viewer (Post-Fitting) to view the post fitting netlist.

To find cells by name, click Edit ➤ Find , type the cell name, and click List .

Related Information

Technology Map Viewer Overview in Quartus Prime Pro Edition User Guide: Design Optimization

3.3.15. Design Optimization

The Quartus Prime software offers advanced netlist optimization options that allow you to optimize a design beyond the standard Quartus Prime Pro Edition compilation flow.

Table 40. Design Optimization Tools Comparison

| GUI Feature | AMD Xilinx Vivado Software | Quartus Prime Pro Edition Software | |---------------------|------------------------------|--------------------------------------| | Design Optimization | - | Hyper-Aware Design Flow (12) | | Design Optimization | Physical Optimization | Physical Synthesis Optimization |

3.3.15.1. Hyper-Aware Design Flow

Use the Hyper-Aware design flow to shorten design cycles and optimize performance for designs targeting Agilex 7 and Stratix 10 devices. The Hyper-Aware design flow combines automated register retiming (Hyper-Retiming), with implementation of targeted timing closure recommendations (Fast Forward compilation), to maximize use of Hyper-Registers and drive the highest performance for Agilex 7 and Stratix 10 designs.

Fast Forward Compilation operates on the post-retimed netlist and outputs Fast Forward Timing Closure Recommendations that show the current and potential performance achievable for each clock domain after applying Hyper-Retiming, HyperPipelining, and Hyper-Optimization steps.

Related Information

Optimize Critical Chains in Quartus Prime Pro Edition User Guide: Design Optimization
Fast Forward Compilation Flow in Quartus Prime Pro Edition User Guide: Design Compilation

3.3.15.2. Physical Synthesis Optimization

The Vivado software applies timing-driven Physical Optimization in the post-place and reroute designs. The Quartus Prime Pro Edition software performs Physical synthesis optimizations to improve performance by performing combinational and sequential optimizations and register duplication. The optimizations are on by default.

Quartus Prime Pro Edition software also has high-level optimization settings for the Compiler that control the settings used throughout design compilation. By default, the high-level optimization is set to balanced, but designs can be optimized for performance, area, routability, and power. You can find these settings on the Optimization tab under Settings ➤ Compiler Settings .

3.3.15.3. Optimization Modes

By default, Quartus Prime Pro Edition uses a balanced optimization strategy that respects timing constraints. It can use other high-level strategies to optimize for performance, area, routability, power, or compile time. These settings affect synthesis and fitter.

(12) Hyper-Aware Design Flow available only for Stratix 10 devices.

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Related Information

Optimization Modes in Quartus Prime Pro Edition User Guide: Design Compilation

3.3.15.4. Fractal Synthesis

Fractal Synthesis optimizations can be used for deep-learning accelerators and other high-throughput, arithmetic-intensive designs that exceed all available DSP resources. For such designs, fractal synthesis optimization can achieve 20-45% area reduction.

Fractal synthesis uses techniques such as multiplier regularization and retiming which are ideal for operations like calculating dot-products, and continuous arithmetic packing to pack adder trees, multipliers into logic blocks optimally sized to fit Altera FPGA LABs.

Related Information

Fractal Synthesis Optimization in Quartus Prime Pro Edition User Guide: Design Compilation

3.3.16. Techniques to Improve Productivity

Table 41. Techniques to Improve Productivity Comparison

| GUI Feature | AMD Xilinx Vivado Software | Quartus Prime Pro Edition Software | |------------------------------------|------------------------------|--------------------------------------| | Techniques to improve productivity | Incremental Compile | Block-Based Design Flows | | Techniques to improve productivity | Hierarchical Design | | | Techniques to improve productivity | - | Design Space Explorer II (DSE) | | Techniques to improve productivity | Design Rule Checking | Design Assistant | | Techniques to improve productivity | Intermediate Design | Snapshot Viewer |

3.3.16.1. Fast Preservation

In Xilinx Vivado designs, the Incremental Compile design flow speeds up place and route runtime.

In Quartus Prime Pro Edition, enabling the Fast Preserve option on the Incremental Compile tab under Assignment ➤ Settings ➤ Compiler Settings specifies that the Compiler can simplify a final snapshot of a partition to only its interface logic.

To use Fast Preservation effectively, ensure that your designs are floorplanned and partitioned and have a well-separated periphery.

Related Information

AN 899: Reducing Compile Time with Fast Preservation

3.3.16.2. Engineering Change Order (ECO) Flow

The Xilinx Vivado Engineering Change Order (ECO) flow allows you to modify a postimplementation design and generate reports and programming files.

Quartus Prime Pro Edition has an ECO Compilation Flow that supports last-minute, targeted design changes including changing routing connections; changing IOPLL frequencies by modifying the input reference clock frequency; modifying LUT masks; I/O pin settings such as slew rate, current strength, and delay chain; creating, removing, or placing individual nodes; and inserting wireluts.

Related Information

Using the ECO Compilation Flow in Quartus Prime Pro Edition User Guide: Design Optimization

3.3.16.3. Block-Based Design Flow

In the Vivado software, the Hierarchical Design flow allows you to partition a design into smaller modules that you process independently. These flows are based on the ability to implement a partitioned module out-of-context (OOC) from the rest of the design. A similar feature in Quartus Prime Pro Edition software is the Block-Based Design Flow, which supports preservation and reuse of design blocks in one or more projects.

The Block-Based Design Flow allows you to reuse synthesized or final design blocks within the same project, or export the block to other projects. Reusable design blocks can include device core or periphery resources.

You can define a logical design partition in a project, and then empty, preserve, or export the contents of that design partition after compilation. The Quartus Prime Pro Edition software supports the following block-based design flows:

Incremental Block-Based Compilation-preserve or empty a core design partition within a project. This flow works only with core resources, and requires no additional files or floorplanning. You can empty the partition, or preserve it at synthesis, placement, or final compilation stages.
Design Block Reuse-export a core or periphery design partition and reuse it in another project. Core partition reuse preserves the placement and routing of timing-critical modules with specific optimized functionality or algorithms, such as modules for encryption, encoding, image processing, or other functions. Periphery partition reuse preserves the placement and routing of the periphery.

Table 42. Block-Based Design Flows Comparison

| AMD Xilinx Hierarchical Design Flows | Quartus Prime Pro Edition Block- Based Design Flows | Description | |----------------------------------------|-------------------------------------------------------|-------------------------------------------------------------------------------------------------------------| | Bottom-Up Reuse | Design Block Reuse | Build a verified module (such as a piece of IP) which is placed, routed and you can reuse in other designs. | | Top-Down Reuse | Periphery Reuse | Build a verified top-level design with details about the pinout, floorplan and timing requirements. |

For more information about design planning and different design approaches, refer to Quartus Prime Pro Edition User Guide: Block-Based Design .

Related Information

Quartus Prime Pro Edition User Guide: Block Based Design

3.3.16.4. Design Assistant

Xilinx Vivado has a Report Design Rule Checking (DRC) feature that checks design rules on a synthesized or implemented design.

The Design Assistant feature in Quartus similarly performs targeted rule checks and guidance at each stage of compilation, reducing the total number of design iterations.

Design Assistant rule categories include block-based design and partial reconfiguration, clock domain crossings, clocks, floorplanning, linting, platform designer interface, project, reset domain crossing, reset, and timing closure.

Design Assistant identifies rule violations and provides recommendations to help resolve these issues.

Related Information

Design Assistant Design Rule Checking in Quartus Prime Pro Edition User Guide: Design Recommendations
Design Assistant Rules List in Quartus Prime Pro Edition Help

3.3.16.5. Snapshot Viewer

Use the Snapshot Viewer to evaluate your design by analyzing the results of compilation snapshots before you run the next compilation stage or before you run a full compilation.

From the Flow Navigator in Snapshot Viewer, you can run timing closure and design after the Fitter Plan, Place, Route, or Finalize stages.

3.3.16.6. Design Space Explorer II

Altera's Design Space Explorer II (DSE II) tool allows you to find optimal project settings for resource, performance, or power optimization goals.

Design Space Explorer II (DSE II) processes a design using combinations of settings and constraints, and reports the best combination of settings and constraints for the design. You can also take advantage of the DSE II parallelization abilities to compile on multiple computers.

If a design is close to meeting timing or area requirements, you can try different seeds with the DSE II, and find one seed that meets timing or area requirements.

Related Information

Optimize Settings with Design Space Explorer II in Quartus Prime Pro Edition User Guide: Design Optimization

3.3.17. Partial Reconfiguration

Partial Reconfiguration (PR) allows for the dynamic reprogramming of a portion of the FPGA while the rest of the design continues to function.

With Partial Reconfiguration, you can dynamically reprogramming part of the FPGA device while the rest of the design continues to function.

You can define multiple personas for a particular region in the design, without impacting operation in areas outside this region. This methodology is effective in systems where multiple functions time-share the same FPGA device resources. PR configuration can be performed either with an internal host or through an external host using dedicated PR pins on the device. It provides the following advancements to a flat design:

Allows run-time design reconfiguration
Increases scalability of the design
Reduces system down-time
Supports dynamic time-multiplexing functions in the design
Lowers cost and power consumption through efficient use of board space

Related Information

Quartus Prime Pro Edition User Guide: Partial Reconfiguration
AN 797: Partially Reconfiguring a Design: on Arria 10 GX FPGA Development Board
AN 825: Partially Reconfiguring a Design: on Stratix 10 GX FPGA Development Board
AN 869: Partially Reconfiguring a Design: on Cyclone 10 GX FPGA Development Board
AN 953: Partially Reconfiguring a Design: on an Agilex F-Series FPGA Development Board

3.3.18. Cross-Probing in the Quartus Prime Pro Edition Software

Cross-probing is the ability to select design elements from one tool and locate them in another tool. The integration between features and tools in the Quartus Prime Pro Edition software results in a design environment that provides seamless cross-probing abilities.

For example, you can locate design elements from the RTL Viewer to the Assignment Editor. This eliminates the search time for node names and pin names when applying design constraints in the Assignment Editor. To locate design elements, use the right mouse click button.

3.4. Additional Quartus Prime Pro Edition Features

In addition to providing the standard set of tools required in any FPGA design flow, the Quartus Prime Pro Edition software includes additional features and tools to assist you with achieving your desired design requirements.

Related Information

Quartus Prime Pro Edition User Guide: Scripting

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3.4.1. Scripting with Tcl in the Quartus Prime Pro Edition Software

The Quartus Prime Pro Edition GUI provides an easy way to access all features and commands that the software offers. However, as designs grow in resource utilization and complexity, the need to automate common tasks and streamline the entire FPGA design flow becomes a requirement.

The Quartus Prime Pro Edition software provides support for Tcl to help facilitate project assignments, compilation, and constraints.

The Quartus Prime Pro Edition software contains Tcl application program interface (API) functions that you can use to automate a variety of common tasks, such as making assignments, compiling designs, analyzing timing, and controlling simulation. You can run your Tcl scripts in the following ways:

Running Scripts from the DOS or UNIX Prompt on page 49

Running Scripts in Batch Mode from a Shell on page 49

Running Tcl Commands Directly from the Command Line on page 49

Running Tcl Commands Interactively from the Shell on page 50

The Quartus Prime Tcl Console Window on page 50

3.4.1.1. Running Scripts from the DOS or UNIX Prompt

The following command runs the Quartus Prime Tcl shell and uses the Tcl file specified by the -t option as the input Tcl script:

quartus_sh -t <script_name>.tcl

The Quartus Prime Tcl interpreter reads and executes the Tcl commands in the Tcl script file and then exits back to the command-line prompt.

3.4.1.2. Running Scripts in Batch Mode from a Shell

You can run Tcl scripts in a Tcl shell by typing:

source <script_name>.tcl

3.4.1.3. Running Tcl Commands Directly from the Command Line

You can use the --tcl_eval option to directly evaluate the rest of the command line arguments as one or more Tcl commands. If there are two or more Tcl commands, separate them with semicolons.

1. For example, typing:

quartus_sh --tcl_eval puts Hello\; puts World Results in the following output: Hello World

The Tcl evaluate option allows external scripting programs (such as make , perl , and sh ) to access information from the Quartus Prime Pro Edition software. You can use these programs to obtain device family information for a targeted part.

The --tcl_eval option also provides Tcl help information directly from the command-line prompt.

3.4.1.4. Running Tcl Commands Interactively from the Shell

Using the -s or --shell switch option starts an interactive Tcl shell session, replacing the normal command line prompt with tcl , as shown in the following example:

1. In a console, type:

quartus_sh -s

When entering the console, you get the welcome message:

Info: ******************************************************************* Info: Running Quartus Prime Shell Info: Version 17.1.0 Internal Build 167 08/21/2017 SJ Pro Edition Info: Copyright (C) 2017 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and its AMPP partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details. Info: Processing started: Thu Aug 31 12:50:32 2017 Info: ******************************************************************* Info: The Quartus Prime Shell supports all TCL commands in addition Info: to Quartus Prime Tcl commands. All unrecognized commands are Info: assumed to be external and are run using Tcl's "exec" Info: command. Info: - Type "exit" to exit. Info: - Type "help" to view a list of Quartus Prime Tcl packages. Info: - Type "help <package name>" to view a list of Tcl commands Info: available for the specified Quartus Prime Tcl package. Info: - Type "help -tcl" to get an overview on Quartus Prime Tcl usages. Info: ******************************************************************* tcl>

Enter any Tcl command.

The Quartus Prime Tcl interpreter directly evaluates everything that you type in the Tcl shell.

The Tcl shell includes a history list of previously-entered commands.

3.4.1.5. The Quartus Prime Tcl Console Window

You can execute Tcl commands directly in the Quartus Prime Tcl Console window. To open the Tcl Console window, click View ➤ Tcl Console .

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Example 1. Tcl Script

This example uses design files from the fir_filter tutorial in tutorial design in the <quartus-installation-directory>/qdesigns directory. The script performs

these tasks:

Opens the fir_filter project, if it exists. If the project does not exist, the script creates the project.
Sets the project to target an Stratix 10 1SG280HU2F50E2VG device.
Assigns the clk pin to the physical pin AW10.
Compiles the project.

# This Tcl file works with quartus_sh.exe # This Tcl file will compile the Quartus Prime tutorial fir_filter design # set the project_name to fir_filter # set compiler setting to filtref set project_name fir_filter set csf_name filtref # Create a new project and open it # Project_name is project name if {![project_exists $project_name]} { project_new -family Stratix10 -part 1SG280HU2F50E2VG -cmp $csf_name $project_name ; } else { project_open -cmp $csf_name $project_name; } # assign pin clk to pin location AW10 set_location_assignment -to clk PIN_AW10 # The project is compiled here package require ::quartus::flow execute_flow -compile project_close

Related Information

Quartus Prime Pro Edition User Guide: Scripting

4. AMD Xilinx to Altera FPGA Design Conversion

To successfully convert a AMD Xilinx-targeted design for use in an Altera FPGA device, you must consider the following aspects:

Replacing AMD Xilinx primitives with Altera FPGA primitives, IP cores, or constraints.
Replacing Vivado IP Catalog modules with IP cores generated with the Altera FPGA IP Catalog.
Expressing timing, device, and placement constraints found in the AMD Xilinx design with their counterpart in the Quartus Prime software.
If applicable, setting up the simulation environment.

Related Information

Project Creation on page 20

4.1. Replacing AMD Xilinx Primitives

When migrating a design, you must convert common AMD Xilinx primitives to the Altera FPGA equivalents. Primitives are the basic building blocks of a AMD Xilinx design. Primitives perform dedicated functions in the device, and implement standards for I/O pins in AMD Xilinx devices. Primitives names are standard.

The following table lists common AMD Xilinx primitives and describes the equivalent Altera FPGA design element.

Table 43. Common AMD Xilinx Device-Specific Primitives and Altera FPGA Equivalents

| AMD Xilinx Primitive | Description | Altera FPGA Equivalent | Conversion Method | |----------------------------------------|-----------------------------------------------|--------------------------------------------------------------|---------------------------| | IBUF | Single Input Buffer | wire/signal Assignment | HDL | | OBUF | Single Output Buffer | wire/signal Assignment | HDL | | BUFG | Global Clock Buffer | wire/signal and Global Signal Assignment | HDL and Assignment Editor | | IBUFG_< selectable I/O standard > (13) | Input Global Buffer with selectable interface | wire/signal, I/O Standard, and Global Signal Assignment (14) | HDL and Assignment Editor | | continued... | continued... | continued... | continued... |

(13) The attributes of the <selectable I/O standard> are device-specific. For specific I/O standard information, refer to the AMD Xilinx device's data sheet.
(14) For differential I/O buffer, you can assign differential I/O standard to the desired differential I/O signal. The Quartus Prime software automatically creates a new signal, signal_name(n) , that is opposite in phase with the desired signal.

*Other names and brands may be claimed as the property of others.

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| AMD Xilinx Primitive | Description | Altera FPGA Equivalent | Conversion Method | |----------------------------------------|------------------------------------------------|----------------------------------------------|---------------------| | IBUF_< selectable I/O standard > (13) | Input buffer with selectable interface | wire/signal and I/O Standard Assignment (14) | | | IOBUF_< selectable I/O standard > (13) | Bidirectional buffer with selectable interface | wire/signal and I/O Standard Assignment (14) | | | OBUFG_< selectable I/O standard > (13) | Output Global Buffer with selectable interface | wire/signal and I/O Standard Assignment (14) | | | OBUF_< selectable I/O standard > (13) | Output buffer with selectable interface | wire/signal and I/O Standard Assignment (14) | | | IBUFDS, OBUFDS | Differential I/O Buffer | wire/signal and I/O Standard Assignment (14) | | | SRL16 | 16-bit Shift Register | AUTO_SHIFT_REGISTER_RE COGNITION | Assignment Editor |

Related Information

Primitives in Quartus Prime Pro Edition Help

4.1.1. Converting I/O Buffers

The Quartus Prime Pro Edition Compiler inserts input, output, or bidirectional buffers automatically.

To convert a design's buffers to the Quartus Prime Pro Edition software:

Remove all buffer primitives from the AMD Xilinx design in the HDL code.
Replace the primitives with wire or signal assignments in the HDL code.
In the Assignment Editor, perform assignments depending on the type of buffer:

Type of Buffer

Assignment to use

Buffers with selectable I/O standard

I/O Standard

Global buffers

Global Signal

Global buffer with I/O Standard

I/O Standard

4.1.1.1. Example of Converting I/O Buffer

In this example, the clk , a , and b inputs are global signals, and the a and b inputs use the IBUFG I/O Standard.

Example 2. Converting BUFG , IBUFG , and OBUF in Verilog HDL.

Original Verilog HDL Code in the Vivado Software

module Top (a, b, c, clk); input a, b, clk; output c; reg c_buf; wire a_buf, b_buf, clk_buf; BUFG inst1 (.O (clk_buf), .I (clk)); IBUFG #("FALSE", "SSTL12") inst2 (.O (a_buf), .I (a)); IBUFG #("FALSE", "SSTL18_I") inst3 (.O (b_buf), .I (b));

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OBUF inst4 (.O (c), .I (c_buf)); always @ (posedge clk_buf) c_buf <= a_buf & b_buf; endmodule

Converted Verilog HDL Code in the Quartus Prime Pro Edition Software

module Top (a, b, c, clk); input a, b, clk; output c; reg c_buf; wire a_buf, b_buf, clk_buf; assign clk_buf = clk; assign a_buf = a; assign b_buf = b; assign c = c_buf; always @ (posedge clk_buf) c_buf <= a_buf & b_buf; endmodule

Example 3. Converting BUFG , IBUFG , and OBUF in VHDL.

Original VHDL Code in the Vivado Software

LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY buf_top IS PORT( a, b : IN STD_ULOGIC; clk : IN STD_ULOGIC; c : OUT STD_ULOGIC); END buf_top; ARCHITECTURE Behave OF buf_top IS SIGNAL a_buf, b_buf, c_buf, clk_buf : STD_ULOGIC; COMPONENT BUFG PORT (O : OUT STD_ULOGIC; I : IN STD_ULOGIC); END COMPONENT; COMPONENT IBUFG generic(IBUF_LOW_PWR : boolean := FALSE; IOSTANDARD : String := "DEFAULT"); PORT (O : OUT STD_ULOGIC; I : IN STD_ULOGIC); END COMPONENT; COMPONENT OBUF PORT (O : OUT STD_ULOGIC; I : IN STD_ULOGIC); END COMPONENT; BEGIN inst1 : BUFG PORT MAP (O => clk_buf, I => clk); inst2 : IBUFG generic map( IBUF_LOW_PWR => FALSE, IOSTANDARD => "SSTL12") PORT MAP (O => a_buf,I => a); inst3 : IBUFG generic map( IBUF_LOW_PWR => FALSE, IOSTANDARD => "SSTL18_I") PORT MAP (O => b_buf, I => b); inst4 : OBUF PORT MAP (O => c, I => c_buf); PROCESS(clk_buf) BEGIN IF (clk_buf'event and clk_buf = '1') THEN c_buf <= a_buf AND b_buf; END IF; END PROCESS; END Behave;

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Converted VHDL Code in the Quartus Prime Pro Edition Software

LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY Top IS PORT( a, b: IN STD_ULOGIC; clk: IN STD_ULOGIC; c: OUT STD_ULOGIC); END Top; ARCHITECTURE Behave OF Top IS SIGNAL a_buf, b_buf, c_buf, clk_buf: STD_ULOGIC; BEGIN PROCESS (a, b, c_buf, clk) BEGIN clk_buf <= clk; a_buf <= a; b_buf <= b; c <= c_buf; END PROCESS; PROCESS(clk_buf) BEGIN IF (clk_buf'event and clk_buf = '1') THEN c_buf <= a_buf AND b_buf; END IF; END PROCESS; END Behave;

To set the ports with specific assignments in the Quartus Prime Pro Edition software, use the Assignment Editor.

Figure 11. Global Signal and I/O Standard Assignments Using the Assignment Editor

In the figure, inputs a , b , and clk are assigned as global signals, with clk as the global clock. Input ports a and b are assigned with specific I/O standards, while other ports are automatically assigned with the device-specific default I/O standard.

4.1.2. Changing Default I/O Standard for Pins

The default I/O standard for pins on the target device in the Quartus Prime Pro Edition software is device-specific. To change the default I/O standard:

Click Assignments ➤ Device .
On the Device dialog box, click Device and Pin Options .
In the Category list, select Voltage and then select the desired I/O standard.

4.1.3. Converting Registers

This table shows the nearest Altera equivalent to some common Xilinx storage primitives.

Table 44. Nearest Altera Equivalent for Common Xilinx Storage Primitives

| Xilinx Primitives | Description | Nearest Altera Equivalent | |---------------------|-------------------------------------------------------------|-----------------------------| | FDCE | D Flip-Flop with Clock Enable and Asynchronous Clear | dffe | | FDPE | D Flip-Flop with Clock Enable and Asynchronous Preset | dffe | | FDRE | D Flip-Flop with Clock Enable and Synchronous Reset | dffeas | | FDSE | D Flip-Flop with Clock Enable and Synchronous Set | dffeas | | LDCE | Transparent Latch with Clock Enable and Asynchronous Clear | dlatch | | LDPE | Transparent Latch with Clock Enable and Asynchronous Preset | dlatch |

Related Information

Storage Primitives in Quartus Prime Pro Edition Help

4.2. Converting IP Cores

This section describes how to convert IPs generated using the AMD Xilinx IP Catalog to IP cores generated with the Quartus Prime Pro Edition IP Catalog.

4.2.1. Converting Memory Blocks

To convert AMD Xilinx memory blocks to Altera FPGA memory blocks, you must consider the embedded memory blocks in the target device, address the differences between memories in Altera FPGA and AMD Xilinx devices, and perform port mapping.

The AMD Xilinx Block Memory Generator defines the following types of memory blocks:

Single Port RAM
Simple Dual Port RAM
True Dual Port RAM
Single Port ROM
Dual Port ROM

AN 307: Altera ® FPGA Design Flow for AMD* Xilinx* Users

Replacing memory blocks is not a trivial task. Depending on the RAM mode, you might encounter some functionality mismatch when converting your design from a AMD Xilinx device to an Altera device.

For information about memory blocks present in Altera FPGA devices, refer to the Embedded Memory User Guide for each device.

Related Information

Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2PORT) User Guide
Stratix 10 Embedded Memory User Guide
Agilex 7 Embedded Memory User Guide

4.2.1.1. Embedded Memory Blocks

The following table lists the memory blocks that Altera FPGA devices support:

Table 45. Embedded Memory Blocks in Altera FPGA Devices

| Device | Types of Memory Blocks | |------------|--------------------------------------| | Agilex 5 | MLAB blocks M20K blocks | | Agilex 7 | eSRAM blocks MLAB blocks M20K blocks | | Arria 10 | MLAB blocks M20K blocks | | Stratix 10 | eSRAM blocks MLAB blocks M20K blocks |

For information about memory features and memory specification, refer to the appropriate Embedded Memory Blocks chapter for the target device.

Related Information

Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2PORT) User Guide
Stratix 10 Embedded Memory User Guide
Agilex 7 Embedded Memory User Guide

4.2.1.2. Differences Between AMD Xilinx Memory and Altera FPGA Memory

Consider the differences between AMD Xilinx memory and Altera FPGA memory features and behavior:

Memory Mode on page 58

Clocking Mode on page 58

Write and Read Operation Triggering on page 59

Read-During-Write Operation at the Same Address on page 59

Error Correction Code (ECC) on page 60 Byte Enable on page 62 Address Clock Enable on page 63 Parity Bit Support on page 63 Memory Initialization on page 63 Output Synchronous Set/Reset on page 64

4.2.1.2.1. Memory Mode

AMD Xilinx memory and Altera FPGA memory support single-port RAM, simple dualport RAM, true dual-port RAM, single-port ROM, and dual-port ROM.

In addition, Altera FPGA supports simple quad-port RAM, which allows user to perform two read and two write operations to different locations in a single clocking mode. AMD Xilinx memory does not have a built-in simple quad-port RAM.

Related Information

Memory Port Mapping on page 65
Inferring Memory Functions from HDL Code in Quartus Prime Pro Edition User Guide: Design Recommendations

4.2.1.2.2. Clocking Mode

In Altera FPGAs, the clock mode depend on which embedded memory block you select:

Table 46. Clocking Mode

| Altera FPGA Clocking Mode | Description | Comment | |-----------------------------|-----------------------------------------------------------------|-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | Single | All ports share the common clock. | | | Input/output | A separate clock is available for input ports and output ports. | AMD Xilinx memories do not differentiate these two clocking modes. However, the clocking mode behavior with simple dual-port RAM can be identical to Altera FPGA clocking mode in the following situations: | | Read/write | A separate clock is available for read ports and write ports. | AMD Xilinx memories do not differentiate these two clocking modes. However, the clocking mode behavior with simple dual-port RAM can be identical to Altera FPGA clocking mode in the following situations: |

For more information about supported clocking modes, refer to the Stratix 10 Embedded Memory User Guide.

Related Information

Clocking Modes and Clock Enable in Embedded Memory (RAM: 1-PORT, RAM: 2PORT, ROM: 1-PORT, and ROM: 2-PORT) User Guide
Stratix 10 Embedded Memory Clocking Modes in Stratix 10 Embedded Memory User Guide

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Agilex 7 Embedded Memory Clocking Modes in Agilex 7 Embedded Memory User Guide

4.2.1.2.3. Write and Read Operation Triggering

Ensure to resolve potential write contentions external to the RAM, because writing to the same address location at both ports results in unknown data storage at that location. Therefore, knowing when the write operation was triggered is crucial.

For Arria 10 devices, the write operation in Altera FPGA memory can occur at either falling clock edges or rising clock edges, depending on the type of embedded memory block. For Agilex 7 and Stratix 10 devices, the write operation is triggered at rising clock edges.

To avoid delta delay, do not trigger control signals together with clock signals.

Related Information

Write and Read Operations Triggering in Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2-PORT) User Guide
Stratix 10 Embedded Memory Design Considerations in Stratix 10 Embedded Memory User Guide
Agilex 7 Embedded Memory Design Considerations in Agilex 7 Embedded Memory User Guide

4.2.1.2.4. Read-During-Write Operation at the Same Address

There are two types of read-during-write operations: same-port operations and mixed-port operations.

Figure 12. Read-During-Write Data Flow

The same-port read-during-write mode applies to either:

a single-port RAM
the same port of a true-dual port RAM
the same port a of simple quad-port RAM

Mixed-port read-during-write mode applies to a RAM in:

simple-dual port
true-dual port
simple-quad port mode

that has one port reading and the other port writing to the same address location with the same clock.

Altera FPGA RAM and AMD Xilinx RAM support both read-during-write port modes. However, they have different output options. These options vary depending on the operation mode and type of embedded memory block or device that you select.

Altera FPGA RAMs support configurations with output options of NEW_DATA (flowthrough), OLD_DATA , DONT_CARE , or NEW_A_OLD_B . AMD Xilinx RAMs support configurations with output options READ_FIRST , WRITE_FIRST , or NO_CHANGE .

Table 47. Output Options in AMD Xilinx RAM and Altera FPGA RAM for Read-DuringWrite Operation

| Description | Output after Read- During-Write operation | Types of RAM Output | Types of RAM Output | |---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|---------------------------------------------|-----------------------|-----------------------| | | Output after Read- During-Write operation | AMD Xilinx | Altera FPGA | | Output reflects the new data at that address. | New data | WRITE_FIRST | NEW_DATA | | Outputs reflect the old data at that address before the new data is written into memory. | Old data | READ_FIRST | OLD_DATA | | Outputs reflect the previous read data and remains unaffected by the write operation. | Unaffected | NO_CHANGE | Not supported (15) | | Read-during-write writes new data into memory, and the output displays unknown values. | Unknown | Not supported | DONT_CARE (16) | | For simple quad port, the read-during-write operation behaves differently for each port: • In port A, the operation writes new data into memory and displays new data at output • In port B, the operation writes new data but displays old data. | Port A: New data Port B: Old data | Not supported | NEW_A_OLD_B |

In Altera FPGA RAMs, the output choices depend on the operation mode and the type of embedded memory block. For information about output choices for same-port and mixed-port read-during-write modes, refer to the Embedded Memory Blocks chapter in the corresponding device handbook.

4.2.1.2.5. Error Correction Code (ECC)

AMD Xilinx and Altera FPGA RAMs use Error Correction Code (ECC) to detect errors in the memory array, and present the corrected single-bit error data on the output.

(15) To implement NO_CHANGE behavior, you must add additional logic. Use the write_enable signal and compare the write and read addresses to track the operation.

(16) You can choose DONT_CARE for a read-during-write operation if the output is not crucial to your design.

Table 48. Comparison of ECC Support and Status Output Signals for Altera FPGA and AMD Xilinx RAMs

| | Altera FPGA | AMD Xilinx | |---------------|-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|-------------------------------------------------------------------------------------| | ECC support | • Built-in support for eSRAM and M20K type of Embedded Memory Block selected in simple dual-port mode. • Altera FPGA also provides a dedicated soft IP ECC core that is flexibly implemented in your design, and is not restricted by the type of memory block used. For more information about the ECC IP core, refer to the Altera FPGA Integer Arithmetic IP Cores User Guide. | For UltraScale+ and 7-series devices in simple dual-port RAM. | | Status Signal | Indicates the status of the M20K block using a three-bit status flag eccstatus[1..0] | Indicates the status of the data read using two status outputs: • SBITERR • DBITERR |

Note:

Altera FPGA does not support using ECC with the byte-enable or coherent read features.

Related Information

ALTECC (Error Correction Code: Encoder/Decoder) IP Core in Altera FPGA Integer Arithmetic IP Cores User Guide

ECC Parity Flip

The ECC parity flip feature is available only on Agilex 7 and Stratix 10 devices.

The ECC parity flip feature dynamically flips the parity value generated in the encoder of M20K blocks to observe the ECC behavior through simulationin both simulation and hardware.

When the ECC Encoder Bypass ( eccencbypass ) port is high, the built-in ECC encoder values are XOR-ed with the 8 parity bits through the parity ports to generate a new set of encoder value. When the ECC Encoder Bypass port is low, the encoder generates the parity bits according to the data input during a write process.

The following table shows an example to construct an 8-bit data width for the parity port.

Table 49. Example of Setting the 8-Bit Parity Ports

| Parity Bit Sequence | ECC Feature | Is the ECC Decoder able to Recognize and Correct the Data Bit? | |-----------------------|-------------------------------------------------|------------------------------------------------------------------| | 00000001 | Single-error correction | Yes | | 00000011 | Double-adjacent-error correction | Yes | | 00000111 | Triple-adjacent-error correction | Yes | | 00000101 | Triple-adjacent-error correction | Yes | | 00010011 | Non-adjacent double/triple correction/detection | No guarantee |

For more information about ECC, refer to the chapter about Embedded Memory Blocks in your target device handbook.

4.2.1.2.6. Byte Enable

To ensure that the operation writes only specific bytes of data, embedded memory blocks support the byte enable property, that masks the input data. The unwritten bytes or bits retain the previous value.

Note: AMD Xilinx RAMs support byte enable in Virtex-4 and newer devices.

The following table compares byte enable implementation in AMD Xilinx and Altera FPGA RAMs

Table 50. Byte Enables Differences in AMD Xilinx RAM and Altera FPGA RAM

| Differences | AMD Xilinx RAM | Altera FPGA RAM | Altera FPGA RAM | Altera FPGA RAM | |--------------------------------------------------------------------------------------|----------------------------------------------------------------------------------------------------------------------------------|------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | Controlling signals | The WEA[n:0] signal controls the byte enable. Each bit in WEA[n:0] acts as a write enable for the corresponding input data byte. | Uses two signals, write enable ( wren ) and byte enable ( byteena ). To control which byte to write, assert the wren signal and the specific bit of the byteena signal. For example, in a RAM block in x16 mode: | Uses two signals, write enable ( wren ) and byte enable ( byteena ). To control which byte to write, assert the wren signal and the specific bit of the byteena signal. For example, in a RAM block in x16 mode: | Uses two signals, write enable ( wren ) and byte enable ( byteena ). To control which byte to write, assert the wren signal and the specific bit of the byteena signal. For example, in a RAM block in x16 mode: | | Controlling signals | The WEA[n:0] signal controls the byte enable. Each bit in WEA[n:0] acts as a write enable for the corresponding input data byte. | | byte_enable | Writing on data[7..0] Writing data[15..8] | | Controlling signals | The WEA[n:0] signal controls the byte enable. Each bit in WEA[n:0] acts as a write enable for the corresponding input data byte. | | 01 | Enabled Disabled | | Controlling signals | The WEA[n:0] signal controls the byte enable. Each bit in WEA[n:0] acts as a write enable for the corresponding input data byte. | | 11 | Enabled Enabled | | Controlling signals | The WEA[n:0] signal controls the byte enable. Each bit in WEA[n:0] acts as a write enable for the corresponding input data byte. | To create a byteena port, the width of the input data port must be a multiple of the byte size for the port. | To create a byteena port, the width of the input data port must be a multiple of the byte size for the port. | To create a byteena port, the width of the input data port must be a multiple of the byte size for the port. | | Input data width support | Support multiples of 8 or 9 bits. | Support multiples of 5, 8, 9, 10 bits. For configurations smaller than two bytes wide, the write_enable or clock_enable signals control the write operation. (17) | Support multiples of 5, 8, 9, 10 bits. For configurations smaller than two bytes wide, the write_enable or clock_enable signals control the write operation. (17) | Support multiples of 5, 8, 9, 10 bits. For configurations smaller than two bytes wide, the write_enable or clock_enable signals control the write operation. (17) | | Output value of masked byte when performing read-during- write to the same location. | Output depends on read-during- write configuration: • WRITE_FIRST • READ_FIRST • NO_CHANGE | Output depends on the type of memory block: Memory Block Output of Masked Bytes | Output depends on the type of memory block: Memory Block Output of Masked Bytes | Output depends on the type of memory block: Memory Block Output of Masked Bytes | | Output value of masked byte when performing read-during- write to the same location. | Output depends on read-during- write configuration: • WRITE_FIRST • READ_FIRST • NO_CHANGE | | SDP | DONT_CARE or OLD_DATA | | Output value of masked byte when performing read-during- write to the same location. | Output depends on read-during- write configuration: • WRITE_FIRST • READ_FIRST • NO_CHANGE | | True dual Port | DONT_CARE | | Output value of masked byte when performing read-during- write to the same location. | Output depends on read-during- write configuration: • WRITE_FIRST • READ_FIRST • NO_CHANGE | | Simple Quad port | DONT_CARE | | Output value of masked byte when performing read-during- write to the same location. | Output depends on read-during- write configuration: • WRITE_FIRST • READ_FIRST • NO_CHANGE | | | |

Related Information

Read-During-Write Operation at the Same Address on page 59
Byte Enable in Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2-PORT) User Guide
Byte Enable in Stratix 10 Embedded Memory Blocks in Stratix 10 Embedded Memory User Guide
Byte Enable in Agilex 7 Embedded Memory Blocks in Agilex 7 Embedded Memory User Guide

(17) Only MLAB memory blocks support byte_enable for input data width that is multiple of 5.

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4.2.1.2.7. Address Clock Enable

Altera FPGA memory supports the address clock enable feature. The address clock enable holds the previous address value for as long as addressstall is enabled. AMD Xilinx RAM blocks support an equivalent feature, called Address Enable.

For more information about the address clock enable feature, refer to the Embedded Memory Blocks chapter in your target device handbook.

Related Information

Memory Blocks Address Clock Enable Support in Embedded Memory (RAM: 1PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2-PORT) User Guide
Address Clock Enable Support in Stratix 10 Embedded Memory User Guide
Address Clock Enable Support in Agilex 7 Embedded Memory User Guide

4.2.1.2.8. Parity Bit Support

Embedded memory blocks in Altera FPGAs have built-in parity-bit support for each byte. While AMD Xilinx memories support separate input and output buses for parity bits, the embedded memory blocks in Stratix 10 and Agilex 7 devices allow you to inject parity bits through the ECC encoder bypass feature.

The amount of memory in each RAM block includes the parity bits. No parity function is actually performed on the parity bits. You can use the parity bits for purposes other than ensuring data integrity; for example, to store user-specified control bits.

For more information about using the parity bit to detect memory errors, refer to the Using Parity to Detect Errors White Paper.

Related Information

Parity Bit in Stratix 10 Embedded Memory User Guide
Parity Bit in Agilex 7 Embedded Memory User Guide

4.2.1.2.9. Memory Initialization

In Altera FPGA devices, all embedded memory blocks support memory initialization, and initialize memory contents through memory initialization files ( .mif ) or Hexadecimal (Altera-Format) files ( .hex ). You can create these files with the Quartus Prime Pro Edition software. You specify the initialization file name while configuring your memory IP core through the IP Catalog/Parameter Editor.

AMD Xilinx devices use a memory coefficient (COE) file for initialization. Alternatively, you can use the default data option

Related Information

Hexadecimal (Altera-Format) File (.hex) Definition in Quartus Prime Pro Edition Help
Memory Initialization File (.mif) Definition in Quartus Prime Pro Edition Help
Converting Xilinx RAM initialization .coe/.mif Format to Altera PSG .mif/.hex Format

4.2.1.2.10. Output Synchronous Set/Reset

AMD Xilinx memory supports optional synchronous set/reset pins that control the reset operation of the last register in the output stage. This ability initializes the memory's output to a user-defined value.

Altera FPGA memory also supports asynchronous clear and synchronous clear on output latches and output registers. If the RAM does not use output registers, clear the RAM outputs using the output latch asynchronous clear ( aclr ). The aclr signal is generated at any time. The internal logic extends the clear pulse until the next rising edge of the output clock. When the aclr signal asserts, the outputs are cleared and stay clear until the next read cycle.

4.2.1.3. Determining Memory Block and Mapping Ports

If you are not sure which memory block to select, or are not particular about the memory block type, select AUTO in the IP Catalog/Parameter Editor.

This option allows the Quartus Prime software to determine the memory block type at compile time.

To find the type of memory block that the Quartus Prime software assigned to your design, check the Quartus Prime Fitter RAM Summary Report.

Otherwise, build the memory blocks in the IP Catalog/Parameter Editor using the proper plug-in.

The available plug-ins are:

Table 51. Memory Modes/Functions and Related Plug-In

| Memory Modes/Function | Plug-In | |---------------------------------------------------------------------|------------| | Single-port RAM | RAM:1-PORT | | Simple dual-port RAM | RAM:2-PORT | | True dual-port RAM (Arria 10 only) | RAM:2-PORT | | Simple quad-port RAM (Agilex 5, Agilex 7, and Stratix 10 (18) only) | RAM:4-PORT | | Single-port ROM | ROM:1-PORT | | Dual-port ROM | ROM:2-PORT |

For information about memory options, and how to build the memory function through the IP Catalog/Parameter Editor, refer to the embedded memory user guide.

Identify the port-mapping from AMD Xilinx memory ports to Altera FPGA memory ports.

Related Information

Fitter Feature Specific Reports in Quartus Prime Pro Edition Help

(18) simple quad-port RAM was removed from mostStratix 10 devices

4.2.1.4. Memory Port Mapping

The following table lists the memory ports that the Vivado's IP Catalog generates, and their corresponding mapping to Altera FPGA memory ports for different memory modes.

Table 52. Block Memory Generator's Memory Port Mapping to Altera FPGA Memory Ports

| Port Description | AMD Xilinx Ports | Port-Mapping to Altera FPGA Ports in Different Memory Modes | Port-Mapping to Altera FPGA Ports in Different Memory Modes | Port-Mapping to Altera FPGA Ports in Different Memory Modes | Port-Mapping to Altera FPGA Ports in Different Memory Modes | Port-Mapping to Altera FPGA Ports in Different Memory Modes | |---------------------------------------------------|------------------------|---------------------------------------------------------------|---------------------------------------------------------------|---------------------------------------------------------------|---------------------------------------------------------------|---------------------------------------------------------------| | Port Description | AMD Xilinx Ports | Single-Port RAM | Simple Dual- Port RAM | True Dual-Port RAM | Single-Port ROM | Dual-Port ROM | | Port A: address | addra | address | wraddress | wraddress/ address_a | address | address_a | | Port A: data input | dina | data | data | data/ data_a | - | - | | Port A: parity data input | dinpa | - | - | - | - | - | | Port A: clock enable for the input register | ena | inclocken/ clken | inclocken/ wrclocken/ enable | inclocken/ wrclocken/ enable | inclocken/ clken | enable | | Port A: clock enable for the last output register | regcea, ena | outclocken/ clken | enable | outclocken/ enable | outclocken/ clken | enable | | Port A: write enable | NA | wren | wren | wren/ wren_a | NA | NA | | Port A: byte enable (19) | wea | byteena | byteena_a | byteena_a | NA | NA | | Port A: asynchronous clear | NA | outaclr/ aclr | NA | out_aclr/ rd_aclr/ aclr | outaclr/ aclr | aclr | | Port A: synchronous set/reset | rsta/ rstrega | sclr | NA | sclr | sclr | sclr | | Port A: read enable | ena (in SDP (20) mode) | rden | NA | rden_a/ rden | rden | rden_a | | Port A: in clock | clka | inclock/ clock | inclock/ wrclock/ clock | inclock/ wrclock/ clock | inclock/ clock | clock | | | | | | | | continued... |

| Port Description | AMD Xilinx Ports | Port-Mapping to Altera FPGA Ports in Different Memory Modes | Port-Mapping to Altera FPGA Ports in Different Memory Modes | Port-Mapping to Altera FPGA Ports in Different Memory Modes | Port-Mapping to Altera FPGA Ports in Different Memory Modes | Port-Mapping to Altera FPGA Ports in Different Memory Modes | |---------------------------------------------------|------------------------|---------------------------------------------------------------|---------------------------------------------------------------|---------------------------------------------------------------|---------------------------------------------------------------|---------------------------------------------------------------| | Port Description | AMD Xilinx Ports | Single-Port RAM | Simple Dual- Port RAM | True Dual-Port RAM | Single-Port ROM | Dual-Port ROM | | Port A: out clock | NA | outclock/ clock | NA | NA | outclock/ clock | NA | | Port A: data output | douta | q | NA | q/ q_a | q | q_a | | Port A: parity data output | doutpa | - | - | - | - | - | | Port A: address enable | addrena (21) | addressstal l_a | wr_addresss tall | wr_addresss tall/ addressstal l_a | addressstal l_a | addressstal l_a | | Port B: address | addrb | NA | rdaddress | rdaddress/ address_b | NA | address_b | | Port B: data input | dinb | NA | NA | data_b | NA | NA | | Port B: parity data input | dinpb | - | - | - | - | - | | Port B: clock enable for the input register | enb | NA | NA | inclocken/ enable | NA | enable | | Port B: clock enable for the last output register | regceb, enb | NA | outclocken/ rdoutclocke n | outclocken/ enable | NA | enable | | Port B: write enable | enb (in SDP (20) mode) | NA | NA | wren_b | NA | NA | | Port B: byte enable | web | NA | NA | byteena_b | NA | NA | | Port B: asynchronous clear | - | NA | out_aclr/ rd_aclr/ aclr | rd_aclr/ out_aclr | NA | aclr | | Port B: synchronous set/reset | rstb/ rstregb | NA | sclr | sclr | NA | sclr | | Port B: read enable | - | NA | rden | rden_b | NA | rden_b | | Port B: clock | clkb | outclock/ clock | outclock/ rdclock/ clock | outclock/ rdclock | outclock/ clock | clock | | Port B: data output | doutb | NA | q | q/ q_b | NA | q_b |

You can also infer RAM in HDL. For more information, refer to the Recommended HDL Coding Styles in Quartus Prime Pro Edition User Guide: Design Recommendations .

Related Information

Memory Mode on page 58
Inferring Memory Functions from HDL Code in Quartus Prime Pro Edition User Guide: Design Recommendations

4.2.1.5. Example: Converting Simple Dual-Port RAM

This example includes Verilog HDL and VHDL code for the top level that instantiates the AMD Xilinx simple dual-port RAM.

In this example, the top-level entity test instantiates sdp_ram , a AMD Xilinx simple dual-port RAM generated through Block Memory Generator, with the following properties:

Table 53. Properties of Simple Dual-Port RAM

| Input data width | 16 bits | |----------------------------|----------------------------------------| | Memory depth | 8 words | | Clocking Mode | Different input and output clocks | | ECC feature | Selected | | Out data registered status | Output registered (one stage pipeline) | | Read-during-write | WRITE_FIRST (New Data) |

The original Verilog HDL Code in the Vivado Software is:

module test( input clka, input ena, input [0:0]wea, input [2:0]addra, input [15:0]dina, input clkb, input enb, input [2:0]addrb, output [1 5:0]doutb, output sbiterr, output dbiterr, output [2:0]rdaddrecc); simple dual port ip i1( .clka(clka), .ena(ena), .wea(wea), .addra(addra), .dina(dina), .clkb(clkb), .enb(enb), .addrb(addrb), .doutb(doutb), .sbiterr(sbiterr), .dbiterr(dbiterr), .rdaddrecc(rdaddrecc)); endmodule

The original VHDL Code in the Vivado Software is:

LIBRARY ieee; USE ieee.STD_LOGIC 1164.all; LIBRARY work; ENTITY test IS port ( clka: IN STD_LOGIC; ena: IN STD_LOGIC; wea: IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra: IN STD_LOGIC_VECTOR(2 DOWNTO 0); dina: IN STD_LOGIC_VECTOR(15 DOWNTO 0); clkb: IN STD_LOGIC; enb: IN STD_LOGIC; addrb: IN STD_LOGIC_VECTOR(2 DOWNTO 0); doutb: OUT STD_LOGIC_VECTOR(15 DOWNTO 0); dbiterr: OUT STD_LOGIC; sbiterr: OUT STD_LOGIC; rdaddrecc: OUT STD_LOGIC_VECTOR(2 DOWNTO 0)); END test; ARCHITECTURE arch OF test IS component simple dual port ip PORT( clka: IN STD_LOGIC; ena: IN STD_LOGIC; wea: IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra: IN STD_LOGIC VECTOR(2 DOWNTO 0); dina: IN STD_LOGIC VECTOR(15 DOWNTO 0); clkb: IN STD_LOGIC; enb: IN STD_LOGIC; addrb: IN STD_LOGIC VECTOR(2 DOWNTO 0); doutb: OUT STD_LOGIC VECTOR(15 DOWNTO 0); dbiterr: OUT STD_LOGIC; sbiterr: OUT STD_LOGIC; rdaddrecc: OUT STD_LOGIC vector ( 2 DOWNTO 0) end component; BEGIN il: simple_dual_port_ip PORT MAP( clka => clka,

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ena => ena, wea => wea, addra => addra, dina => dina, clkb => clkb, enb => enb, addrb => addrb, doutb => doutb, dbiterr => dbiterr, sbiterr => sbiterr, rdaddrecc => rdaddrecc); END;

To convert a AMD Xilinx Simple Dual Port RAM to Altera FPGA:

Create an Altera FPGA simple dual-port RAM through the Quartus Prime software IP Catalog/Parameter Editor.
Configure the RAM with the following options:
Instantiate the new Altera FPGA RAM. to replace the AMD Xilinx RAM.

Table 54. Parameters of Simple Dual-Port RAM

| How will you be using the dual port RAM? | How will you be using the dual port RAM? | How will you be using the dual port RAM? | Specifies how you use the dual port RAM. | |--------------------------------------------|---------------------------------------------------|---------------------------------------------------|-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | | With one read port and one write port | With one read port and one write port | | | Read/Write Ports | Read/Write Ports | Read/Write Ports | Specifies the width of the input and output ports. | | | How wide should the 'q_a' output bus be? | 16 bits | | | | How wide should the 'q_b' output bus be? | 16 bits | | | What should the memory type be? | What should the memory type be? | What should the memory type be? | Specifies the memory block type. The available memory blocks depend on the target device. | | | RAM Block Type | M20K | | | What clocking method do you want to use? | What clocking method do you want to use? | What clocking method do you want to use? | Specifies the clocking method to use. | | | Dual clock: use separate 'read' and 'write' clock | Dual clock: use separate 'read' and 'write' clock | A write clock controls the data-input, write- address, and write-enable registers while the read clock controls the data-output, read-address, and read-enable registers. | | ECC Checking | ECC Checking | ECC Checking | | | | Enable Error Correction Check (ECC) | On | Specifies whether to enable the ECC feature that corrects single bit errors, double adjacent bit errors, and detects triple adjacent bit errors at the output of the memory | | | Enable ECC Pipeline Registers | On | Specifies whether to enable the ECC pipeline registers before the output decoder to achieve that same performance as non-ECC mode at the expense of one cycle of latency | | Clock Enables | Clock Enables | Clock Enables | Specifies whether to create clock enables for read and write registers. | | | Use different clock enables for registers | On | | | | Use clock enable for write input registers | On | | | | Use clock enable for output registers | On | |

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The converted Verilog HDL code in the Quartus Prime Software after instantiating the new RAM:

module test( input clka, input ena, input [0:0]wea, input [2:0]addra, input [15:0]dina, input clkb, input enb, input [2:0]addrb, output [15:0]doutb, output sbiterr, output dbiterr, output [2:0]rdaddrecc); simple_dual_port_ip i1( .wrclock (clka), .wrclocken (ena), .wren (wea), .wraddress (addra), .data (dina), .rdclock (clkb), .rdoutclocken (regceb | enb), .rdaddress (addrb), .q (doutb), .eccstatus ({dbiterr, sbiterr}) ); endmodule

The converted VHDL code in the Quartus Prime Software:

LIBRARY ieee; USE ieee.STD_LOGIC_1164.all; LIBRARY work; ENTITY test IS port ( clka: IN STD_LOGIC; ena: IN STD_LOGIC; wea: IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra: IN STD_LOGIC_VECTOR(2 DOWNTO 0); dina: IN STD_LOGIC_VECTOR(15 DOWNTO 0); clkb: IN STD_LOGIC; end: IN std_Iogic; addrb: IN STD_LOGIC_VECTOR(2 DOWNTO 0); doutb: OUT STD_LOGIC_VECTOR(15 DOWNTO 0); dbiterr: OUT STD_LOGIC; sbiterr: OUT STD_LOGIC; rdaddrecc: OUT STD_LOGIC_VECTOR(2 DOWNTO 0)); END test, ARCHITECTURE arch OF test IS component simple_dual_port_ip PORT( wrclock: IN STD_LOGIC; wrclocken: IN STD_LOGIC; wren: IN STD_LOGIC_VECTOR(0 DOWNTO 0); wraddress: IN STD_LOGIC_VECTOR(2 DOWNTO 0); data: IN STD_LOGIC_VECTOR(15 DOWNTO 0); rdclock: IN STD_LOGIC; rdaddress: IN STD_LOGIC_VECTOR(2 DOWNTO 0); q: OUT STD_LOGIC_VECTOR(1 DOWNTO 0); eccstatus: OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ); end component; signal eccstatus_o: STD_LOGIC_VECTOR(1 DOWNTO 0); BEGIN dbiterr <= eccstatus_o(1); sbiterr <= eccstatus_o(0); i1: simple_dual_port_ip PORT MAP(

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Related Information

RAM: 2-PORT IP Core Parameters in Stratix 10 Embedded Memory User Guide
RAM: 2-PORT IP Core Parameters in Agilex 7 Embedded Memory User Guide

4.2.2. Converting Mixed-Mode Clock Manager (MMCM) to Phase-Locked Loop (PLL)

Similar to Mixed-Mode Clock Managers (MMCM) in AMD Xilinx devices, some Altera FPGA device families support PLLs. This ability increases device and board-level performance by allowing you to minimize clock skew and clock delay and provide support for clock synthesis.

You can convert MMCMs to PLLs in Altera FPGA devices with the IP Catalog/Parameter Editor by using the Altera FPGA IOPLL IP core, which allows you to create custom PLLs targeting to Altera FPGA devices.

Note:

Altera now refers to the ALTPLL IP Core as Altera FPGA IOPLL IP core.

AMD Xilinx MMCMs require specific input buffers to feed into the source clock port; for example, IBUF , IBUFG , or BUFGMUX . In contrast, PLLs in Altera FPGA devices do not require input buffers when using the IP Catalog/Parameter Editor.

4.2.2.1. Feature Comparison

The following table compares MMCM features in UltraScale+ with PLL features in Stratix 10 devices.

Table 55. MMCM in UltraScale+ versus PLL in Stratix 10 Devices

| Features | Features | AMD Xilinx MMCM (UltraScale+) | Altera FPGA IOPLL (Stratix 10) | |---------------------|-----------------------------------|---------------------------------|----------------------------------| | Frequency Synthesis | Clock Multiplication and Division | Yes | Yes | | Frequency Synthesis | Phase Shifting | Yes | Yes | | Frequency Synthesis | Clock Duty Cycle | Yes | Yes | | MMCM Deskew Adjust | Internal Feedback | Yes | | | MMCM Deskew Adjust | Spread Spectrum | Yes | Yes | | MMCM Deskew Adjust | System Synchronous Normal Mode | Yes | Yes | | MMCM Deskew Adjust | Source Synchronous | Yes | Yes | | MMCM Deskew Adjust | Zero Delay Buffer | Yes | Yes | | continued... | continued... | continued... | continued... |

| Features | Features | AMD Xilinx MMCM (UltraScale+) | Altera FPGA IOPLL (Stratix 10) | |------------|-------------------------------------|---------------------------------|----------------------------------| | | No Compensation | Yes (CMT to CMT connection) | Yes (Direct compensation) (22) | | | External Feedback | Yes | Yes | | Others | Input Clock Switchover | Yes | Yes | | Others | Dynamic re-configuration | Yes | Yes | | Others | Single or Differential Clock Inputs | Yes | Yes |

4.2.2.2. Port Mapping Reference

The following table shows the mapping between MMCM UltraScale ports, created with the AMD Xilinx IP Catalog, and PLL ports in Stratix 10 device, created with the IP Catalog.

Table 56. Port-Mapping MMCM UltraScale versus PLL Stratix 10

| AMD Xilinx MMCM Core Port | Altera FPGA Altera FPGA IOPLL IP Core Port | Description | |------------------------------|----------------------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | clk_in1 | refclk | First clock input | | clk_in2 | refclk1 | Second clock input | | clkfb_in | fbclk | External clock feedback | | clkfbout | fboutclk | Feeds into the feedback port | | - | activeclk | Output signal that indicates which reference clock source the I/O PLL uses | | clk_in_sel | extswitch | Switch between input clock ports | | reset | rst | Asynchronous reset port | | clk_out1, clk_out2, clk_outX | outclk_[] | Clock frequency output ports. AMD Xilinx MMCM has fixed settings for most outputs, and you can configure the Altera FPGA IOPLL IP core to suit them. | | clkinstopped | clkbad[1..0] | Indicates whether the clock input signal stopped switching | | clkfb_stopped | - | Specifies whether the feedback clock stopped | | locked | locked | Specifies whether the PLL is locked | | - | adjpllin | Input signal that feeds from upstream I/O PLL | | - | cascade_out | Output signal that feeds into downstream I/O PLL | | - | zdbfbclk | Bidirectional port that connects to the mimic circuitry. You connect this port to a bidirectional pin that is placed on the positive feedback dedicated output pin of the I/O PLL. The zdbfbclk port is available only if the I/O PLL is in zero-delay buffer mode. |

| AMD Xilinx MMCM Core Port | Dynamic Phase Shift Ports in Altera FPGA IOPLL | Description | |-----------------------------|--------------------------------------------------|--------------------------------------------------------------------| | psclk | scanclk | Specifies clock that drives the dynamic phase shift operation | | psen | phase_en | Start dynamic phase-shift operation | | psincdec | updn | Specifies direction of phase shift operation | | - | cntsel | Specifies counter for dynamic phase shift operation | | - | num_phase_shift | Specifies number of phase shifts per dynamic phase shift operation | | psdone | phase_done | Specifies completion of dynamic phase shift operation | | power_down | - | Enables power_down input port for user selection |

For more information about using dynamic PLL reconfiguration, refer to the PhaseLocked Loops (Altera FPGA IOPLL) IP Core User Guide.

Related Information

IOPLL IP Core User Guide
Stratix 10 Clocking and PLL User Guide
Agilex 7 Clocking and PLL User Guide

4.2.2.3. Example: Converting AMD Xilinx MMCM into an Altera PLL

This example uses a mymmcm module generated with the AMD Xilinx IP Catalog. The top module instantiates the mymmccm module with i1 . The parameters are:

Table 57. Example Parameters

| Parameter | Value | |--------------------------------------|--------------------------| | Input Clock Frequency | 100 MHz | | Clock frequency output port clk_out1 | Divide by 2 (50 MHz). | | Clock frequency output port clk_out2 | Multiply by 4 (400 MHz). |

Original Verilog Code in the Vivado Software:

module top( // Clock out ports output clk_out1, output clk_out2, input reset, output locked, // Clock in ports input clk_in1 ); mymmcm i1 ( .reset(reset), .clk_in1(clk_in1), .locked(locked), .clk_out1(clk_out1), .clk_out2(clk_out2) );

// Status and control signals endmodule

To recreate the same behavior using Altera FPGA software:

In the IP Catalog/Parameter Editor, point to Library ➤ Basic Functions ➤ Clocks, PLLs and Resets ➤ PLL , and double-click Altera FPGA IOPLL .

Figure 13. Altera FPGA IOPLL on IP Catalog

Generate an IP variant named mypll .
In the Parameter Editor, set the following parameters:

Table 58. Parameters of mypll

| General | General | General | | |---------------|---------------------------|---------------|----------------------------------------------------------| | | Reference Clock Frequency | 100 MHz | | | Output Clocks | Output Clocks | Output Clocks | | | | Number of Clocks | 2 | Specifies the number of clocks that your design requires | | outclk0 | outclk0 | outclk0 | | | | Clock Name | clk_out11 | | | | Desired Frequency | 50 MHz | | | outclk1 | outclk1 | outclk1 | | | | Clock Name | clk_out2 | | | | Desired Frequency | 400 MHz | |

Click Finish .
Create a top module, and instantiate the mypll module with i1 .

The converted Verilog HDL code in the Quartus Prime Software is:

module top(output clk_out1, output clk_out2, input reset, output locked, input clk_in1); mypll i1(.rst(reset), .refclk(clk_in1), .locked (locked), .outclk_0 (clk_out1), .outclk_1(clk_out2)); end module

4.2.3. Converting Multipliers

The following section discusses converting instances of the AMD Xilinx Multiplier Core to Altera FPGA Multiplier IP cores.

Altera provides two IP cores for implementing multiply, multiply- accumulate, and multiply-add functions using DSP blocks or logic resources:

The LPM_MULT IP core, which performs multiply functions only.
The Altera FPGA Multiply Adder IP core, which performs multiply, multiply-add, or multiply-accumulate functions.

To perform the conversion:

In the original code, identify whether the dataa and datab ports have the same sign.
If the ports have the same sign, replace the AMD Xilinx Multiplier Core with the LPM_MULT IP core,
Otherwise, replace with the Altera FPGA Multiply Adder IP core.
In the IP Catalog, click the selected IP core.
Assign the parameters and generate HDL IP core.

For more information, refer to Inferring Multipliers in the Recommended HDL Coding Styles chapter of Quartus Prime Pro Edition User Guide: Design Recommendations .

Related Information

Inferring Multipliers and DSP Functions in Quartus Prime Pro Edition User Guide: Design Recommendations

4.2.3.1. Feature Comparison

The AMD Xilinx Multiplier Core and the Altera FPGA LPM_MULT IP core have similar features; however, you must consider one difference:

In the LPM_MULT IP core, the dataa and datab ports must have the same sign. If your design does not meet this requirement, you can use the Altera FPGA Multiply Adder IP core to replace the AMD Xilinx Multiplier Core.

The following table compares the AMD Xilinx Multiplier Core and the Altera FPGA LPM_MULT IP core.

Table 59. AMD Xilinx Multiplier Core versus Altera FPGA LPM_MULT IP Core

| Feature | AMD Xilinx Multiplier Core Generator Module | Altera FPGA LPM_MULT IP Core | |-------------------------------|-----------------------------------------------|--------------------------------| | Constant Coefficient | Yes | Yes | | Signed and Unsigned Data | Yes | Yes | | Configurable Pipeline Latency | Yes | Yes | | Area versus Speed Trade-off | Yes | Yes | | continued... | continued... | continued... |

| Feature | AMD Xilinx Multiplier Core Generator Module | Altera FPGA LPM_MULT IP Core | |------------------------------------------|-----------------------------------------------|----------------------------------------------------------------------------------------------| | Asynchronous Clear | - | Yes | | Synchronous Clear | Yes | Yes | | Port A and Port B support different sign | Yes | - Consider using the Altera FPGA LPM_MULT IP core to replace the AMD Xilinx Multiplier Core. |

Related Information

LPM_MULT (Multiplier) IP Core in Altera FPGA Integer Arithmetic IP Cores User Guide

4.2.3.2. Port Mapping

The following table shows the port mapping between the AMD Xilinx Multiplier Core and the Altera FPGA LPM_MULT IP core.

Table 60. Port Mapping Between AMD Xilinx Multiplier Core and LPM_MULT IP Core

| AMD Xilinx Multiplier Core Port | Altera FPGA LPM_MULT IP Core Port | Description | |-----------------------------------|-------------------------------------|----------------------------| | A [] | dataa [] | Data Input Port A | | B [] | datab [] | Data Input Port B | | CLK [] | clock | Clock Port | | CE | clken | Clock Enable Port | | SCLR | sclr | Synchronous Clear Port | | N/A | aclr | Asynchronous Clear Port | | P [] | result [] | Multiplication Result Port |

4.2.3.3. Example: Converting to the LPM_MULT IP Core

You can convert the AMD Xilinx Multiplier Core that targets a AMD Xilinx device into multipliers for an Altera FPGA device by using the IP Catalog.

In this example, the test module instantiates the mymult module, created using the AMD Xilinx Core Generator. The parameters are:

Table 61. Parameters of Multiplier Module

| Parameter | Value | |-------------------------------------------------------|--------------------------------------------------------------------------| | Multiplier Type | Parallel multiplier where neither of the input buses is a constant value | | Input data width | 18 bits | | Input data type | Signed | | Output result width | Restricted to 36 bits | | Number of pipeline stages | 2 | | Implemented using Multipliers and optimized for Speed | Implemented using Multipliers and optimized for Speed |

AN 307: Altera ® FPGA Design Flow for AMD* Xilinx* Users

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The Original Verilog HDL Code in the Vivado Software is:

module top( input clk, input [17:0] a, input [17:0] b, input ce, input sclr, output [35:0] p ); mymult i1 ( .CLK(clk), .A(a), // Bus [17: 0] .B(b), // Bus [17: 0] .CE(ce), .SCLR(sclr), .P(p)); // Bus [35: 0] endmodule

The original VHDL Code in the Vivado Software is:

LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY work; ENTITY test IS port ( clk: IN STD_LOGIC; a: IN STD_LOGIC_VECTOR(17 downto 0); b: IN STD_LOGIC_VECTOR(17 downto 0); sclr: IN STD_LOGIC; ce: IN STD_LOGIC; p: OUT STD_LOGIC_VECTOR(35 downto 0) ); END test; ARCHITECTURE arch OF test IS component mymult PORT( CLK: IN STD_LOGIC; A: IN STD_LOGIC_VECTOR(17 downto 0); B: IN STD_LOGIC_VECTOR(17 downto 0); CE: IN STD_LOGIC; SCLR: IN STD_LOGIC; P: OUT STD_LOGIC_VECTOR(35 downto 0) ); end component; BEGIN i1: mymult PORT MAP(CLK => clk, A => a, B => b, CE => ce, SCLR => sclr, P => p); END;

In the IP Catalog, select the LPM_MULT IP core to create the equivalent mymult module.

Converted Verilog HDL Code in the Quartus Prime Pro Edition software:

module test( input clk, input [17:0] a, input [17:0] b, input ce, input sclr, output [35:0] p );

mymult i1 ( .clock(clk), .dataa(a), // Bus [17: 0] .datab(b), // Bus [17: 0] .clken(ce), .sclr(sclr), .result(p)); // Bus [35: 0] endmodule

Converted VHDL Code in the Quartus Prime Pro Edition Software

LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY work; ENTITY test IS port ( clk: IN STD_LOGIC; a: IN STD_LOGIC_VECTOR(17 downto 0); b: IN STD_LOGIC_VECTOR(17 downto 0); ce: IN STD_LOGIC; sclr: IN STD_LOGIC; p: OUT STD_LOGIC_VECTOR(35 downto 0) ); END test; ARCHITECTURE arch OF test IS component mymult PORT(clock: IN STD_LOGIC; dataa: IN STD_LOGIC_VECTOR(17 downto 0); datab: IN STD_LOGIC_VECTOR(17 downto 0); clken: IN STD_LOGIC; sclr: IN STD_LOGIC; result: OUT STD_LOGIC_VECTOR(35 downto 0) ); end component; BEGIN i1: mymult PORT MAP(clock => clk, dataa => a, datab => b, clken => ce, sclr => sclr, result => p); END;

4.2.3.4. Example: Converting to the Altera FPGA Multiply Adder IP core

The following example shows VHDL multipliers compiled in the Quartus Prime Pro Edition Software after the conversion. The IP Catalog implements the Multiply Adder IP core by creating the mymult_add module.

The converted VHDL Code in the Quartus Prime Pro Edition Software is:

LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY work; ENTITY test IS port ( clk:IN STD_LOGIC; a: IN STD_LOGIC_VECTOR(17 downto 0);

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b: IN STD_LOGIC_VECTOR(17 downto 0); ce: IN STD_LOGIC; sclr: IN STD_LOGIC; p: OUT STD_LOGIC_VECTOR(35 downto 0) ); END test; ARCHITECTURE arch OF test IS component mymult_add PORT( clock0: IN STD_LOGIC; dataa_0: IN STD_LOGIC_VECTOR(17 downto 0); datab_0: IN STD_LOGIC_VECTOR(17 downto 0); ena0: IN STD_LOGIC; sclr0: IN STD_LOGIC; result: OUT STD_LOGIC_VECTOR(35 downto 0) ); end component; BEGIN i1: mymult_add PORT MAP(clock0 => clk, dataa_0 => a, datab_0 => b, ena0 => ce, sclr0 => sclr, result => p); END;

4.3. Setting Equivalent AMD Xilinx Design Constraints

AMD Xilinx designs store all the constraints and attributes in AMD Xilinx Design Constraint ( .xdc ) files, including timing and device constraints. Altera FPGA designs use separate files for device ( .qsf ) and timing ( .sdc ) constraints. The Design Constraints section in FPGA Tools Comparison lists the appropriate GUIs to enter design constraints.

Note:

AMD Xilinx-based placement constraints do not carry over to Altera FPGA placement constraints. Avoid making placement constraints to a design until you finish the conversion to the Quartus Prime software.

Related Information

Design Constraints on page 25
Timing Constraints on page 86

4.3.1. Device Constraints

The following table summarizes the most common AMD Xilinx device constraints and Altera FPGA equivalent device constraints.

Table 62. Altera FPGA Equivalent Device Constraints

| AMD Xilinx Constraint | Altera FPGA Constraint | Altera FPGA Constraint | Description | |-------------------------|--------------------------|--------------------------|---------------------------------------| | AMD Xilinx Constraint | Assignment Name | QSF Variable | Description | | DRIVE | Current Strength | CURRENT_STRENGTH_NEW | Controls the output pin current value | | SLEW | Slew Rate | SLEW_RATE | Turns on Fast Slew Rate Control. | | continued... | continued... | continued... | continued... |

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| AMD Xilinx Constraint | Altera FPGA Constraint | Altera FPGA Constraint | Description | |-------------------------|------------------------------------------|----------------------------------------------------|--------------------------------------------------------------------------| | AMD Xilinx Constraint | Assignment Name | QSF Variable | Description | | IOB | Fast Input Register Fast Output Register | FAST_INPUT_REGISTER FAST_OUTPUT_REGISTER | Specifies whether the Compiler places a register in the device's IOB. | | IOSTANDARD | IO Standard | IO_STANDARD | Specifies the I/O standard for an I/O pin | | KEEP | Implement as Output of Logic Cell | "attribute keep" (VHDL) "synthesis keep" (Verilog) | Prevents a net from either being absorbed by a block or synthesized out. |

To set or modify a device constraint, use the Quartus Prime Assignment Editor. Alternatively, you can edit the .qsf file.

4.3.1.1. DRIVE

Equivalent to the DRIVE constraint in the AMD Xilinx Vivado software, the CURRENT_STRENGTH_NEW logic option sets the drive strength of a pin. You must assign this option to an output or bidirectional pin; otherwise, the Compiler ignores it.

The following example shows how to set the equivalent DRIVE constraint with 12 mA to the output ' q1 '.

Example of XDC command:

# Set drive strength 12 mA to q1 set_property DRIVE 12 [get_ports q1];

Equivalent QSF command:

# Set drive strength 12 mA to q1 set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to q1

For more information about the current strength feature in the device, refer to the specific device handbook and the Quartus Prime Help.

Related Information

Current Strength logic option in Quartus Prime Pro Edition Help

4.3.1.2. SLEW

Equivalent to the SLEW constraint in the AMD Xilinx Vivado software, the SLEW_RATE logic option helps to reduce switching noise by controlling low-to-high or high-to-low transitions on output pins. When a large number of output pins switch simultaneously, pins that use the lower SLEW_RATE option help reduce switching noise. This option is only applicable to output or bidirectional pins.

The following example shows how to set the equivalent SLEW constraint to the output ' q1 '.

Example of XDC command:

# set fast slew rate to q1 set_property SLEW FAST [get_ports q1]

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Equivalent QSF command:

# set programmable slew rate to q1 set_instance_assignment -name SLEW_RATE 1 -to q1

For more information about the slew rate feature in the device, refer to the specific device handbook.

4.3.1.3. IOB

Equivalent to the IOB constraint in AMD Xilinx, the FAST_INPUT_REGISTER and FAST_OUTPUT_REGISTER logic options directs the Compiler to implement an input register and output register in an I/O cell that has a fast, direct connection from an I/O pin.

The following example shows how to set the equivalent IOB constraint to the input ' d1 ' or the output ' q1 '.

Example of XDC command:

# Set IOB to input d1 set_property IOB TRUE [get_ports d1]; # Set IOB to output q1 set_property IOB TRUE [get_ports q1];

Equivalent QSF command:

# Set FAST_INPUT_REGSITER to input d1 set_instance_assignment -name FAST_INPUT_REGISTER ON -to d1 # Set FAST_OUTPUT_REGSITER to output q1 set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to q1

For more information about the slew fast input and output register features in the device, refer to the specific device handbook and the Quartus Prime Help.

Related Information

Fast Input Register logic option in Quartus Prime Pro Edition Help
Fast Output Register logic option in Quartus Prime Pro Edition Help

4.3.1.4. IOSTANDARD

Equivalent to the IOSTANDARD constraint in AMD Xilinx, the IO_STANDARD logic option uniquely defines the input and output (VCCIO) voltage, reference VREF voltage (if applicable), and the types of input and output buffers used for I/O pins.

The following example shows how to set the equivalent IOSTANDARD constraint (Differential SSTL-2 Class I) to the ' q2 ' output.

Example XDC command:

# Set Differential SSTL18_I I/O Standard to q2 set_property IOSTANDARD SSTL18_I [get_ports q2];

Equivalent QSF command:

# Set Differential SSTL-18 Class I I/O Standard to q2 set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to q2

Related Information

I/O Standard logic option in Quartus Prime Pro Edition Help

4.3.1.5. KEEP

Equivalent to the KEEP constraints, the Attribute Keep (VHDL) or Synthesis Keep (Verilog) synthesis attributes direct the Compiler to keep a wire or combinational node through logic synthesis minimizations and netlist optimizations. Similarly, you can also set the Implement as Output of Logic Cell logic option in the Quartus Prime Assignment Editor.

The following example shows how both VHDL and Verilog HDL set the equivalent KEEP constraint (Differential SSTL-2 Class I) to the my_wire signal.

Verilog HDL example in the Vivado software:

(* KEEP = "TRUE" *) wire my_wire

Equivalent Verilog HDL example in the Quartus Prime software:

(    *preserve*) wire my_wire;

VHDL example in the Vivado software:

signal my_wire: bit; attribute keep: string;

attribute keep of my_wire: signal is "TRUE";

Equivalent VHDL example in the Quartus Prime software:

signal my_wire: bit; attribute syn_keep: boolean; attribute syn_keep of my_wire: signal is true;

Related Information

Preserving Registers During Synthesis in Quartus Prime Pro Edition User Guide: Design Compilation
keep VHDL Synthesis Attribute in Quartus Prime Pro Edition Help
keep Verilog HDL Synthesis Attribute in Quartus Prime Pro Edition Help

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4.3.2. Placement Constraints

The following table compares the most common AMD Xilinx placement constraints with the Altera FPGA equivalent placement constraints:

Table 63. Placement Constraints

| AMD Xilinx Constraint | Altera FPGA Constraint | Altera FPGA Constraint | Description | |----------------------------------------------|--------------------------|--------------------------|-----------------------------------------------------------------------------------------------------| | | Assignment Name | QSF Variable | | | PBLOCK | Logic Lock Region | CORE_ONLY_PLACE_REGION | Specifies whether the placement region only applies to core logic. | | PBLOCK | Logic Lock Region | FLOATING_REGION | Specifies the type of floating region | | PBLOCK | Logic Lock Region | PLACE_REGION | Specifies the target and bounding boxes of a placement region | | PBLOCK | Logic Lock Region | REGION_NAME | Specifies the region name of a design instance. | | PBLOCK | Logic Lock Region | RESERVE_PLACE_REGION | Specifies whether the placement region prevents the Fitter from placing other logic in that region. | | PBLOCK | Logic Lock Region | ROUTE_REGION | Specifies the target and bounding boxes of a routing region. | | PACKAGE_PIN < Pin Number > | Location Assignment | PIN_< Pin number > | Assigns a location on the device for the current nodes or pins. | | LOC (for primitive cell such as SLICE, RAMB) | Location Assignment | < Location > < Value > | Assigns a location on the device for the current nodes or pins. | | BEL (for registers, LUT, SRL, LUTRAM) | Location Assignment | < Location > < Value > | Assigns a location on the device for the current nodes or pins. | | PROHIBIT | NA | NA | NA |

To set or modify placement constraints, use the Quartus Prime Assignment Editor. Alternatively, you can edit the .qsf file.

Related Information

Viewing and Editing Design Placement on page 31

4.3.2.1. PBLOCK

Equivalent to the PBLOCK constraint in the AMD Xilinx Vivado software, Logic Lock regions are floorplan location constraints in the Quartus Prime Pro Edition software. Logic Lock region assignments have Placement and Routing Regions

The following example shows how to set a module's attributes in a XDC file, using:

EXCLUDE_PLACEMENT -directs the Fitter to place only pblock's logic in the device resources within the pblock region.
CONTAIN_ROUTING -directs the Fitter to route signals in the pblock area using only resources available within the pblock area.

In this example, the module does not contain any I/O resources.

XDC Command:

create_pblock pblock_uut_inst add_cells_to_pblock [get_pblocks pblock_uut_inst] [get_cells -quiet [list uut_inst]] resize_pblock [get_pblocks pblock_uut_inst] -add {SLICE_X218Y284:SLICE_X220Y346} resize_pblock [get_pblocks pblock_uut_inst] -add {RAMB18_X12Y114:RAMB18_X12Y137} resize_pblock [get_pblocks pblock_uut_inst] -add {RAMB36_X12Y57:RAMB36_X12Y68} set_property CONTAIN_ROUTING 1 [get_pblocks pblock_uut_inst] set_property EXCLUDE_PLACEMENT 1 [get_pblocks pblock_uut_inst]

Equivalent QSF Command:

set_instance_assignment -name PLACE_REGION "X1 Y1 X20 Y20" -to uut_inst

set_instance_assignment -name RESERVE_PLACE_REGION ON -to uut_inst set_instance_assignment -name CORE_ONLY_PLACE_REGION ON -to uut_inst set_instance_assignment -name REGION_NAME uut_inst -to uut_inst set_instance_assignment -name ROUTE_REGION "X1 Y1 X20 Y20" -to uut_inst

REGION_NAME creates an Logic Lock region named 'uut_inst', and assigns module uut_inst to this region. This is similar to XDC's CREATE_PBLOCK and ADD_CELLS_TO_PBLOCK assignments.

set_instance_assignment -name REGION_NAME uut_inst -to uut_inst

PLACE_REGION defines the coordinates for the placement region, similar to XDC's RESIZE_PBLOCK assignments.

set_instance_assignment -name PLACE_REGION "X1 Y1 X20 Y20" -to uut_inst

RESERVE_PLACE_REGION prevents the Fitter from placing other logic in the region, equivalent to XDC's EXCLUDE_PLACEMENT assignment.

set_instance_assignment -name RESERVE_PLACE_REGION ON -to uut_inst

Defining ROUTE_REGION with the same coordinates as PLACE_REGION indicates the routing to remain within the placement region, equivalent to XDC's CONTAIN_ROUTING assignment.

set_instance_assignment -name ROUTE_REGION "X1 Y1 X20 Y20" -to uut_inst

By default, Logic Lock assignments include periphery resources, and you prevent this behavior with the CORE_ONLY_PLACE_REGION logic option. However, in XDC, the default behavior is to exclude periphery resources, so you must apply pblock constraints to include periphery resources in the pblock region.

set_instance_assignment -name CORE_ONLY_PLACE_REGION ON -to uut_inst

Related Information

Logic Lock Region Assignment Examples in Quartus Prime Pro Edition User Guide: Design Optimization

AN-307 | 2026.01.05

4.3.2.1.1. Differences Between PBLOCK and Logic Lock Regions

The default behavior of PBLOCK Logic Lock regions presents one important difference:

When you assign a module to a Logic Lock region, the resources within the Logic Lock region become available to the module automatically. In the Vivado software, you must manually assign the resources that the module can use to the PBLOCK region.

4.3.2.2. PACKAGE_PIN

Equivalent to the PACKAGE_PIN constraint in the AMD Xilinx Vivado software, PIN_<pin number> is the pin location constraint assignment that the Quartus Prime Pro Edition uses.

The following example shows how to set the location for a clock pin on the device.

Example of XDC Command:

# Assign location for the clock pin set_property PACKAGE_PIN B26 [get_ports clock]

Equivalent QSF Command:

# Assign location for the clock pin set_location_assignment PIN_AU33 -to clock

4.3.2.3. LOC & BEL

In the AMD Xilinx Vivado software, the LOC constraint specifies the placement of a logic cell to a specific SLICE, and the BEL constraint specifies the placement of a leaf cell within the SLICE. The AMD Xilinx Vivado software uses the LOC & BEL constraints to place a register or LUT or SRL or memory to a specific location. An equivalent constraint in the Quartus Prime Pro Edition software is <Location> -to <value> .

The following example shows how to constraint the location for a current node on the device.

Example of XDC Command:

# Assign location for an internal register

set_property LOC SLICE_X0Y0 [get_cells uut_inst/dout_reg]

Equivalent QSF Command:

# Assign location for an internal register set_location_assignment FF_X60_Y119_N55 -to uut_inst|dout_reg

4.3.2.4. PROHIBIT

PROHIBIT specifies the BEL or LOC on a AMD Xilinx device where placement is prohibited. An equivalent constraint is not available in the Quartus Prime Pro Edition Software.

4.3.3. Timing Constraints

You can convert constraints defined in XDC files to SDC commands that the Quartus Prime Pro Edition Timing Analyzer can use.

The following table summarizes the most common Vivado XDC timing constraints and the equivalent SDC timing constraints. You can set the constraints by either modifying the .sdc file or by using the Timing Analyzer GUI.

Table 64. Vivado XDC versus Timing Analyzer SDC Timing Constraints

| Vivado XDC Timing Constraint | Timing Analyzer SDC Command | Description | |--------------------------------|------------------------------------------------------------------|-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | | create_clock create_generated_clock set_max_delay set_false_path | Defines all the clocks and their relationship in a design. | | NA | derive_pll_clocks | Automatically creates a generated clock constraint on each output of the PLLs in a design. Note: Only Arria 10and Cyclone 10 GX devices support this command. For Stratix 10 and Agilex 7 devices, the Timing Analyzer derives PLL clocks from the constraints bound to the related IP. Vivado tools auto-derive the generated clocks; therefore, XDC files do not require these constraints. | | NA | derive_clock_uncertainty | Calculates clock-to-clock uncertainties within the FPGA due to characteristics like PLL jitter , clock tree jitter , etc. The Timing Analyzer generates a warning if the command is not present in the SDC files. Vivado tools auto-derive the generated clocks; therefore, XDC files do not require these constraints. | | set_input_delay | set_input_delay | Input timing constraint that you use to define the Pad-to-Setup timing requirement in a design. | | | set_output_delay | Defines the global Clock to Pad timing requirement in a design. | | | set_max_delay | Combinational path that constrains all combinational pin to pin paths. | | | set_false_path | Eliminates the paths from timing consideration during Place and Route and timing analysis. | | | set_clock_groups | Cuts timing between clocks in different groups. |

For more information about using the SDC commands and their usage, refer to the Quartus Prime Pro Edition User Guide: Timing Analyzer.

Related Information

Using the Quartus Prime Timing Analyzer in Quartus Prime Pro Edition User Guide: Timing Analyzer

4.3.3.1. Clock Domain Crossing

The following table shows how to convert Xilinx Vivado XDC timing constraints for clock domain crossings to the equivalent Quartus Prime Pro Edition Timing Analyzer SDC timing constraints.

Table 65. Vivado XDC versus Timing Analyzer SDC Timing Constraints for Clock Domain Crossing

| Vivado XDC Timing Constraint | Timing Analyzer SDC Command | Description | |--------------------------------|--------------------------------|-------------------------------------------------------------------------------------------------------------------------------------| | set_clock_groups -asynchronous | set_clock_groups -asynchronous | Removes the timing paths between two asynchronous clock domains. | | set_bus_skew | set_max_skew | Constrains the skew within bits on a bus. This constraint ensures that related data arrives together. | | set_max_delay -datapath_only | set_data_delay | Sets a maximum delay on a path, not including clock skew. This constraint ensures that data arrives in a reasonable amount of time. |

4.3.4. Retimer Constraints

In the Quartus Prime Pro Edition Software, the Fitter's Retime stage moves (retimes) existing registers into Hyper-Registers for fine-grained performance improvement (available in Stratix 10 and Agilex 7 devices). AMD Xilinx devices do not have HyperRegisters in their architecture, hence the existing Vivado based designs do not have equivalent constraints.

Related Information

Hyper-Aware Design Flow on page 44

4.4. Setting Up the Simulation Environment

Quartus Prime Pro Edition software supports RTL and gate-level design simulation in the EDA simulators listed in the table. Unless you use a simulator specific to AMD Xilinx, the simulation environment in the Quartus Prime Pro Edition is similar. The AMD Xilinx environment also supports all the following EDA simulators:

Table 66. Supported Simulators

| Simulation Tools | Version | |-----------------------------------|------------------------------| | Aldec* Active-HDL* | 15.0 (Windows* only) | | Aldec Riviera-PRO* | 2024.10 | | Cadence* Xcelium* Logic Simulator | 24.09.004 (Linux* only) | | Questa-Altera FPGA Edition | 2025.2 | | Siemens* EDA Questa SIM | 2025.2 | | Synopsys VCS* | W-2024.09-SP2-4 (Linux only) |

For more information about Questa - Altera FPGA Edition software refer to the Questa-Altera FPGA Edition Software page of the Altera FPGA website.

Related Information

Questa - Altera FPGA Edition Software
Questa-Altera FPGA Edition Quick-Start: Quartus Prime Pro Edition

4.4.1. Simulation Levels

The Quartus Prime Pro Edition software supports RTL and gate-level simulation in the supported EDA Simulators.

If you use the Questa - Altera FPGA Edition Simulator in a design that includes deep levels of hierarchy, turn off the Maintain hierarchy EDA tools option. This action prevents the Compiler to generate a large number of module instances in post-fit or post-map netlist, thus exceeding the Questa - Altera FPGA Edition instance limitation. To access this option, click Assignments ➤ Settings ➤ EDA Tool Settings ➤ More Settings .

For information about Questa - Altera FPGA Edition Products, refer to the Questa Altera FPGA Edition page of the Altera FPGA website.

For information about supported simulation levels, refer to Quartus Prime Pro Edition User Guide: Third-party Simulation .

Related Information

Questa - Altera FPGA Edition Software
Supported Simulation Levels in Quartus Prime Pro Edition User Guide: Third-party Simulation

4.4.2. HDL Support for EDA Simulators

The Quartus Prime Pro Edition software provides the following HDL support for EDA simulators:

VHDL 1987 (IEEE Standard 1076-1987)
VHDL 1993 (IEEE Standard 1076-1993)
VHDL 2008 (IEEE Standard 1076-2008)
VHDL 2019 (IEEE Standard 1076-2019) (23)
Verilog-1995 (IEEE Standard 1364-1995)
Verilog-2001 (IEEE Standard 1364-2001)
SystemVerilog-2005 (IEEE Standard 1800-2005)
SystemVerilog-2009 (IEEE Standard 1800-2009)

(23) The following VHDL 2019 features are supported:

○ Conditional analysis tool directives (IEEE Std 1076-2019 Section 24.2)

○ Interface declarations (IEEE Std 1076-2019 Section 6.5)

4.4.3. Value Change Dump (VCD) Support

All the EDA simulators that the Quartus Prime Pro Edition software support, besides other third-party simulators can generate .vcd files. The Quartus Prime Pro Edition Power Analyzer tool can read .vcd files for power measurements.

4.4.4. Simulating Altera FPGA IP Cores

The Quartus Prime software supports IP core RTL simulation in specific EDA simulators. IP generation creates simulation files, including the functional simulation model, any testbench (or example design), and vendor-specific simulator setup scripts for each IP core. Use the functional simulation model and any testbench or example design for simulation. IP generation output may also include scripts to compile and run any testbench. The scripts list all models or libraries you require to simulate your IP core.

The Quartus Prime software provides integration with many simulators and supports multiple simulation flows, including your own scripted and custom simulation flows.

Related Information

Simulating IP Cores in Quartus Prime Pro Edition User Guide: Third-party Simulation

5. Conclusion

The Quartus Prime software provides a complete design environment that you can easily adapt to your design for the development of Altera FPGAs and CPLD devices.

Programmable logic design and compilation flow is very similar between Quartus Prime software and AMD Xilinx Vivado software, and in most cases, you can easily import a Vivado design into the Quartus Prime software design environment. You can improve your design conversion experience by following the design conversion guidelines and considerations discussed in this application note, including migrating a design targeted at a AMD Xilinx device to one that is compatible with an Altera FPGA device.

*Other names and brands may be claimed as the property of others.

6. AN 307: Altera FPGA Design Flow for AMD Xilinx Users Archives

For the latest and previous versions of this application note, refer to AN 307: Altera FPGA Design Flow for AMD Xilinx Users . If a software version is not listed, the application note for the previous software version applies.

*Other names and brands may be claimed as the property of others.

7. Document Revision History for Altera FPGA Design Flow for AMD Xilinx Users

| Document Version | Quartus Prime Version | Changes | |--------------------|-------------------------|------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | 2026.01.05 | 24.1 | • Revised Toolkit Explorer . • Updated the Device Family Comparison table: ○ Added Zynq UltraScale+ (lower densities), Artix UltraScale+, and Spartan UltraScale+ in the Xilinx Devices column for mid-range applications. ○ Removed Stratix 10 devices from the Altera Devices column for mid-range applications. • Added Agilex 3 devices support. | | 2023.04.01 | 24.1 | • Added information for Agilex 5 devices | | 2023.09.08 | 23.2 | • Added information about DSP register packing restrictions to 'Design Implementation'. • Renamed "Xilinx" to "AMD Xilinx" where needed. | | 2022.02.25 | 21.3 | • Revised content for Quartus Prime Pro Edition software version 21.3 and Xilinx Vivado Design Suite version 2020.2. • Updated the ECC Parity Flip (Stratix 10 Devices only) topic to correct the parity bit sequence for double-adjacent-error correction. • Removed the set_clock_groups section. The include_generated_clocks switch of the set_clock_groups constraint has been supported by Quartus Prime Pro Edition since Version 19.3. | | 2020.08.24 | 17.1.0 | • Added a link to Converting Xilinx RAM initialization .coe/.mif Format to Intel PSG .mif/.hex Format in the Memory Initialization topic. | | 2018.03.20 | 17.1.0 | • Revised content for Quartus Prime Pro Edition software version 17.1 and Xilinx Vivado Design Suite version 2017.2. • Added chapter that compares latest devices. • Updated for latest Altera naming conventions. | | May 2015 | 2015.05.11 | • Updated content for DSE II • Updated GUI screenshots to v15.0 • Removed obsolete devices not supported in v15.0 • Removed MegaWizard Plug-in Manager content and replaced with IP Catalog/Parameter Editor content • Updated links | | March 2013 | 7.0 | • Revised content for software versions ISE 14.2 and Quartus II 12.1 • Removed outdated design examples. • Updated template | | November 2009 | 6.2 | Corrected set_max_delay constraint equivalents for OFFSET IN BEFORE and OFFSET OUTPUT AFTER UCF commands in Timing Constraints section. | | April 2009 | 6.2 | Added Appendix A: Design Example and Appendix B | | continued... | continued... | continued... |

AN-307 | 2026.01.05

Metadata

SourceAN 307: Altera FPGA Design Flow for Xilinx Users

Tokens68,932

Chunks245

Chunks (245)

#030 tokens

## AN 307: Altera ® FPGA Design Flow for AMD* Xilinx* Users Updated for Quartus ® Prime Design Suite: 24.1

#11250 tokens

## Contents | 1. Introduction to Altera FPGA Design Flow for AMD* Xilinx* Users................................. | 4...

#21247 tokens

## Contents Static Timing Analysis...............................................................................32 | ...

#3311 tokens

## Contents Converting Multipliers...............................................................................75 | ...

#4453 tokens

## Contents | 4.3.4. Retimer Constraints..................................................................................87 ...

#5563 tokens

## 1. Introduction to Altera ® FPGA Design Flow for AMD* Xilinx* Users Designing for Altera ® FPGA devices is similar in concept and practice to designing for AMD* Xilinx* FPGA devices. In most cas...

#6536 tokens

## 2.1. Altera FPGA and SoC Devices Altera FPGA devices are ideal for a wide variety of applications, from prototyping state-of-the-art new products all the way through to high-volume production. Alt...

#7422 tokens

## Table 1. Altera FPGA Family Technologies and Architectures | Altera FPGA Family | Technology | Architecture | |--------------------------------|----------------|----------------|...

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## 2.2. Altera-AMD Xilinx Device Comparison - Enabling Next-Generation Platforms Using Altera's 3D System-in-Package Technology White Paper - Achieving the Highest Levels of Integration in Programm...

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## Table 2. Device Family Comparison | Application | Xilinx Devices | Altera Devices ...

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## AN-307 | 2026.01.05 | Application | Xilinx Devices | Altera Devices | |---------------|----------------------------------------...

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## Table 3. Agilex 7 Device Features Altera Product Performance: FPGA - Performance Index | Performance (1) | Built on Altera 10nm SuperFin technology with second generation Hyperflex ® a...

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## Table 4. Stratix 10 Device Features | Performance | Built on the Altera 14 nm Tri-Gate process, Stratix 10 devices deliver 2X core performance gains over previous-generation, high-pe...

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## Table 5. Arria 10 Device Features | Performance | A speed grade faster core performance and up to a 20% fMAX advantage compared to the competition, using publicly-available Altera FPGA IP Eval...

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## Table 6. Cyclone 10 GX Device Features | Industry's first | Low-cost FPGA with IEEE 754-compliant hard floating-point DSP blocks | |----------...

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## 3. FPGA Tools Comparison AN-307 | 2026.01.05 - Altera FPGA Products Overview - Altera SoC Products Overview - Arria 10 Performance Benchmarking Methodology and Results The Quartus Prime ...

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## 3.1. Hardware and Software Tools for FPGA Design The Quartus Prime Pro Edition software provides tools similar to those found in the AMD Xilinx Vivado software. The following table shows AMD Xilin...

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## Table 7. Hardware and Software Tools Available | AMD Xilinx | Altera ...

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## AN-307 | 2026.01.05 | AMD Xilinx | Altera | Description ...

#19347 tokens

## 3.2. FPGA Design Flow Using Command Line Scripting - Altera FPGA Development Tools - AMD Xilinx Vivado Design Suite Automating the FPGA design process saves time and increases productivity. The ...

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## The Hyper-Aware Design Flow The Hyper-Aware Design Flow allows you to take full advantage of the Hyperflex architecture provided on Agilex 7 and Stratix 10 devices. This flow combines automated re...

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## Related Information - Altera Hyperflex Architecture High-Performance Design Handbook - Quartus Prime Pro Edition User Guide: Design Compilation - Quartus Prime Pro Edition User Guide: Scripting - ...

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## 3.2.1. Command-Line Executable Equivalents The table and following sections describe and compare the two software flows using command line executables. The examples belong to the fir\_filter desig...

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## 3. FPGA Tools Comparison | AMD Xilinx Vivado Software | AMD Xilinx Vivado Software | Quartus Prime Pro Edition Software | Description...

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## 3.2.1.1. synth\_design Start this browser by typing quartus\_sh --qhelp at the command prompt. In the Quartus Prime Pro Edition command-line flow, the quartus\_syn executable performs both syn...

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## 3.2.1.2. place\_design/route\_design Depending on the use mode, the Vivado software provides different commands to place and route device resources into the FPGA device. In Project Mode, the launc...

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## 3.2.1.3. report\_timing In place of the report\_timing\_summary executable that the Vivado software provides for performing a static timing analysis on your design, the Quartus Prime Pro Edition s...

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## 3.2.1.4. write\_bitstream - Timing Constraints on page 86 - Create Timing Constraints with the Timing Analyzer Text Editor on page 27 The Vivado software provides the write\_bitstream executable...

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## 3.2.1.5. write\_sdf/write\_verilog/write\_vhdl In Vivado, the write\_sdf executable reads data from design files, and writes timing delays in .sdf files. The write\_verilog executable uses this ou...

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## 3.2.1.6. report\_power The report\_power executable provides power and thermal estimates after place and route to estimate a design's power consumption. Similarly, quartus\_pow estimates the therm...

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## 3.2.1.7. write\_checkpoint Value Change Dump (VCD) Support on page 89 In Vivado, the write\_checkpoint command allows you to save a project at any point in the design process. In the Quartus Pri...

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## 3.2.1.8. Run Complete Design Flow - Design Optimization on page 44 - Exporting Compilation Results in Quartus Prime Pro Edition User Guide: Design Compilation - Partition Snapshot Preservation and...

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## 3.2.2. Programming and Configuration File Support in the Quartus Prime Pro Edition Software Quartus Prime Pro Edition User Guide: Scripting The Quartus Prime Pro Edition software requires differ...

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## Table 9. GUI Feature Equivalents Quartus Prime Pro Edition User Guide: Programmer The Quartus Prime Pro Edition and the Vivado software GUIs address the major FPGA design steps in different ways...

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## AN-307 | 2026.01.05 | GUI Feature | AMD Xilinx Vivado Software | Quartus Prime Pro Edition Software ...

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## AN-307 | 2026.01.05 | Integrated Logic Analyzer (ILA) and System ILA IP | Signal Tap Logic Analyzer ...

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## AN-307 | 2026.01.05 | GUI Feature | AMD Xilinx Vivado Software | Quartus Prime Pro Edition Software | |------------------------------------|-----------------------------...

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## Table 10. IP Status Comparison | GUI Feature | AMD Xilinx Vivado Software | Quartus Prime Pro Edition Software | |------------------|------------------------------|-----------------------...

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## Table 11. Project Files Comparison After creating a new project, the Quartus Prime Pro Edition software automatically generates the following project files necessary for successful compilation: ...

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## Features You can modify the compiler settings by changing the assignments through the GUI or directly on the .qsf file. Note: Avoid modifying assignments through the .qsf file and through the GU...

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## 3.3.2. Design Entry The Quartus Prime software supports all the design entry methods that the Vivado software supports. Table 12. Design Entry Methods Comparison | GUI Feature | AMD Xilinx Viv...

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## Managing Project Files In the AMD Xilinx Vivado software, you use the Add Source dialog box to add or remove existing design files. To add or remove existing design files from a project in the Qua...

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## 3.3.2.1. HDL Editor In the Vivado software you create a new HDL design file using the New Source Wizard on the Project menu. To create a new HDL design file in the Quartus Prime Pro Edition softwa...

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## 3.3.2.2. Schematic/Block Editor Quartus Prime Pro Edition User Guide: Design Recommendations In the Quartus Prime Pro Edition software, you can use Altera FPGA-supplied design elements, su...

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## 3.3.2.3. State Machine Editor The Quartus Prime Pro Edition software supports graphical state machine entry. To create a new finite state machine (FSM) design: 1. Click File ➤ New . 2. In the New...

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## 3.3.2.4. IP Catalog and Parameter Editor Use the IP Catalog to generate Altera FPGA equivalents for AMD Xilinx primitives and IP Catalog cores. To display the IP Catalog in the Quartus Prime Pro E...

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## Features of the IP Catalog - Allows you to create custom IP cores that are optimized for the design's target device. - Altera provides a library-of parameterized-modules (LPM). This library offers...

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## 3.3.2.5. Platform Designer System Integration Tool - IP Catalog and Parameter Editor in Quartus Prime Pro Edition Help - Altera FPGA IP Cores/LPM in Quartus Prime Pro Edition Help Similar to AMD...

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## Features Platform Designer enables the use of processors (such as the Altera FPGA Nios II embedded processor), interfaces to off-chip processors, standard peripherals, IP cores, on-chip memory, of...

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## Migration When migrating from AMD Xilinx to Altera FPGA, one of the main differences to consider while creating systems is the standard bus interface: - AMD Xilinx uses AMBA* AXI as the standard ...

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## Related Information - Creating a System with Platform Designer in Quartus Prime Pro Edition User Guide: Platform Designer - Platform Designer Transformations in Quartus Prime Pro Edition User Guid...

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## 3.3.2.6. Platform Designer Component Editor In the Vivado software, you can use the IP Packager to add custom IPs to the IP catalog. In the Quartus Prime Pro Edition software, you create and packa...

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## 3.3.3. IP Status Creating Platform Designer Components in Quartus Prime Pro Edition User Guide: Platform Designer When migrating a project in the Vivado software, the Report IP Status window dis...

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## Table 13. IP Status Tools Comparison | GUI Feature | AMD Xilinx Vivado Software | Quartus Prime Pro Edition Software | |---------------|------------------------------|-----------------------...

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## 3.3.4. Design Constraints Upgrade IP Components Dialog Box (Project Menu) in Quartus Prime Pro Edition Help The Vivado software provides GUI editors (Device/Physical/Timing windows) to create ...

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## Features The table summarizes the file format and assignment types that the tools in the Quartus Prime Pro Edition software set. Table 15. Quartus Prime Pro Edition Assignment Tools | Assignment...

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## 3.3.4.1. Assignment Editor Quartus Prime Pro Edition User Guide: Design Constraints The Quartus Prime Assignment Editor ( Assignments ➤ Assignment Editor ) allows you to add device and placement...

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## 3.3.4.2. Create Timing Constraints with the Timing Analyzer GUI Assignment Editor (Assignments Menu) in Quartus Prime Pro Edition Help To create timing constraints with the Timing Analyzer GUI: ...

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## AN-307 | 2026.01.05 4. Enter the values in the dialog box, and click Insert to insert the SDC command into the open SDC file. 5. Save the updated SDC file. The constraints are available on the Co...

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## 3.3.4.3. Create Timing Constraints with the Timing Analyzer Text Editor Constraints in Quartus Prime Pro Edition Help The Quartus Prime Timing Analyzer ( Tools ➤ Timing Analyzer ) reads and writ...

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## 3.3.5. Synthesis - Timing Analyzer Cookbook - Quartus Prime Pro Edition User Guide: Timing Analyzer The Quartus Prime Pro Edition Synthesis provides full support for VHDL, Verilog HDL, SystemVer...

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## Table 16. Synthesis Comparison | GUI Feature | AMD Xilinx Vivado Software | Quartus Prime Pro Edition Software | |---------------|------------------------------|-----------------------------...

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## Features The Quartus Prime Pro Edition Synthesis engine enforces strict industry-standard HDL structures. Synthesis supports Verilog Quartus Mapping ( .vqm ) files generated by third-party EDA to...

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## Access The Assignments ➤ Settings ➤ IP Settings dialog box allows you to control the IP regeneration stage for synthesis or simulation The Assignments ➤ Settings ➤ Compiler Settings ➤ Advanced Se...

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## Related Information - Design Synthesis in Quartus Prime Pro Edition User Guide: Design Compilation - Quartus Prime Pro Edition User Guide: Third-party Synthesis - Generating a VQM Netlist for othe...

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## 3.3.6. Design Implementation The implementation flow in the Vivado software places and routes the netlist onto the FPGA device resources based on the constraints of the design. The Finalize flow i...

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## Table 17. Design Implementation Comparison | GUI Feature | AMD Xilinx Vivado Software | Quartus Prime Pro Edition Software | |-----------------------|---------------...

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## Features The Quartus Prime Pro Edition Compiler offers unique features, such as: - Snapshot Viewer-analyze the results of a compilation snapshot to evaluate the design before running the next sta...

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## Limitations The Assignments ➤ Settings ➤ Compiler Settings ➤ Advanced Settings (Fitter) dialog box allows you customize the place and route of the compilation flow. DSP register packing in Quart...

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## Related Information - Compilation Dashboard in Quartus Prime Pro Edition Help - Fitter Settings Reference in Quartus Prime Pro Edition User Guide: Design Compilation - Concurrent Analysis During S...

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## 3.3.7. Finalize Pinout In the Vivado software, you can use the I/O Planning View Layout to finalize the pinout. For I/O planning of Memory Interfaces, the Vivado software uses the Memory Bank/Byte...

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## Table 18. Finalize Pinout Comparison | GUI Feature | AMD Xilinx Vivado Software | Quartus Prime Pro Edition Software ...

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## 3.3.7.1. Pin Planner The Quartus Prime Pro Edition Pin Planner provides a graphical package view, allowing you to validate I/O assignments by performing legality checks on a design's I/O pins and ...

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## 3.3.7.2. Interface Planner To invoke the Pin Planner, click Assignments ➤ Pin Planner Managing Device I/O Pins in Quartus Prime Pro Edition User Guide: Design Constraints The Vivado software...

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## 3.3.7.3. Tile Interface Planner Interface Planning in Quartus Prime Pro Edition User Guide: Design Constraints Tile Interface Planner helps quickly place component IP in legal tile locations on ...

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## 3.3.8. Viewing and Editing Design Placement Using Tile Interface Planner in Quartus Prime Pro Edition User Guide: Design Constraints The Vivado software provides the Device Window for floorplann...

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## 3.3.9. Static Timing Analysis To open the Chip Planner, click Tools ➤ Chip Planner . The Report Timing Summary in Vivado generates the Post-Place and Post-Route Static Timing Report. Similarly, ...

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## Table 20. Static Timing Analysis Methods Comparison | GUI Feature | AMD Xilinx Vivado Software | Quartus Prime Pro Edition Software | |------------------------|---------------------...

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## Figure 10. Timing Analyzer GUI AN-307 | 2026.01.05 The major difference between performing timing analysis with the Report Timing Summary in Vivado and the Altera FPGA Timing Analyzer is that in...

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## Access Static timing analysis with the Timing Analyzer is part of the full compilation flow, but you can also run the module separately. To run the Timing Analyzer over a post-fit netlist, click ...

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## 3.3.10. Generation of Device Programming Files - Timing Analyzer Cookbook - Quartus Prime Pro Edition User Guide: Timing Analyzer Similar to the Hardware Manager in the AMD Xilinx Vivado softwar...

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## Features The Assembler converts the Fitter's device, logic cell, and pin assignments into a programming image for the device, in the form of one or more Programmer Object Files ( .pof ) or SRAM Ob...

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## 3.3.11. Power Analysis Quartus Prime Pro Edition User Guide: Programmer Similar to the AMD Xilinx Power Estimator and Report Power tool, Altera provides tools that allow you to estimate power co...

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## 3.3.12. Simulation - Power Estimators and Power Analyzer - Quartus Prime Pro Edition User Guide: Power Analysis and Optimization - Altera FPGA Power and Thermal Calculator User Guide Both the AM...

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## Table 23. Simulation Support Comparison | GUI Feature | AMD Xilinx Vivado Software | Quartus Prime Pro Edition Software | |---------------|------------------------------|--------------------...

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## Access To specify third-party simulation tools in the Quartus Prime Pro Edition software: 1. Click Assignments ➤ Settings . 2. In Category , click EDA Tool Settings . 3. Under Simulation select t...

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## Functional Simulation EDA Interface Information in Quartus Prime Pro Edition Software and Device Support Release Notes The Quartus Prime Pro Edition software provides functional simulation model...

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## Table 24. Simulation Model Files | | Verilog HDL | VHDL | |----------|---------------|----------------------------------------| | LPM | 220model.v...

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## Gate-level Functional Simulation To perform gate-level functional simulation on a design, the Quartus Prime Pro Edition software generates output netlist files containing information about how the...

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## Table 25. Generated Output Files | | Extension | |-------------------------|-------------| | Verilog HDL output file | .vo | | VHDL output file | .vho ...

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## 3.3.13. Hardware Verification AMD Xilinx offers solutions for hardware debugging that have equivalent tools in Altera FPGA software. In contrast, not all Altera FPGA debug solutions have an equiva...

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## 3.3.13.1. System Console AMD Xilinx Vivado software's Hardware Manager provides a TCL console to interact with the debug IP on the hardware. Similarly, in the Quartus Prime software, you can perfo...

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## 3.3.13.2. Signal Tap Logic Analyzer Analyzing and Debugging Designs with System Console in Quartus Prime Pro Edition User Guide: Debug Tools The Vivado software includes the Integrated Logic A...

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## 3.3.13.3. In-System Sources and Probes Design Debugging with the Signal Tap Logic Analyzer in Quartus Prime Pro Edition User Guide: Debug Tools The Vivado software provides the Virtual Input/Out...

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## 3.3.13.4. Toolkit Explorer Design Debugging Using In-System Sources and Probes in Quartus Prime Pro Edition User Guide: Debug Tools For designs with debug-enabled IP, the Toolkit Explorer automa...

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## External Memory Interfaces (EMIF) Toolkits For external memory interfaces, the following toolkits are available: - EMIF Debug Toolkit This toolkit helps you to debug external memory interfaces b...

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## Table 30. Available EMIF Toolkits | Toolkit | Supported Device Families | Documentation ...

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## Table 31. Available Ethernet Toolkits The Ethernet Toolkit is a TCL-based debugging tool that allows you to interact with an Ethernet Altera FPGA IP in real time. | Toolkit | Supporte...

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## PCI Express Debug Toolkits The PCI Express (PCIe) debug toolkits are System Console-based tools that provide real-time control, monitoring, and debugging of the PCIe links at the Physical, Data Li...

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## Serial Lite IV IP Toolkit The Serial Lite IV IP Toolkit is an inspection tool that monitors the status of a Serial Lite IV IP link and provides a step-by-step guide for the IP link initialization ...

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## Transceiver PHY Toolkits Transceiver PHY toolkits help you to optimize high-speed serial links in your board design by providing real-time control, monitoring, and debugging of the transceiver lin...

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## Related Information - in System Console in Quartus Prime Pro Edition User Guide: Debug Tools - External Memory Interfaces IP User Guide: Agilex 3 FPGAs and SoCs - External Memory Interfaces IP Use...

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## 3.3.13.4.1. Transceiver Toolkit - Ethernet Link Inspector User Guide for Stratix 10 Devices - Stratix 10 Configuration User Guide The Vivado software uses IBERT IP along with the serial I/O anal...

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## Table 34. Transceiver Toolkit Features and Usage | Features ...

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## 3.3.13.4.2. EMIF Debug Toolkit in System Console in Quartus Prime Pro Edition User Guide: Debug Tools In the Vivado software, the Memory Calibration Debug tool allows you to debug calibration or...

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## Table 35. EMIF Debug Toolkit Features and Usage | Features ...

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## 3.3.13.5. Remote Debugging in System Console in Quartus Prime Pro Edition User Guide: Debug Tools You can perform remote debugging of a system with the Quartus Prime software via the System Cons...

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## 3.3.13.6. Other Altera FPGA Debugging Tools - Analyzing and Debugging Designs with System Console in Quartus Prime Pro Edition User Guide: Debug Tools - Application Note 624: Debugging with System...

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## Table 36. Signal Probe Features and Usage | Features | Typical Usage ...

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## Table 37. Logic Analyzer Interface Features and Usage | Features ...

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## Table 38. In-System Memory Content Editor Features and Usage | Features | Typical Usage ...

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## Related Information - Quick Design Verification with Signal Probe in Quartus Prime Pro Edition User Guide: Debug Tools - In-System Debugging Using External Logic Analyzers in Quartus Prime Pro Edi...

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## 3.3.14. View Netlist Similar to the Netlist Window and Schematic Window features available in the Vivado software to generate logical or physical hierarchy, the Quartus Prime Pro Edition RTL Viewe...

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## Table 39. View Netlist Methods Comparison | GUI Feature | AMD Xilinx Vivado Software | Quartus Prime Pro Edition Software ...

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## 3.3.14.1. RTL Viewer Snapshot Viewer on page 47 To run the RTL Viewer for an Quartus Prime Pro Edition project: 1. Click Processing ➤ Start ➤ Start Analysis & Elaboration to generate a RTL ...

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## 3.3.14.2. Technology Map Viewer RTL Viewer Overview in Quartus Prime Pro Edition User Guide: Design Optimization The Technology Map Viewer is a detached window that provides a graphical represen...

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## 3.3.15. Design Optimization Technology Map Viewer Overview in Quartus Prime Pro Edition User Guide: Design Optimization The Quartus Prime software offers advanced netlist optimization opti...

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## Table 40. Design Optimization Tools Comparison | GUI Feature | AMD Xilinx Vivado Software | Quartus Prime Pro Edition Software | |---------------------|------------------------------|-...

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## 3.3.15.1. Hyper-Aware Design Flow Use the Hyper-Aware design flow to shorten design cycles and optimize performance for designs targeting Agilex 7 and Stratix 10 devices. The Hyper-Aware design fl...

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## 3.3.15.2. Physical Synthesis Optimization - Optimize Critical Chains in Quartus Prime Pro Edition User Guide: Design Optimization - Fast Forward Compilation Flow in Quartus Prime Pro Edition User ...

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## 3.3.15.3. Optimization Modes By default, Quartus Prime Pro Edition uses a balanced optimization strategy that respects timing constraints. It can use other high-level strategies to optimize for pe...

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## 3.3.15.4. Fractal Synthesis Optimization Modes in Quartus Prime Pro Edition User Guide: Design Compilation Fractal Synthesis optimizations can be used for deep-learning accelerators and other hi...

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## 3.3.16. Techniques to Improve Productivity Fractal Synthesis Optimization in Quartus Prime Pro Edition User Guide: Design Compilation Table 41. Techniques to Improve Productivity Comparison | G...

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## 3.3.16.1. Fast Preservation In Xilinx Vivado designs, the Incremental Compile design flow speeds up place and route runtime. In Quartus Prime Pro Edition, enabling the Fast Preserve option on the...

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## 3.3.16.2. Engineering Change Order (ECO) Flow AN 899: Reducing Compile Time with Fast Preservation The Xilinx Vivado Engineering Change Order (ECO) flow allows you to modify a postimplementation...

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## 3.3.16.3. Block-Based Design Flow Using the ECO Compilation Flow in Quartus Prime Pro Edition User Guide: Design Optimization In the Vivado software, the Hierarchical Design flow allows you to p...

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## 3.3.16.4. Design Assistant Quartus Prime Pro Edition User Guide: Block Based Design Xilinx Vivado has a Report Design Rule Checking (DRC) feature that checks design rules on a synthesized or i...

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## 3.3.16.5. Snapshot Viewer - Design Assistant Design Rule Checking in Quartus Prime Pro Edition User Guide: Design Recommendations - Design Assistant Rules List in Quartus Prime Pro Edition Help ...

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## 3.3.16.6. Design Space Explorer II Altera's Design Space Explorer II (DSE II) tool allows you to find optimal project settings for resource, performance, or power optimization goals. Design Space...

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## 3.3.17. Partial Reconfiguration Optimize Settings with Design Space Explorer II in Quartus Prime Pro Edition User Guide: Design Optimization Partial Reconfiguration (PR) allows for the dynamic r...

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## Related Information - Quartus Prime Pro Edition User Guide: Partial Reconfiguration - AN 797: Partially Reconfiguring a Design: on Arria 10 GX FPGA Development Board - AN 825: Partially Reconfigur...

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## 3.3.18. Cross-Probing in the Quartus Prime Pro Edition Software Cross-probing is the ability to select design elements from one tool and locate them in another tool. The integration between featur...

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## 3.4. Additional Quartus Prime Pro Edition Features In addition to providing the standard set of tools required in any FPGA design flow, the Quartus Prime Pro Edition software includes additional f...

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## 3.4.1. Scripting with Tcl in the Quartus Prime Pro Edition Software Quartus Prime Pro Edition User Guide: Scripting AN-307 | 2026.01.05 The Quartus Prime Pro Edition GUI provides an easy wa...

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## 3.4.1.1. Running Scripts from the DOS or UNIX Prompt The following command runs the Quartus Prime Tcl shell and uses the Tcl file specified by the -t option as the input Tcl script: ``` quartus_s...

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## 3.4.1.3. Running Tcl Commands Directly from the Command Line You can run Tcl scripts in a Tcl shell by typing: ``` source <script_name>.tcl ``` You can use the --tcl\_eval option to directly ev...

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## 1. For example, typing: ``` quartus_sh --tcl_eval puts Hello\; puts World Results in the following output: Hello World ``` The Tcl evaluate option allows external scripting programs (such as ...

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## 1. In a console, type: Using the -s or --shell switch option starts an interactive Tcl shell session, replacing the normal command line prompt with tcl , as shown in the following example: ``` q...

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## Example 1. Tcl Script You can execute Tcl commands directly in the Quartus Prime Tcl Console window. To open the Tcl Console window, click View ➤ Tcl Console . AN-307 | 2026.01.05 This exampl...

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## these tasks: - Opens the fir\_filter project, if it exists. If the project does not exist, the script creates the project. - Sets the project to target an Stratix 10 1SG280HU2F50E2VG device. - Ass...

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## 4. AMD Xilinx to Altera FPGA Design Conversion Quartus Prime Pro Edition User Guide: Scripting To successfully convert a AMD Xilinx-targeted design for use in an Altera FPGA device, you ...

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## 4.1. Replacing AMD Xilinx Primitives Project Creation on page 20 When migrating a design, you must convert common AMD Xilinx primitives to the Altera FPGA equivalents. Primitives are the basic b...

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## 4.1.1. Converting I/O Buffers Primitives in Quartus Prime Pro Edition Help The Quartus Prime Pro Edition Compiler inserts input, output, or bidirectional buffers automatically. To convert a des...

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## 4.1.1.1. Example of Converting I/O Buffer Buffers with selectable I/O standard I/O Standard Global buffers Global Signal Global buffer with I/O Standard I/O Standard In this example, the cl...

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## Example 2. Converting BUFG , IBUFG , and OBUF in Verilog HDL. Original Verilog HDL Code in the Vivado Software ``` module Top (a, b, c, clk); input a, b, clk; output c; reg c_buf; wire a_buf, b_b...

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## Converted Verilog HDL Code in the Quartus Prime Pro Edition Software ``` module Top (a, b, c, clk); input a, b, clk; output c; reg c_buf; wire a_buf, b_buf, clk_buf; assign clk_buf = clk; assign a...

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## Original VHDL Code in the Vivado Software ``` LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY buf_top IS PORT( a, b : IN STD_ULOGIC; clk : IN STD_ULOGIC; c : OUT STD_ULOGIC); END buf_top; ARCHIT...

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## Converted VHDL Code in the Quartus Prime Pro Edition Software ``` LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY Top IS PORT( a, b: IN STD_ULOGIC; clk: IN STD_ULOGIC; c: OUT STD_ULOGIC); END To...

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## Figure 11. Global Signal and I/O Standard Assignments Using the Assignment Editor In the figure, inputs a , b , and clk are assigned as global signals, with clk as the global clock. Input ports a ...

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## 4.1.2. Changing Default I/O Standard for Pins The default I/O standard for pins on the target device in the Quartus Prime Pro Edition software is device-specific. To change the default I/O standar...

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## 4.1.3. Converting Registers This table shows the nearest Altera equivalent to some common Xilinx storage primitives. Table 44. Nearest Altera Equivalent for Common Xilinx Storage Primitives | Xi...

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## 4.2. Converting IP Cores Storage Primitives in Quartus Prime Pro Edition Help This section describes how to convert IPs generated using the AMD Xilinx IP Catalog to IP cores generated with the Q...

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## 4.2.1. Converting Memory Blocks To convert AMD Xilinx memory blocks to Altera FPGA memory blocks, you must consider the embedded memory blocks in the target device, address the differences between...

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## 4.2.1.1. Embedded Memory Blocks - Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2PORT) User Guide - Stratix 10 Embedded Memory User Guide - Agilex 7 Embedded Memory User Guide ...

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## 4.2.1.2. Differences Between AMD Xilinx Memory and Altera FPGA Memory - Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2PORT) User Guide - Stratix 10 Embedded Memory User Guide -...

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## 4.2.1.2.1. Memory Mode AMD Xilinx memory and Altera FPGA memory support single-port RAM, simple dualport RAM, true dual-port RAM, single-port ROM, and dual-port ROM. In addition, Altera FPGA supp...

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## 4.2.1.2.2. Clocking Mode - Memory Port Mapping on page 65 - Inferring Memory Functions from HDL Code in Quartus Prime Pro Edition User Guide: Design Recommendations In Altera FPGAs, the clock mo...

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## Table 46. Clocking Mode | Altera FPGA Clocking Mode | Description | Comment ...

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## Related Information - Clocking Modes and Clock Enable in Embedded Memory (RAM: 1-PORT, RAM: 2PORT, ROM: 1-PORT, and ROM: 2-PORT) User Guide - Stratix 10 Embedded Memory Clocking Modes in Stratix 1...

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## 4.2.1.2.3. Write and Read Operation Triggering Ensure to resolve potential write contentions external to the RAM, because writing to the same address location at both ports results in unknown data...

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## Related Information - Write and Read Operations Triggering in Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2-PORT) User Guide - Stratix 10 Embedded Memory Design Considerations...

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## Figure 12. Read-During-Write Data Flow There are two types of read-during-write operations: same-port operations and mixed-port operations. The same-port read-during-write mode applies to either...

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## 4.2.1.2.5. Error Correction Code (ECC) AMD Xilinx and Altera FPGA RAMs use Error Correction Code (ECC) to detect errors in the memory array, and present the corrected single-bit error data on the ...

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## ECC Parity Flip ALTECC (Error Correction Code: Encoder/Decoder) IP Core in Altera FPGA Integer Arithmetic IP Cores User Guide The ECC parity flip feature is available only on Agilex 7 and Strati...

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## 4.2.1.2.6. Byte Enable To ensure that the operation writes only specific bytes of data, embedded memory blocks support the byte enable property, that masks the input data. The unwritten bytes or b...

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## 4.2.1.2.6. Byte Enable | Differences | AMD Xilinx RAM ...

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## 4.2.1.2.6. Byte Enable | ...

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## 4.2.1.2.6. Byte Enable | Output depends on read-during- write configuration: • WRITE_FIRST • READ_FIRST • NO_CHANGE | ...

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## Related Information - Read-During-Write Operation at the Same Address on page 59 - Byte Enable in Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2-PORT) User Guide - Byte Enable ...

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## 4.2.1.2.7. Address Clock Enable Altera FPGA memory supports the address clock enable feature. The address clock enable holds the previous address value for as long as addressstall is enabled. AMD ...

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## Related Information - Memory Blocks Address Clock Enable Support in Embedded Memory (RAM: 1PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2-PORT) User Guide - Address Clock Enable Support in Stratix 10 ...

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## 4.2.1.2.8. Parity Bit Support Embedded memory blocks in Altera FPGAs have built-in parity-bit support for each byte. While AMD Xilinx memories support separate input and output buses for parity bi...

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## 4.2.1.2.9. Memory Initialization - Parity Bit in Stratix 10 Embedded Memory User Guide - Parity Bit in Agilex 7 Embedded Memory User Guide In Altera FPGA devices, all embedded memory blocks supp...

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## Related Information - Hexadecimal (Altera-Format) File (.hex) Definition in Quartus Prime Pro Edition Help - Memory Initialization File (.mif) Definition in Quartus Prime Pro Edition Help - Conver...

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## 4.2.1.2.10. Output Synchronous Set/Reset AMD Xilinx memory supports optional synchronous set/reset pins that control the reset operation of the last register in the output stage. This ability init...

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## 4.2.1.3. Determining Memory Block and Mapping Ports 1. If you are not sure which memory block to select, or are not particular about the memory block type, select AUTO in the IP Catalog/Parameter ...

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## Table 51. Memory Modes/Functions and Related Plug-In | Memory Modes/Function | Plug-In | |---------------------------------------------------------...

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## 4.2.1.4. Memory Port Mapping Fitter Feature Specific Reports in Quartus Prime Pro Edition Help (18) simple quad-port RAM was removed from mostStratix 10 devices The following table lists the ...

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## 4.2.1.4. Memory Port Mapping | Port Description | AMD Xilinx Ports | Port-Mapping to Altera FPGA Ports in Different Memory Modes | Port-Mapping to Altera F...

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## 4.2.1.4. Memory Port Mapping a/ rden | rden | rden_a ...

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## 4.2.1.4. Memory Port Mapping | Port Description | AMD Xilinx Ports | Port-Mapping to Altera FPGA Ports in Different Memory Modes | Port-Mapping to Altera F...

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## 4.2.1.4. Memory Port Mapping b | NA | NA ...

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## 4.2.1.4. Memory Port Mapping | Port Description | AMD Xilinx Ports | Port-Mapping to Altera FPGA Ports in Different Memory Modes | Port-Mapping to Altera FPGA Ports in Different Memo...

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## 4.2.1.5. Example: Converting Simple Dual-Port RAM - Memory Mode on page 58 - Inferring Memory Functions from HDL Code in Quartus Prime Pro Edition User Guide: Design Recommendations This example...

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## Table 53. Properties of Simple Dual-Port RAM | Input data width | 16 bits | |----------------------------|----------------------------------------| | Memor...

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## The original Verilog HDL Code in the Vivado Software is: ``` module test( input clka, input ena, input [0:0]wea, input [2:0]addra, input [15:0]dina, input clkb, input enb, input [2:0]addrb, output...

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## The original VHDL Code in the Vivado Software is: ``` LIBRARY ieee; USE ieee.STD_LOGIC 1164.all; LIBRARY work; ENTITY test IS port ( clka: IN STD_LOGIC; ena: IN STD_LOGIC; wea: IN STD_LOGIC_VECTOR...

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## The original VHDL Code in the Vivado Software is: | How will you be using the dual port RAM? | How will you be using the dual port RAM? | How will you be using the dual port RAM? ...

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## The original VHDL Code in the Vivado Software is: | | ...

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## The original VHDL Code in the Vivado Software is: AN-307 | 2026.01.05 The converted Verilog HDL code in the Quartus Prime Software after instantiating the new RAM: ``` module test( input clka, i...

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## 4.2.2. Converting Mixed-Mode Clock Manager (MMCM) to Phase-Locked Loop (PLL) - RAM: 2-PORT IP Core Parameters in Stratix 10 Embedded Memory User Guide - RAM: 2-PORT IP Core Parameters in Agilex 7...

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## 4.2.2.1. Feature Comparison The following table compares MMCM features in UltraScale+ with PLL features in Stratix 10 devices. Table 55. MMCM in UltraScale+ versus PLL in Stratix 10 Devices | Fe...

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## 4.2.2.2. Port Mapping Reference The following table shows the mapping between MMCM UltraScale ports, created with the AMD Xilinx IP Catalog, and PLL ports in Stratix 10 device, created with the IP...

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## 4.2.2.2. Port Mapping Reference | AMD Xilinx MMCM Core Port | Altera FPGA Altera FPGA IOPLL IP Core Port | Description ...

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## 4.2.2.2. Port Mapping Reference | | clkinstopped | clkbad[1..0] ...

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## 4.2.2.3. Example: Converting AMD Xilinx MMCM into an Altera PLL - IOPLL IP Core User Guide - Stratix 10 Clocking and PLL User Guide - Agilex 7 Clocking and PLL User Guide This example uses a mym...

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## Table 57. Example Parameters | Parameter | Value | |--------------------------------------|--------------------------| | Input Clock Frequency ...

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## Original Verilog Code in the Vivado Software: ``` module top( // Clock out ports output clk_out1, output clk_out2, input reset, output locked, // Clock in ports input clk_in1 ); mymmcm i1 ( .reset...

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## Table 58. Parameters of mypll 2. Generate an IP variant named mypll . 3. In the Parameter Editor, set the following parameters: | General | General | General | ...

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## 4.2.3. Converting Multipliers The following section discusses converting instances of the AMD Xilinx Multiplier Core to Altera FPGA Multiplier IP cores. Altera provides two IP cores for implement...

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## 4.2.3.1. Feature Comparison Inferring Multipliers and DSP Functions in Quartus Prime Pro Edition User Guide: Design Recommendations The AMD Xilinx Multiplier Core and the Altera FPGA LPM\_MULT I...

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## 4.2.3.2. Port Mapping LPM\_MULT (Multiplier) IP Core in Altera FPGA Integer Arithmetic IP Cores User Guide The following table shows the port mapping between the AMD Xilinx Multiplier Core and t...

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## 4.2.3.3. Example: Converting to the LPM\_MULT IP Core You can convert the AMD Xilinx Multiplier Core that targets a AMD Xilinx device into multipliers for an Altera FPGA device by using the IP Cat...

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## Table 61. Parameters of Multiplier Module | Parameter | Value | |--------------------...

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## The Original Verilog HDL Code in the Vivado Software is: ``` module top( input clk, input [17:0] a, input [17:0] b, input ce, input sclr, output [35:0] p ); mymult i1 ( .CLK(clk), .A(a), // Bus [1...

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## The original VHDL Code in the Vivado Software is: ``` LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY work; ENTITY test IS port ( clk: IN STD_LOGIC; a: IN STD_LOGIC_VECTOR(17 downto 0); b: IN S...

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## Converted VHDL Code in the Quartus Prime Pro Edition Software ``` LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY work; ENTITY test IS port ( clk: IN STD_LOGIC; a: IN STD_LOGIC_VECTOR(17 downto...

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## 4.2.3.4. Example: Converting to the Altera FPGA Multiply Adder IP core The following example shows VHDL multipliers compiled in the Quartus Prime Pro Edition Software after the conversion. The IP ...

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## 4.3. Setting Equivalent AMD Xilinx Design Constraints AMD Xilinx designs store all the constraints and attributes in AMD Xilinx Design Constraint ( .xdc ) files, including timing and device constr...

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## Table 62. Altera FPGA Equivalent Device Constraints - Design Constraints on page 25 - Timing Constraints on page 86 The following table summarizes the most common AMD Xilinx device constraints a...

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## 4.3.1.1. DRIVE Equivalent to the DRIVE constraint in the AMD Xilinx Vivado software, the CURRENT\_STRENGTH\_NEW logic option sets the drive strength of a pin. You must assign this option to an out...

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## 4.3.1.2. SLEW Current Strength logic option in Quartus Prime Pro Edition Help Equivalent to the SLEW constraint in the AMD Xilinx Vivado software, the SLEW\_RATE logic option helps to reduce swi...

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## Equivalent QSF command: ``` # set fast slew rate to q1 set_property SLEW FAST [get_ports q1] ``` AN-307 | 2026.01.05 ``` # set programmable slew rate to q1 set_instance_assignment -name SLEW_...

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## 4.3.1.3. IOB Equivalent to the IOB constraint in AMD Xilinx, the FAST\_INPUT\_REGISTER and FAST\_OUTPUT\_REGISTER logic options directs the Compiler to implement an input register and output regis...

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## Equivalent QSF command: ``` # Set IOB to input d1 set_property IOB TRUE [get_ports d1]; # Set IOB to output q1 set_property IOB TRUE [get_ports q1]; ``` ``` # Set FAST_INPUT_REGSITER to input d1...

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## 4.3.1.4. IOSTANDARD - Fast Input Register logic option in Quartus Prime Pro Edition Help - Fast Output Register logic option in Quartus Prime Pro Edition Help Equivalent to the IOSTANDARD constr...

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## Example XDC command: ``` # Set Differential SSTL18_I I/O Standard to q2 set_property IOSTANDARD SSTL18_I [get_ports q2]; ``` Equivalent QSF command: ``` # Set Differential SSTL-18 Class I ...

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## 4.3.1.5. KEEP I/O Standard logic option in Quartus Prime Pro Edition Help Equivalent to the KEEP constraints, the Attribute Keep (VHDL) or Synthesis Keep (Verilog) synthesis attributes direct th...

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## Related Information - Preserving Registers During Synthesis in Quartus Prime Pro Edition User Guide: Design Compilation - keep VHDL Synthesis Attribute in Quartus Prime Pro Edition Help - keep Ver...

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## 4.3.2. Placement Constraints The following table compares the most common AMD Xilinx placement constraints with the Altera FPGA equivalent placement constraints: Table 63. Placement Constraints ...

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## 4.3.2.1. PBLOCK Viewing and Editing Design Placement on page 31 Equivalent to the PBLOCK constraint in the AMD Xilinx Vivado software, Logic Lock regions are floorplan location constraints in th...

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## XDC Command: ``` create_pblock pblock_uut_inst add_cells_to_pblock [get_pblocks pblock_uut_inst] [get_cells -quiet [list uut_inst]] resize_pblock [get_pblocks pblock_uut_inst] -add {SLICE_X218Y284...

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## Equivalent QSF Command: ``` set_instance_assignment -name PLACE_REGION "X1 Y1 X20 Y20" -to uut_inst ``` ``` set_instance_assignment -name RESERVE_PLACE_REGION ON -to uut_inst set_instance_assignm...

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## 4.3.2.1.1. Differences Between PBLOCK and Logic Lock Regions Logic Lock Region Assignment Examples in Quartus Prime Pro Edition User Guide: Design Optimization AN-307 | 2026.01.05 The default...

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## 4.3.2.2. PACKAGE\_PIN Equivalent to the PACKAGE\_PIN constraint in the AMD Xilinx Vivado software, PIN\_<pin number> is the pin location constraint assignment that the Quartus Prime Pro Edit...

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## Example of XDC Command: ``` # Assign location for the clock pin set_property PACKAGE_PIN B26 [get_ports clock] ``` ``` Equivalent QSF Command: ``` ``` # Assign location for the clock pin set_loc...

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## 4.3.2.3. LOC & BEL In the AMD Xilinx Vivado software, the LOC constraint specifies the placement of a logic cell to a specific SLICE, and the BEL constraint specifies the placement of a leaf c...

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## Equivalent QSF Command: ``` # Assign location for an internal register ``` ``` set_property LOC SLICE_X0Y0 [get_cells uut_inst/dout_reg] ``` ``` # Assign location for an internal register set_l...

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## 4.3.3. Timing Constraints PROHIBIT specifies the BEL or LOC on a AMD Xilinx device where placement is prohibited. An equivalent constraint is not available in the Quartus Prime Pro Edition Softwar...

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## 4.3.3. Timing Constraints | Vivado XDC Timing Constraint | Timing Analyzer SDC Command | Description ...

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## 4.3.3.1. Clock Domain Crossing Using the Quartus Prime Timing Analyzer in Quartus Prime Pro Edition User Guide: Timing Analyzer The following table shows how to convert Xilinx Vivado XDC timin...

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## 4.3.4. Retimer Constraints In the Quartus Prime Pro Edition Software, the Fitter's Retime stage moves (retimes) existing registers into Hyper-Registers for fine-grained performance improvement (av...

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## 4.4. Setting Up the Simulation Environment Hyper-Aware Design Flow on page 44 Quartus Prime Pro Edition software supports RTL and gate-level design simulation in the EDA simulators listed in the...

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## Table 66. Supported Simulators | Simulation Tools | Version | |-----------------------------------|------------------------------| | Aldec* Active-HDL* ...

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## 4.4.1. Simulation Levels - Questa - Altera FPGA Edition Software - Questa-Altera FPGA Edition Quick-Start: Quartus Prime Pro Edition The Quartus Prime Pro Edition software supports RTL and gate-...

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## 4.4.2. HDL Support for EDA Simulators - Questa - Altera FPGA Edition Software - Supported Simulation Levels in Quartus Prime Pro Edition User Guide: Third-party Simulation The Quartus Prime Pro ...

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## 4.4.3. Value Change Dump (VCD) Support All the EDA simulators that the Quartus Prime Pro Edition software support, besides other third-party simulators can generate .vcd files. The Quartus Prime P...

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## 4.4.4. Simulating Altera FPGA IP Cores The Quartus Prime software supports IP core RTL simulation in specific EDA simulators. IP generation creates simulation files, including the functional simul...

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## 5. Conclusion Simulating IP Cores in Quartus Prime Pro Edition User Guide: Third-party Simulation The Quartus Prime software provides a complete design environment that you can easily adap...

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## 6. AN 307: Altera FPGA Design Flow for AMD Xilinx Users Archives For the latest and previous versions of this application note, refer to AN 307: Altera FPGA Design Flow for AMD Xilinx Users . If a...

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## 7. Document Revision History for Altera FPGA Design Flow for AMD Xilinx Users | Document Version | Quartus Prime Version | Changes ...

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## 7. Document Revision History for Altera FPGA Design Flow for AMD Xilinx Users • Updated template ...

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## 7. Document Revision History for Altera FPGA Design Flow for AMD Xilinx Users AN-307 | 2026.01.05 | Document Version | Quartus Prime Version | Changes ...