Agilex™ 5 FPGAs and SoCs E-Series P ro duct Table

Agilex™ 5 FPGAs and SoCs E-Series P ro duct Table

altera

<!-- image -->

Version 2025.09.30

| Line | DeviceGroupAFPGAs | DeviceGroupAFPGAs | DeviceGroupAFPGAs | DeviceGroupAFPGAs | DeviceGroupAFPGAs | |----------------------------------------------------------|----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | Product | A5E013A | A5E028A | A5E043A | A5E052A | A5E065A | | Specification Options¹ | C,D | C,D | C,D | C,D | C,D | | Logic elements (LEs) | 138,060 | 282,256 | 434,240 | 523,920 | 656,080 | | Adaptivelogicmodules(ALMs) | 46,800 | 95,680 | 147,200 | 177,600 | 222,400 | | ALMregisters | 187,200 | 382,720 | 588,800 | 710,400 | 889,600 | | M20Kmemoryblocks | 358 | 716 | 1,050 | 1,288 | 1,611 | | M20Kmemorysize(Mb) | 6.99 | 13.98 | 20.51 | 25.16 | 31.46 | | Resources MLABmemorycount | 2,340 | 4,784 | 6,720 | 8,440 | 11,120 | | MLABmemorysize(Mb) | 1.43 | 2.92 | 4.10 | 5.15 | 6.79 | | I/OPLL | 4 | 4 | 8 | 8 | 8 | | Fabric-feedingI/OPLL 2 | 8 | 10 | 13 | 13 | 13 | | Variable-precision digital signal processing(DSP) blocks | 188 | 376 | 564 | 676 | 846 | | 18 x 19 multipliers | 376 | 752 | 1,128 | 1,352 | 1,692 | | PeakINT8(TOPS) | 5.78 | 11.55 | 17.33 | 20.78 | 25.99 | | LVDSpairsat1.6Gbps | 96 | 96 | 192 | 192 | 192 | | DDR4/5andLPDDR4/5interfaces(x32) | 2 | 2 | 4 | 4 | 4 | | MIPID-PHYinterface | 14 | 14 | 28 | 28 | 28 | | Differential(RXorTX)pairsat28Gbps | 4 | 12 | 16 | 24 | 24 | | PCIe4.0x4instance | 1 | 3 | 4 | 6 | 6 | | High-speedI/O(HSIO) | 192 | 192 | 384 | 384 | 384 | | MaximumAvailableDeviceResources High-voltageI/O(HVIO) | 200 | 200 | 120 | 120 | 120 | | Securedevicemanager(SDM) | Provides SHA-384bitstreamintegrity, ECDSA256/384bitstreamauthentication, AES-256bitstreamencryption, physically unclonable function(PUF) protected key storage, side-channel attack resistance, SPDMattestation, cryptographic services, physical anti-tamper support | Provides SHA-384bitstreamintegrity, ECDSA256/384bitstreamauthentication, AES-256bitstreamencryption, physically unclonable function(PUF) protected key storage, side-channel attack resistance, SPDMattestation, cryptographic services, physical anti-tamper support | Provides SHA-384bitstreamintegrity, ECDSA256/384bitstreamauthentication, AES-256bitstreamencryption, physically unclonable function(PUF) protected key storage, side-channel attack resistance, SPDMattestation, cryptographic services, physical anti-tamper support | Provides SHA-384bitstreamintegrity, ECDSA256/384bitstreamauthentication, AES-256bitstreamencryption, physically unclonable function(PUF) protected key storage, side-channel attack resistance, SPDMattestation, cryptographic services, physical anti-tamper support | Provides SHA-384bitstreamintegrity, ECDSA256/384bitstreamauthentication, AES-256bitstreamencryption, physically unclonable function(PUF) protected key storage, side-channel attack resistance, SPDMattestation, cryptographic services, physical anti-tamper support | | Hardprocessorsystem(HPS) | Multi-corewith32-bit/64-bitdual-coreArmCortex*-A55upto1.5GHzwith32KBI/Dcacheand128KBL2cache,anddual-coreArmCortex-A76upto1.8GHz with64KBI/Dcacheand256KBL2cache,andupto2MBL3sharedcache,multi-channelsdirectmemoryaccess(DMA),512KBon-chipRAM,USB3.1x1, USB2.0OTGx2,TSNMACx3,UARTx2,SPIMx2,SPISx2,I3Cx2,I2Cx5,NANDx1,SDMMCx1,Osctimerx2,SPtimerx2,watchdogx5,GPIOx2. | Multi-corewith32-bit/64-bitdual-coreArmCortex*-A55upto1.5GHzwith32KBI/Dcacheand128KBL2cache,anddual-coreArmCortex-A76upto1.8GHz with64KBI/Dcacheand256KBL2cache,andupto2MBL3sharedcache,multi-channelsdirectmemoryaccess(DMA),512KBon-chipRAM,USB3.1x1, USB2.0OTGx2,TSNMACx3,UARTx2,SPIMx2,SPISx2,I3Cx2,I2Cx5,NANDx1,SDMMCx1,Osctimerx2,SPtimerx2,watchdogx5,GPIOx2. | Multi-corewith32-bit/64-bitdual-coreArmCortex*-A55upto1.5GHzwith32KBI/Dcacheand128KBL2cache,anddual-coreArmCortex-A76upto1.8GHz with64KBI/Dcacheand256KBL2cache,andupto2MBL3sharedcache,multi-channelsdirectmemoryaccess(DMA),512KBon-chipRAM,USB3.1x1, USB2.0OTGx2,TSNMACx3,UARTx2,SPIMx2,SPISx2,I3Cx2,I2Cx5,NANDx1,SDMMCx1,Osctimerx2,SPtimerx2,watchdogx5,GPIOx2. | Multi-corewith32-bit/64-bitdual-coreArmCortex*-A55upto1.5GHzwith32KBI/Dcacheand128KBL2cache,anddual-coreArmCortex-A76upto1.8GHz with64KBI/Dcacheand256KBL2cache,andupto2MBL3sharedcache,multi-channelsdirectmemoryaccess(DMA),512KBon-chipRAM,USB3.1x1, USB2.0OTGx2,TSNMACx3,UARTx2,SPIMx2,SPISx2,I3Cx2,I2Cx5,NANDx1,SDMMCx1,Osctimerx2,SPtimerx2,watchdogx5,GPIOx2. | Multi-corewith32-bit/64-bitdual-coreArmCortex*-A55upto1.5GHzwith32KBI/Dcacheand128KBL2cache,anddual-coreArmCortex-A76upto1.8GHz with64KBI/Dcacheand256KBL2cache,andupto2MBL3sharedcache,multi-channelsdirectmemoryaccess(DMA),512KBon-chipRAM,USB3.1x1, USB2.0OTGx2,TSNMACx3,UARTx2,SPIMx2,SPISx2,I3Cx2,I2Cx5,NANDx1,SDMMCx1,Osctimerx2,SPtimerx2,watchdogx5,GPIOx2. | | Transceiver | PCIExpress*(PCIe*)hardIPuptoPCIe4.0x4EPandRP Transceiverchannelcount:upto24channelsat28Gbps(NRZ) EthernetIP:upto6x10/25GbEhardIP(MAC,PCS,andFEC) | PCIExpress*(PCIe*)hardIPuptoPCIe4.0x4EPandRP Transceiverchannelcount:upto24channelsat28Gbps(NRZ) EthernetIP:upto6x10/25GbEhardIP(MAC,PCS,andFEC) | PCIExpress*(PCIe*)hardIPuptoPCIe4.0x4EPandRP Transceiverchannelcount:upto24channelsat28Gbps(NRZ) EthernetIP:upto6x10/25GbEhardIP(MAC,PCS,andFEC) | PCIExpress*(PCIe*)hardIPuptoPCIe4.0x4EPandRP Transceiverchannelcount:upto24channelsat28Gbps(NRZ) EthernetIP:upto6x10/25GbEhardIP(MAC,PCS,andFEC) | PCIExpress*(PCIe*)hardIPuptoPCIe4.0x4EPandRP Transceiverchannelcount:upto24channelsat28Gbps(NRZ) EthernetIP:upto6x10/25GbEhardIP(MAC,PCS,andFEC) |

Notes:

1. Specification code definition:

| Code | HPS | Transceiver | Crypto | |--------|---------|---------------|----------| | C | No | Yes | No | | D | QuadHPS | Yes | Yes |

Quad HPS:

2xA55 and 2xA76

Agilex™ 5 FPGAs and SoCs E-Series P ro duct Table

altera

<!-- image -->

Version 2025.09.30

| | DeviceGroupAFPGAs | DeviceGroupAFPGAs | DeviceGroupAFPGAs | DeviceGroupAFPGAs | DeviceGroupAFPGAs | |-------------------------------------|---------------------------------|---------------------------------|---------------------------------|---------------------------------|---------------------------------| | Product Line | A5E013A | A5E028A | A5E043A | A5E052A | A5E065A | | PackageOptions 3 andI/OPins | | | | | | | Packagecode(Packagesize,ball pitch) | HVIO/HSIO 4 /HPSIO/Transceivers | HVIO/HSIO 4 /HPSIO/Transceivers | HVIO/HSIO 4 /HPSIO/Transceivers | HVIO/HSIO 4 /HPSIO/Transceivers | HVIO/HSIO 4 /HPSIO/Transceivers | | B23A(23mmx23mm,Variable 5,6 ) | 120/96/48/4 | 120/96/48/12 | 120/96/48/12 | 120/96/48/12 | 120/96/48/12 | | B32A(32mmx32mm,Variable 5,6 ) | 200/192/48/4 | 200/192/48/12 | 120/384/48/16 | 120/384/48/24 | 120/384/48/24 |

Notes:

3. For more information about the device migration path, please refer to the Device Migration Guidelines: Agilex™ 5 FPGAs and SoCs E-Series .

4. The number of LVDS pairs is half of the HSIO count.

5. VPBGA packaging is compatible with Type III PCBs, that use design rules equivalent to 0.8mm ball pitch packages and standard plated through hole (PTH) vias.

6. The ball pitch is variable, ranging from 0.65mm - 1.45mm in single package to ease signal routing. For more details about Variable Pitch BGA (VPBGA) technology, please refer to PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex™ 5 FPGAs and SoCs.

7. All data is correct at the time of printing, and may be subject to change without prior notice. For the latest information, please visit www.intel.com/fpga .

Agilex™ 5 FPGAs and SoCs E-Series P ro duct Table

altera

<!-- image -->

Version 2025.09.30

| | DeviceGroupBFPGAs | DeviceGroupBFPGAs | DeviceGroupBFPGAs | DeviceGroupBFPGAs | DeviceGroupBFPGAs | DeviceGroupBFPGAs | DeviceGroupBFPGAs | DeviceGroupBFPGAs | |----------------------------------------------------------|-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | Product Line | A5E005B | A5E007B | A5E008B | A5E013B | A5E028B | A5E043B | A5E052B | A5E065B | | Specification Options¹ | A,G | A,G | A,B,C,D,E | A,B,C,D,E | A,B,C,D,E | C,D | C,D | C,D | | Logic elements (LEs) | 50,445 | 69,030 | 85,196 | 138,060 | 282,256 | 434,240 | 523,920 | 656,080 | | Adaptivelogicmodules(ALMs) | 17,100 | 23,400 | 28,880 | 46,800 | 95,680 | 147,200 | 177,600 | 222,400 | | ALMregisters | 68,400 | 93,600 | 115,520 | 187,200 | 382,720 | 588,800 | 710,400 | 889,600 | | M20Kmemoryblocks | 130 | 179 | 229 | 358 | 716 | 1,050 | 1,288 | 1,611 | | M20Kmemorysize(Mb) | 2.54 | 3.50 | 4.47 | 6.99 | 13.98 | 20.51 | 25.16 | 31.46 | | Resources MLABmemorycount | 850 | 1,170 | 1,780 | 2,340 | 4,784 | 6,720 | 8,440 | 11,120 | | MLABmemorysize(Mb) | 0.52 | 0.71 | 1.09 | 1.43 | 2.92 | 4.10 | 5.13 | 6.79 | | I/OPLL | 2 | 2 | 4 | 4 | 4 | 8 | 8 | 8 | | Fabric-feedingI/OPLL 2 | 5 | 5 | 8 | 8 | 10 | 13 | 13 | 13 | | Variable-precision digital signal processing(DSP) blocks | 65 | 94 | 116 | 188 | 376 | 564 | 676 | 846 | | 18 x 19 multipliers | 130 | 188 | 232 | 376 | 752 | 1,128 | 1,352 | 1,692 | | PeakINT8(TOPS) | 1.7 | 2.46 | 3.05 | 4.93 | 9.85 | 14.78 | 17.72 | 22.17 | | LVDSpairsat1,250Mbps | 48 | 48 | 96 | 96 | 96 | 192 | 192 | 192 | | DDR4andLPDDR4/5interfaces(x32) | 1 | 1 | 2 | 2 | 2 | 4 | 4 | 4 | | MIPID-PHYinterface | 7 | 7 | 14 | 14 | 14 | 28 | 28 | 28 | | Differential(RXorTX)pairsat17Gbps | 0 | 0 | 4 | 4 | 12 | 16 | 24 | 24 | | PCIe4.0x4instance | 0 | 0 | 1 | 1 | 3 | 4 | 6 | 6 | | High-speedI/O(HSIO) | 96 | 96 | 192 | 192 | 192 | 384 | 384 | 384 | | MaximumAvailableDeviceResources High-voltageI/O(HVIO) | 160 | 160 | 200 | 200 | 200 | 120 | 120 | 120 | | Securedevicemanager(SDM) | Provides SHA-384bitstreamintegrity, ECDSA256/384bitstreamauthentication, AES-256bitstreamencryption, physically unclonable function (PUF)protected key storage, side-channel attack resistance, SPDMattestation, cryptographic services, physical anti-tamper support | Provides SHA-384bitstreamintegrity, ECDSA256/384bitstreamauthentication, AES-256bitstreamencryption, physically unclonable function (PUF)protected key storage, side-channel attack resistance, SPDMattestation, cryptographic services, physical anti-tamper support | Provides SHA-384bitstreamintegrity, ECDSA256/384bitstreamauthentication, AES-256bitstreamencryption, physically unclonable function (PUF)protected key storage, side-channel attack resistance, SPDMattestation, cryptographic services, physical anti-tamper support | Provides SHA-384bitstreamintegrity, ECDSA256/384bitstreamauthentication, AES-256bitstreamencryption, physically unclonable function (PUF)protected key storage, side-channel attack resistance, SPDMattestation, cryptographic services, physical anti-tamper support | Provides SHA-384bitstreamintegrity, ECDSA256/384bitstreamauthentication, AES-256bitstreamencryption, physically unclonable function (PUF)protected key storage, side-channel attack resistance, SPDMattestation, cryptographic services, physical anti-tamper support | Provides SHA-384bitstreamintegrity, ECDSA256/384bitstreamauthentication, AES-256bitstreamencryption, physically unclonable function (PUF)protected key storage, side-channel attack resistance, SPDMattestation, cryptographic services, physical anti-tamper support | Provides SHA-384bitstreamintegrity, ECDSA256/384bitstreamauthentication, AES-256bitstreamencryption, physically unclonable function (PUF)protected key storage, side-channel attack resistance, SPDMattestation, cryptographic services, physical anti-tamper support | Provides SHA-384bitstreamintegrity, ECDSA256/384bitstreamauthentication, AES-256bitstreamencryption, physically unclonable function (PUF)protected key storage, side-channel attack resistance, SPDMattestation, cryptographic services, physical anti-tamper support | | Hardprocessorsystem(HPS) | NA | NA | Multi-corewith32-bit/64-bitdual-coreArmCortex-A55upto1.25GHzwith32KBI/Dcacheand128KBL2cache,and dual-coreArmCortex-A76upto1.4GHzwith64KBI/Dcacheand256KBL2cache,andupto2MBL3sharedcache, multi-channelsdirectmemoryaccess(DMA),512KBon-chipRAM,USB3.1x1,USB2.0OTGx2,TSNMACx3,UARTx2, SPIMx2,SPISx2,I3Cx2,I2Cx5,NANDx1,SDMMCx1,Osctimerx2,SPtimerx2,watchdogx5,GPIOx2. | Multi-corewith32-bit/64-bitdual-coreArmCortex-A55upto1.25GHzwith32KBI/Dcacheand128KBL2cache,and dual-coreArmCortex-A76upto1.4GHzwith64KBI/Dcacheand256KBL2cache,andupto2MBL3sharedcache, multi-channelsdirectmemoryaccess(DMA),512KBon-chipRAM,USB3.1x1,USB2.0OTGx2,TSNMACx3,UARTx2, SPIMx2,SPISx2,I3Cx2,I2Cx5,NANDx1,SDMMCx1,Osctimerx2,SPtimerx2,watchdogx5,GPIOx2. | Multi-corewith32-bit/64-bitdual-coreArmCortex-A55upto1.25GHzwith32KBI/Dcacheand128KBL2cache,and dual-coreArmCortex-A76upto1.4GHzwith64KBI/Dcacheand256KBL2cache,andupto2MBL3sharedcache, multi-channelsdirectmemoryaccess(DMA),512KBon-chipRAM,USB3.1x1,USB2.0OTGx2,TSNMACx3,UARTx2, SPIMx2,SPISx2,I3Cx2,I2Cx5,NANDx1,SDMMCx1,Osctimerx2,SPtimerx2,watchdogx5,GPIOx2. | Multi-corewith32-bit/64-bitdual-coreArmCortex-A55upto1.25GHzwith32KBI/Dcacheand128KBL2cache,and dual-coreArmCortex-A76upto1.4GHzwith64KBI/Dcacheand256KBL2cache,andupto2MBL3sharedcache, multi-channelsdirectmemoryaccess(DMA),512KBon-chipRAM,USB3.1x1,USB2.0OTGx2,TSNMACx3,UARTx2, SPIMx2,SPISx2,I3Cx2,I2Cx5,NANDx1,SDMMCx1,Osctimerx2,SPtimerx2,watchdogx5,GPIOx2. | Multi-corewith32-bit/64-bitdual-coreArmCortex-A55upto1.25GHzwith32KBI/Dcacheand128KBL2cache,and dual-coreArmCortex-A76upto1.4GHzwith64KBI/Dcacheand256KBL2cache,andupto2MBL3sharedcache, multi-channelsdirectmemoryaccess(DMA),512KBon-chipRAM,USB3.1x1,USB2.0OTGx2,TSNMACx3,UARTx2, SPIMx2,SPISx2,I3Cx2,I2Cx5,NANDx1,SDMMCx1,Osctimerx2,SPtimerx2,watchdogx5,GPIOx2. | Multi-corewith32-bit/64-bitdual-coreArmCortex-A55upto1.25GHzwith32KBI/Dcacheand128KBL2cache,and dual-coreArmCortex-A76upto1.4GHzwith64KBI/Dcacheand256KBL2cache,andupto2MBL3sharedcache, multi-channelsdirectmemoryaccess(DMA),512KBon-chipRAM,USB3.1x1,USB2.0OTGx2,TSNMACx3,UARTx2, SPIMx2,SPISx2,I3Cx2,I2Cx5,NANDx1,SDMMCx1,Osctimerx2,SPtimerx2,watchdogx5,GPIOx2. | | Transceiver | NA | NA | PCIehardIPuptoPCIe4.0x4EPandRP Transceiverchannelcount:upto24channelsat17Gbps(NRZ) EthernetIP:upto6x10GbEhardIP(MAC,PCS,andFEC) | PCIehardIPuptoPCIe4.0x4EPandRP Transceiverchannelcount:upto24channelsat17Gbps(NRZ) EthernetIP:upto6x10GbEhardIP(MAC,PCS,andFEC) | PCIehardIPuptoPCIe4.0x4EPandRP Transceiverchannelcount:upto24channelsat17Gbps(NRZ) EthernetIP:upto6x10GbEhardIP(MAC,PCS,andFEC) | PCIehardIPuptoPCIe4.0x4EPandRP Transceiverchannelcount:upto24channelsat17Gbps(NRZ) EthernetIP:upto6x10GbEhardIP(MAC,PCS,andFEC) | PCIehardIPuptoPCIe4.0x4EPandRP Transceiverchannelcount:upto24channelsat17Gbps(NRZ) EthernetIP:upto6x10GbEhardIP(MAC,PCS,andFEC) | PCIehardIPuptoPCIe4.0x4EPandRP Transceiverchannelcount:upto24channelsat17Gbps(NRZ) EthernetIP:upto6x10GbEhardIP(MAC,PCS,andFEC) |

Notes:

1. Specification code definition:

| Code | HPS | Transceiver | Crypto | |--------|---------|---------------|----------| | A | No | No | No | | B | QuadHPS | No | Yes | | C | No | Yes | No | | D | QuadHPS | Yes | Yes | | E | DualHPS | No | Yes | | G | No | No | Yes § |

Quad HPS:

2xA55 and 2xA76

Dual HPS:

2xA55

§ Enabled for B18A package only

Agilex™ 5 FPGAs and SoCs E-Series P ro duct Table

altera

<!-- image -->

Version 2025.09.30

| Product Line | DeviceGroupBFPGAs | DeviceGroupBFPGAs | DeviceGroupBFPGAs | DeviceGroupBFPGAs | DeviceGroupBFPGAs | DeviceGroupBFPGAs | DeviceGroupBFPGAs | DeviceGroupBFPGAs | |-------------------------------------|---------------------------------|---------------------------------|---------------------------------|---------------------------------|---------------------------------|---------------------------------|---------------------------------|---------------------------------| | Product Line | A5E005B | A5E007B | A5E008B | A5E013B | A5E028B | A5E043B | A5E052B | A5E065B | | PackageOptions 3 andI/OPins | | | | | | | | | | Packagecode(Packagesize,ball pitch) | HVIO/HSIO 4 /HPSIO/Transceivers | HVIO/HSIO 4 /HPSIO/Transceivers | HVIO/HSIO 4 /HPSIO/Transceivers | HVIO/HSIO 4 /HPSIO/Transceivers | HVIO/HSIO 4 /HPSIO/Transceivers | HVIO/HSIO 4 /HPSIO/Transceivers | HVIO/HSIO 4 /HPSIO/Transceivers | HVIO/HSIO 4 /HPSIO/Transceivers | | B15A(15mmx15mm,Variable 5,6 ) | 80/72/0/0 | 80/72/0/0 | | | | | | | | M16A(16mmx16mm,0.5mm 7 ) | | | 40/192/48/4 | 40/192/48/4 | 40/192/48/8 | | | | | B18A(18mmx18mm,Variable 5,6 ) | 160/48/0/0 | 160/48/0/0 | | | | | | | | B23B(23mmx23mm,Variable 5,6 ) | 160/96/0/0 | 160/96/0/0 | 160/192/48/0 | 160/192/48/0 | 160/192/48/0 | | | | | B23A(23mmx23mm,Variable 5,6 ) | | | 120/96/48/4 | 120/96/48/4 | 120/96/48/12 | 120/96/48/12 | 120/96/48/12 | 120/96/48/12 | | B32A(32mmx32mm,Variable 5,6 ) | | | 200/192/48/4 | 200/192/48/4 | 200/192/48/12 | 120/384/48/16 | 120/384/48/24 | 120/384/48/24 |

Notes:

3. For more information about the device migration path, please refer to the Device Migration Guidelines: Agilex™ 5 FPGAs and SoCs E-Series.

4. The number of LVDS pairs is half of the HSIO count.

5. VPBGA packaging is compatible with Type III PCBs, that use design rules equivalent to 0.8mm ball pitch packages and standard plated through hole (PTH) vias.

6. The ball pitch is variable, ranging from 0.65mm - 1.45mm in single package to ease signal routing. For more details about Variable Pitch BGA (VPBGA) technology, please refer to PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex™ 5 FPGAs and SoCs.

7. 0.5mm Micro Fineline BGA (MBGA).

8. All data is correct at the time of printing, and may be subject to change without prior notice. For the latest information, please visit www.intel.com/fpga.

© Altera Corporation. Altera, the Altera logo, the 'a' logo, and other Altera marks are trademarks of Altera Corporation. Altera reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

*Other names and brands may be claimed as the property of others.