Agilex™ 5 FPGAs and SoCs D-Series Product Table

Agilex™ 5 FPGAs and SoCs D-Series Product Table

altera

Version 2025.09.30

| Product Line | A5D051 | A5D064 | A5D110 | A5D130 | A5D160 | |----------------------------------------------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | Specification Options¹ | D, I | D, I | D, I | D, I | D, I | | Logic elements (LEs) | 515,070 | 644,280 | 1,073,800 | 1,293,280 | 1,616,600 | | Adaptivelogicmodules(ALMs) | 174,600 | 218,400 | 364,000 | 438,400 | 548,000 | | ALMregisters | 698,400 | 873,600 | 1,456,000 | 1,753,600 | 2,192,000 | | M20Kmemoryblocks | 2,563 | 3,204 | 5,340 | 6,408 | 8,010 | | M20Kmemorysize(Mb) | 50.06 | 62.58 | 104.30 | 125.16 | 156.45 | | Resources MLABmemorycount | 8,440 | 10,920 | 18,200 | 21,920 | 27,400 | | MLABmemorysize(Mb) | 5.15 | 6.67 | 11.11 | 13.38 | 16.72 | | I/OPLL | 8 | 8 | 12 | 16 | 16 | | Fabric-feedingI/OPLL 2 | 15 | 15 | 13 | 23 | 23 | | Variable-precision digital signal processing (DSP)blocks. AI-capable | 1,472 | 1,840 | 3,312 | 3,864 | 4,968 | | 18 x 19 multipliers | 2,944 | 3,680 | 6,624 | 7,728 | 9,936 | | PeakINT8(TOPS) | 45.22 | 56.52 | 101.75 | 118.70 | 152.62 | | LVDSpairsat1.6Gbps | 192 | 192 | 288 | 384 | 384 | | DDR4interface(x64) | 2 | 2 | 2 | 4 | 4 | | DDR4/5andLPDDR4/5interfaces(x32) | 4 | 4 | 6 | 8 | 8 | | MIPID-PHYinterface | 28 | 28 | 28 | 28 | 28 | | Differential(RXorTX)pairsat28Gbps | 24 | 32 | 24 | 48 | 48 | | PCIe4.0, x4ports | 6 | 8 | 6 | 12 | 12 | | PCIe4.0, x8ports | 3 | 4 | 3 | 6 | 6 | | MaximumAvailableDeviceResources High-speedI/O(HSIO) | 384 | 384 | 576 | 768 | 768 | | High-voltageI/O(HVIO) | 60 | 60 | 40 | 120 | 120 | | Securedevicemanager(SDM) | Provides SHA-384bitstreamintegrity, ECDSA256/384bitstreamauthentication, PQCsecureboot,AES-256bitstreamencryption,physically unclonable function (PUF)protected key storage, side-channel attack resistance, SPDMattestation, cryptographic services, physical anti-tamper support. | Provides SHA-384bitstreamintegrity, ECDSA256/384bitstreamauthentication, PQCsecureboot,AES-256bitstreamencryption,physically unclonable function (PUF)protected key storage, side-channel attack resistance, SPDMattestation, cryptographic services, physical anti-tamper support. | Provides SHA-384bitstreamintegrity, ECDSA256/384bitstreamauthentication, PQCsecureboot,AES-256bitstreamencryption,physically unclonable function (PUF)protected key storage, side-channel attack resistance, SPDMattestation, cryptographic services, physical anti-tamper support. | Provides SHA-384bitstreamintegrity, ECDSA256/384bitstreamauthentication, PQCsecureboot,AES-256bitstreamencryption,physically unclonable function (PUF)protected key storage, side-channel attack resistance, SPDMattestation, cryptographic services, physical anti-tamper support. | Provides SHA-384bitstreamintegrity, ECDSA256/384bitstreamauthentication, PQCsecureboot,AES-256bitstreamencryption,physically unclonable function (PUF)protected key storage, side-channel attack resistance, SPDMattestation, cryptographic services, physical anti-tamper support. | | Hardprocessorsystem(HPS) | Multi-corewith32-bit/64-bitdual-coreArmCortex*-A55upto1.5GHzwith32KBI/Dcacheand128KBL2cache,anddual-coreArmCortex-A76upto1.8GHz with64KBI/Dcacheand256KBL2cache,andupto2MBL3sharedcache,multi-channeldirectmemoryaccess(DMA),512KBon-chipRAM,USB3.1x1,USB 2.0OTGx2,TSNMACx3,UARTx2,SPIMx2,SPISx2,I3Cx2,I2Cx5,NANDx1,SDMMCx1,Osctimerx2,SPtimerx2,watchdogx5,GPIOx2. | Multi-corewith32-bit/64-bitdual-coreArmCortex*-A55upto1.5GHzwith32KBI/Dcacheand128KBL2cache,anddual-coreArmCortex-A76upto1.8GHz with64KBI/Dcacheand256KBL2cache,andupto2MBL3sharedcache,multi-channeldirectmemoryaccess(DMA),512KBon-chipRAM,USB3.1x1,USB 2.0OTGx2,TSNMACx3,UARTx2,SPIMx2,SPISx2,I3Cx2,I2Cx5,NANDx1,SDMMCx1,Osctimerx2,SPtimerx2,watchdogx5,GPIOx2. | Multi-corewith32-bit/64-bitdual-coreArmCortex*-A55upto1.5GHzwith32KBI/Dcacheand128KBL2cache,anddual-coreArmCortex-A76upto1.8GHz with64KBI/Dcacheand256KBL2cache,andupto2MBL3sharedcache,multi-channeldirectmemoryaccess(DMA),512KBon-chipRAM,USB3.1x1,USB 2.0OTGx2,TSNMACx3,UARTx2,SPIMx2,SPISx2,I3Cx2,I2Cx5,NANDx1,SDMMCx1,Osctimerx2,SPtimerx2,watchdogx5,GPIOx2. | Multi-corewith32-bit/64-bitdual-coreArmCortex*-A55upto1.5GHzwith32KBI/Dcacheand128KBL2cache,anddual-coreArmCortex-A76upto1.8GHz with64KBI/Dcacheand256KBL2cache,andupto2MBL3sharedcache,multi-channeldirectmemoryaccess(DMA),512KBon-chipRAM,USB3.1x1,USB 2.0OTGx2,TSNMACx3,UARTx2,SPIMx2,SPISx2,I3Cx2,I2Cx5,NANDx1,SDMMCx1,Osctimerx2,SPtimerx2,watchdogx5,GPIOx2. | Multi-corewith32-bit/64-bitdual-coreArmCortex*-A55upto1.5GHzwith32KBI/Dcacheand128KBL2cache,anddual-coreArmCortex-A76upto1.8GHz with64KBI/Dcacheand256KBL2cache,andupto2MBL3sharedcache,multi-channeldirectmemoryaccess(DMA),512KBon-chipRAM,USB3.1x1,USB 2.0OTGx2,TSNMACx3,UARTx2,SPIMx2,SPISx2,I3Cx2,I2Cx5,NANDx1,SDMMCx1,Osctimerx2,SPtimerx2,watchdogx5,GPIOx2. | | Transceiver | PCIExpress*(PCIe*)hardIPuptosixPCIe4.0x8EPandRP Transceiverchannelcount:upto48channelsat28Gbps(NRZ) EthernetIP:upto24x10/25GbEhardIP(MAC,PCS,andFEC) | PCIExpress*(PCIe*)hardIPuptosixPCIe4.0x8EPandRP Transceiverchannelcount:upto48channelsat28Gbps(NRZ) EthernetIP:upto24x10/25GbEhardIP(MAC,PCS,andFEC) | PCIExpress*(PCIe*)hardIPuptosixPCIe4.0x8EPandRP Transceiverchannelcount:upto48channelsat28Gbps(NRZ) EthernetIP:upto24x10/25GbEhardIP(MAC,PCS,andFEC) | PCIExpress*(PCIe*)hardIPuptosixPCIe4.0x8EPandRP Transceiverchannelcount:upto48channelsat28Gbps(NRZ) EthernetIP:upto24x10/25GbEhardIP(MAC,PCS,andFEC) | PCIExpress*(PCIe*)hardIPuptosixPCIe4.0x8EPandRP Transceiverchannelcount:upto48channelsat28Gbps(NRZ) EthernetIP:upto24x10/25GbEhardIP(MAC,PCS,andFEC) |

Notes:

1. Specification code definition:

| Code | HPS | Transceiver | Crypto | PQC | |--------|---------|---------------|----------|-------| | D | QuadHPS | Yes | Yes | Yes | | I | No | Yes | No | Yes |

Agilex™ 5 FPGAs and SoCs D-Series Product Table

altera

Version 2025.09.30

| Product Line | | | | | | |-----------------------------------------------------------------|------------------------------------------|------------------------------------------|------------------------------------------|------------------------------------------|------------------------------------------| | | A5D051 | A5D064 | A5D110 | A5D130 | A5D160 | | PackageOptions 3 andI/OPins | NumberofHVIO/HSIO 4 / HPSIO/Transceivers | NumberofHVIO/HSIO 4 / HPSIO/Transceivers | NumberofHVIO/HSIO 4 / HPSIO/Transceivers | NumberofHVIO/HSIO 4 / HPSIO/Transceivers | NumberofHVIO/HSIO 4 / HPSIO/Transceivers | | PackageCode (Package size, min. ball pitch, grid array pattern) | | | | | | | B32B (32x32mm 2 ,0.65mm,VariablePitchBGA) | 60/384/48/24 | 60/384/48/32 | - | - | - | | B37A (37.5x37.5mm 2 ,0.65mm,VariablePitchBGA) | - | - | 40/576/48/24 | 40/576/48/24 | 120/576/48/32 | | B41A (41x41mm 2 ,0.65mm,VariablePitchBGA) | - | - | - | 120/768/48/48 | 120/768/48/48 |

Notes:

3. For more information about the device migration path, please refer to Device Migration Guidelines: Agilex™ 5 FPGAs and SoCs D-Series .

4. The number of LVDS pairs is half of the HSIO count.

5. VPBGA packaging is compatible with Type III PCBs, that use design rules equivalent to 0.8mm ball pitch packages and standard plated through hole (PTH) vias.

6. The ball pitch is variable, ranging from 0.65mm - 1.45mm in single package to ease signal routing. For more details about Variable Pitch BGA (VPBGA) technology, please refer to PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex™ 5 FPGAs and SoCs.

7. All data is correct at the time of printing and may be subject to change without prior notice. For the latest information, please visit www.altera.com .

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