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Quartus ® Prime Pro Edition User Guide

Content

Quartus ® Prime Pro Edition User Guide

Design Optimization

Updated for Quartus ® Prime Design Suite:

25.3.1

This document is part of a collection - Quartus ® Prime Pro Edition User Guides - Combined PDF link

Answers to Top FAQs:

Q What are the optimization trade-offs? A Optimization Trade-Offs and Limitations on page 67
Q How can I optimize for area? A Area Optimization on page 15
Q How can I optimize for timing? A Timing Closure and Optimization on page 52
Q Which reports help analyze timing paths? A Timing Optimization on page 65
Q How can I run a seed sweep? A Optimize with Design Space Explorer II on page 14
Q How can I optimize I/O timing? A I/O Timing Optimization Techniques on page 80
Q How do I see routing congestion? A Viewing Routing Congestion on page 54
Q How do I make last-minute design changes? A Using the ECO Compilation Flow on page 207

| 1. Answers to Top FAQs.................................................................................... |----------------------------------------------------------------------------------------------------------- | 2. Design Optimization Overview........................................................................... | 2.1. Initial FPGA Device Considerations...........................................................................7 | 2.1.1. Device Migration Considerations.................................................................. | 2.2. Initial Compiler Settings......................................................................................... | 2.2.1. Initial I/O Assignment Guidelines.................................................................9 | 2.2.2. Initial Timing Constraint Guidelines..............................................................9 | 2.3. Optimization Trade-Offs and Limitations..................................................................11 | 2.3.1. Area Reduction Trade-Offs.........................................................................11 | 2.3.2. Critical Path Delay Reduction Trade-Offs......................................................12 | 2.3.3. Power Consumption Reduction Trade-Offs....................................................13 | 2.3.4. Compilation Time Trade-Offs......................................................................13 | 2.4. Design Visualization and Optimization Tools.............................................................13 | 2.4.1. Design Visualization Tools......................................................................... | 2.4.2. Design Optimization Tools......................................................................... | 2.5. Design Optimization Overview Revision History........................................................15 | 3. Optimizing the Design Netlist....................................................................................... | 3.1. When to Use the Netlist Viewers: Analyzing Design Problems | 3.2. Quartus Prime Design Flow with the Netlist Viewers..................................................18 | 3.3. RTL Viewer Overview............................................................................................19 | 3.3.1. Maximizing Readability in RTL Viewer..........................................................20 | 3.3.2. Running the RTL Viewer............................................................................20 | 3.4. Technology Map Viewer Overview...........................................................................20 | 3.5. Netlist Viewer User Interface.................................................................................21 | 3.5.1. Netlist Navigator Pane.............................................................................. | 3.5.2. Properties Pane....................................................................................... | 3.5.3. Netlist Viewers Find Pane..........................................................................25 | 3.6. Schematic View....................................................................................... | 3.6.1. Display Schematics in Multiple Tabbed View.................................................26 | 3.6.2. Schematic Symbols..................................................................................26 | 3.6.3. Select Items in the Schematic View............................................................31 | 3.6.4. Shortcut Menu Commands in the Schematic View.........................................31 | 3.6.5. Filtering in the Schematic View.................................................................. | 3.6.6. View Contents of Nodes in the Schematic View............................................ | 3.6.7. Moving Nodes in the Schematic View..........................................................34 | 3.6.8. View LUT Representations in the Technology Map Viewer...............................35 | 3.6.9. Zoom Controls.........................................................................................35 | 3.6.10. Navigating with the Bird's Eye View.......................................................... | 3.6.11. Partition the Schematic into Pages............................................................37 | 3.6.12. Follow Nets Across Schematic Pages......................................................... | 3.7. Cross-Probing to a Source Design File and Other Quartus Prime Windows....................37 | 3.8. Cross-Probing to the Netlist Viewers from Other Quartus Prime Windows.....................38 | 3.9. Viewing a Timing Path.......................................................................................... | 3.10. Optimizing the Design Netlist Revision .................. 6 | 1. Answers to Top FAQs...................................................................................................... 6 | -----------------------|----------------------------------------------------------------------------------------------------------------------------------| .............7 | | | | | 7 | | 8 | | | | | | | | | | | | | | | | | | 14 | | 14 | | | 17 | 3. Optimizing the Design Netlist....................................................................................... 17 | | ....................................17 | | | | | | | | | | | | | | 23 | | 24 | | | ............26 | | | | | | | | | | | 32 | | 32 | | | | | | | | 36 | | | | 37 | | | | | | 39 | | History........................................................40 |

| 4. Netlist Optimizations and Physical Synthesis................................................................42 | | |-----------------------------------------------------------------------------------------------------------------------------------------------------|-----------------------------------------------------------------------------------| | 4.1. Physical Synthesis Optimizations............................................................................42 | | | 4.1.1. Disabling or Enabling Physical Synthesis Optimization...................................43 | | | 4.1.2. Physical Synthesis Options........................................................................ | 43 | | 4.2. Applying Netlist Optimizations............................................................................... | 44 | | 4.2.1. WYSIWYG Primitive Resynthesis.................................................................44 | | | 4.3. Scripting Support.................................................................................................45 | | | 4.3.1. Synthesis Netlist Optimizations..................................................................46 | | | 4.3.2. Physical Synthesis Optimizations................................................................46 | | | 4.4. Netlist Optimizations and Physical Synthesis Revision History.....................................47 | | | 5. Area Optimization.........................................................................................................49 | | | 5.1. Resource Utilization Information............................................................................ | 49 | | 5.1.1. Flow Summary Report.............................................................................. | 49 | | 5.1.2. Fitter Reports.......................................................................................... | 50 | | 5.1.3. Design Assistant Recommendations............................................................53 | | | 5.1.4. Analysis and Synthesis Reports..................................................................53 | | | 5.1.5. Compilation Messages.............................................................................. | 53 | | 5.1.6. Chip Planner Visualization......................................................................... | 54 | | 5.2. Optimizing Resource Utilization..............................................................................54 | | | 5.2.1. Resource Utilization Issues Overview.......................................................... | 54 | | 5.2.2. I/O Pin Utilization or Placement..................................................................55 | | | 5.2.3. Logic Utilization or Placement.................................................................... | 55 | | 5.2.4. Routing.................................................................................................. | 61 | | 5.3. Scripting Support.................................................................................................64 | | | 5.3.1. Initial Compilation Settings....................................................................... | 64 | | 5.3.2. Resource Utilization Optimization Techniques...............................................65 | | | 5.4. Area Optimization Revision History.........................................................................65 | | | 6. Timing Closure and Optimization.................................................................................. | 67 | | 6.1. Optimize Multi Corner Timing................................................................................ | 67 | | 6.2. Optimize Critical Paths..........................................................................................67 | | | 6.2.1. Viewing Critical Paths............................................................................... | 68 | | 6.3. Optimize Critical Chains........................................................................................68 | | | 6.3.1. Viewing Critical Chains..............................................................................68 | | | 6.4. Design Evaluation for Timing Closure......................................................................69 | | | 6.4.1. Review Messages.....................................................................................69 | | | 6.4.2. Evaluate Fitter Netlist Optimizations........................................................... | 69 | | 6.4.3. Evaluate Optimization Results....................................................................69 | | | 6.4.4. Evaluate Resource Usage.......................................................................... | 70 | | 6.4.5. Evaluate Other Reports and Adjust Settings Accordingly................................73 | | | 6.4.6. Evaluate Clustering Difficulty.....................................................................75 | | | 6.4.7. Revise and Recompile...............................................................................75 | | | 6.5. Timing Optimization.............................................................................................76 | | | 6.5.1. Correct Design Assistant Rule Violations......................................................76 | | | 6.5.2. Implement Fast Forward Timing Closure Recommendations........................... | 78 | | 6.5.3. Review Timing Path Details....................................................................... | 80 | | 6.5.4. Try Optional Fitter | Settings......................................................................103 | | 6.5.5. Back-Annotating Optimized Assignments................................................... 6.5.6. Optimize Settings with Design Space Explorer | 105 II.........................................107 |

| 6.5.7. Aggregating and Comparing Compilation Results with Exploration Dashboard.126 | | |--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|--------------------------------------------------------------------------| | 6.5.8. I/O Timing Optimization Techniques..........................................................133 | | | 6.5.9. Register-to-Register Timing Optimization Techniques...................................138 | | | 6.5.10. Metastability Analysis and Optimization Techniques...................................154 | | | 6.6. Periphery to Core Register Placement and Routing Optimization | ...............................154 | | 6.6.1. Setting Periphery to Core Optimizations in the Advanced Fitter Setting Dialog Box............................................................................................ | 155 | | 6.6.2. Setting Periphery to Core Optimizations in the Assignment Editor................. | 156 | | 6.6.3. Viewing Periphery to Core Optimizations in the Fitter Report........................ | 156 | | 6.7. Scripting Support...............................................................................................157 | | | 6.7.1. Initial Compilation Settings......................................................................158 | | | 6.7.2. I/O Timing Optimization Techniques | .........................................................158 | | 6.7.3. Register-to-Register Timing Optimization Techniques...................................159 | | | 6.8. Timing Closure and Optimization Revision History...................................................159 | | | 7. Analyzing and Optimizing the Design Floorplan.......................................................... | 164 | | 7.1. Location Assignment Optimization Guidelines.........................................................165 | | | 7.2. Design Floorplan Analysis in Chip | Planner..............................................................166 | | 7.2.1. Starting the Chip Planner........................................................................ | 167 | | 7.2.2. Chip Planner GUI....................................................................................167 | | | 7.2.3. Viewing Design Elements in Chip Planner...................................................170 | | | 7.2.4. Finding Design Elements in the Chip Planner..............................................182 | | | 7.2.5. Exploring Paths in the Chip Planner...........................................................184 | | | 7.2.6. Viewing Assignments in the Chip Planner...................................................188 | | | 7.2.7. Viewing High-Speed and Low-Power Tiles in the Chip Planner.......................188 | | | 7.2.8. Viewing Design Partition Placement.......................................................... | 189 | | 7.3. Defining Logic Lock Placement Constraints.............................................................189 | | | 7.3.1. The Logic Lock Regions Window............................................................... | 190 | | 7.3.2. Defining Logic Lock Regions.....................................................................191 | | | 7.3.3. Customizing the Shape of Logic Lock Regions.............................................200 | | | 7.3.4. Assigning Device Pins to Logic Lock Regions...............................................202 | | | 7.3.5. Viewing Connections Between Logic Lock Regions in Chip Planner.................202 | | | 7.3.6. Example: Placement Best Practices for Arria 10 FPGAs................................ | 203 | | 7.3.7. Migrating Assignments between Quartus Prime Standard Edition and Quartus Prime Pro Edition........................................................................204 | | | 7.4. Defining Virtual Pins........................................................................................... | 205 | | 7.5. Using Logic Lock Regions in Combination with Design Partitions................................206 | | | 7.5.1. Viewing Design Connectivity and Hierarchy................................................207 | | | 7.6. Creating Clock Region Assignments in Chip Planner................................................ | 209 | | 7.6.1. Creating Clock Assignments in Chip Planner...............................................210 | | | 7.6.2. Resizing a Clock Assignment in Chip Planner..............................................212 | | | 7.6.3. Moving a Clock Assignment in Chip Planner................................................213 | | | 7.6.4. Deleting a Clock Region Assignment in Chip Planner....................................213 | | | 7.6.5. Assigning a Clock Signal to a Clock Region in Chip Planner...........................213 | | | 7.7. Scripting Support...............................................................................................214 | | | 7.7.1. Creating Logic Lock Assignments with Tcl commands.................................. | 214 | | 7.7.2. Assigning Virtual Pins with a Tcl command.................................................215 | | | 7.7.3. Logic Lock Region Assignment Examples................................................... | 215 | | 7.8. Analyzing and Optimizing the Design Floorplan Revision History............................... | 216 |

| 8.1. ECO Compilation Flow.........................................................................................220 | | |-------------------------------------------------------------------------------------------------------------------------|-----| | 8.2. ECO Tcl Script Example.......................................................................................221 | | | 8.3. Viewing ECO Compilation Reports.........................................................................222 | | | 8.4. ECO Commands.................................................................................................223 | | | 8.4.1. ECO Command Quick Reference...............................................................224 | | | 8.4.2. make_connection...................................................................................224 | | | 8.4.3. remove_connection................................................................................ | 225 | | 8.4.4. modify_lutmask.....................................................................................226 | | | 8.4.5. adjust_pll_refclk.................................................................................... | 226 | | 8.4.6. modify_io_slew_rate...............................................................................227 | | | 8.4.7. modify_io_current_strength.....................................................................227 | | | 8.4.8. modify_io_delay_chain........................................................................... | 227 | | 8.4.9. create_new_node...................................................................................228 | | | 8.4.10. remove_node.......................................................................................229 | | | 8.4.11. place_node..........................................................................................229 | | | 8.4.12. unplace_node...................................................................................... | 230 | | 8.4.13. create_wirelut......................................................................................230 | | | 8.5. ECO Command Limitations.................................................................................. | 231 | | 8.6. Interactive ECO Fitting........................................................................................232 | | | 8.6.1. eco_load_design and eco_commit_design Commands................................. | 232 | | 8.7. Using the ECO Compilation Flow Revision History....................................................233 | | | 9. Quartus Prime Pro Edition Design Optimization User Guide Archives..........................235 | |

1. Answers to Top FAQs

| Q | What are the optimization trade-offs? | A | Optimization Trade-Offs and Limitations on page 67 | |-----|-------------------------------------------|-----|------------------------------------------------------| | Q | How can I optimize for area? | A | Area Optimization on page 15 | | Q | How can I optimize for timing? | A | Timing Closure and Optimization on page 52 | | Q | Which reports help analyze timing paths? | A | Timing Optimization on page 65 | | Q | How can I run a seed sweep? | A | Optimize with Design Space Explorer II on page 14 | | Q | How can I optimize I/O timing? | A | I/O Timing Optimization Techniques on page 80 | | Q | How do I see routing congestion? | A | Viewing Routing Congestion on page 54 | | Q | How do I make last-minute design changes? | A | Using the ECO Compilation Flow on page 207 |

2. Design Optimization Overview

In the early stages of FPGA design development, you typically focus on meeting your timing requirement, resource usage, and power consumption goals. After meeting these basic goals, you can focus on optimizing performance.

Optimization of FPGA design performance requires a multi-dimensional approach to reduce resource use, critical path delays, power consumption, and runtime. The Quartus Prime software provides various tools and techniques for performance optimization.

This chapter provides an overview of the initial techniques and settings in the Quartus Prime software that you can use to optimize your design results and achieve the highest performance in Altera FPGAs.

Related Information

Quartus Prime Pro Edition User Guide: Design Compilation

2.1. Initial FPGA Device Considerations

All Altera ® FPGAs have a unique timing model that describes the delay information between all physical elements in the device, such as combinational adaptive logic modules, memory blocks, interconnects, and registers. The delay models comprise all valid combinations of operating condition delays for the target FPGA. The Timing Analyzer references these delay models in calculating performance during timing analysis. The device size and package determine pin-out and the resource availability. When selecting your target Altera FPGA device for your design, you must consider the performance specifications and resources available in the device meet the needs of your design.

2.1.1. Device Migration Considerations

If you anticipate that you might later migrate your design to a different target device later in the design cycle (for example, a larger or faster device), you must plan for this migration from the beginning of cycle. Planning for migration early helps you to minimize the complex design changes that you must make later to accommodate the new device.

When choosing a target FPGA device in the Device dialog box, you can click the Migration Devices button to view a list of all compatible devices.

© Altera Corporation. Altera, the Altera logo, the 'a' logo, and other Altera marks are trademarks of Altera Corporation. Altera reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

*Other names and brands may be claimed as the property of others.

Figure 1. Devices Available for Migration from Selected Device

Related Information

Migration Devices Dialog Box

In Quartus Prime Help

2.2. Initial Compiler Settings

Your design compilation results can vary significantly, depending on the initial assignments and settings that you choose prior to compiling. The Quartus Prime software initial settings for compilation are set to provide a balanced trade-off between the time required for compilation, the device resource utilization, and the design timing performance.

You can easily adjust this trade-off to focus the Compiler's effort more on shortening the total compile time, reducing device resource utilization, or maximizing timing performance.

The initial FPGA device selection and Compiler settings have a very significant impact on design performance and optimization. You should also consider the following guidelines for specifying initial settings before compiling your design for the first time in the Quartus Prime software.

2. Design Optimization Overview

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Figure 2. Compiler Optimization Mode Settings

Click Assignments ➤ Settings ➤ Compiler Settings ➤ Optimization Mode to adjust the Compiler's effort on Performance , Area , Routability , or Compile Time .

2.2.1. Initial I/O Assignment Guidelines

The I/O standard and drive strength requirements that you specify for your design affect the I/O timing. Follow these guidelines when specifying initial I/O assignments:

When specifying I/O assignments, specify an accurate I/O timing delay for timing analysis and Fitter optimizations.
If the PCB layout does not indicate pin locations, then leave the pin locations unconstrained. This technique allows the Compiler to search for the best layout. Otherwise, make pin assignments to constrain the compilation appropriately.

Related Information

Quartus Prime Pro Edition User Guide: Design Constraints

2.2.2. Initial Timing Constraint Guidelines

Before running initial compilation or timing analysis, specify realistic timing requirements. Specifying more stringent timing requirements than the design requires causes the Compiler to expend effort to increase performance at the expense of resource usage, power utilization, or compilation time.

Click Tools ➤ Timing Analyzer then click the Constraints menu to enter constraints in the GUI, such as defining the clock signals. Alternatively, you can specify timing constraints directly in an .sdc file.

Figure 3. Create Clock Dialog Defines Clock Constraints

Specifying realistic and comprehensive timing requirements up front helps the Compiler to achieve the best results for the following reasons:

Comprehensive timing assignments enable the Compiler to work hardest to optimize the performance of the timing-critical parts of the design. This optimization can also save area or power utilization in non-critical parts of the design.
Enables physical synthesis optimizations based on the comprehensive timing requirements.

Figure 4. Timing Analyzer Shows Failing Paths in Red

Following compilation and timing analysis, the Compilation Report reports whether the design meets the timing requirements. You can then use the Quartus Prime Timing Analyzer to fine tune constraints and report detailed information about all timing paths.

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Related Information

Using the Quartus Prime Timing Analyzer In Quartus Prime Pro Edition User Guide: Timing Analyzer
Quartus Prime Timing Analyzer Cookbook

2.3. Optimization Trade-Offs and Limitations

Design optimization requires balancing the trade-offs between device performance, resource usage, power utilization, and compilation time. Your application of project settings and constraints determines the balance of these factors in meeting your design goals. When you want to increase optimization of one type, you can consider the trade-offs that might limit that optimization.

Table 1. Design Optimization Trade-Off Examples

| Trade-off | Comments | |--------------------------------------------------------------------------------|------------------------------------------------------------------------------------------------------------------------------------------------------------------| | Resource usage and critical path timing. | Certain techniques (such as logic duplication) can improve timing performance at the cost of increased area. | | Power requirements can result in area and timing trade-offs. | For example, reducing the number of available high-speed tiles, or attempting to shorten high-power nets at the expense of critical path nets. | | System cost and time-to-market considerations can affect the choice of device. | For example, a device with a higher speed grade or more clock networks can facilitate timing closure at the expense of higher power consumption and system cost. |

Finally, constraints that are too stringent can produce a situation with no possible solution for the selected device. If the Fitter cannot resolve a design due to resource limitations, timing constraints, or power constraints, consider rewriting parts of the HDL code.

2.3.1. Area Reduction Trade-Offs

By default, the Quartus Prime Fitter might physically spread a design over the entire device to meet the set timing constraints. If you prefer to optimize your design to use the smallest area, you can change this behavior by selecting Aggressive Area for the Compiler Optimization Mode . If you require reduced area, you can enable certain physical synthesis options to modify your netlist to create a more area-efficient implementation, but at the cost of increased runtime and decreased performance.

Figure 5. Optimize for Area

Related Information

Area Optimization on page 49
Netlist Optimizations and Physical Synthesis on page 42

2.3.2. Critical Path Delay Reduction Trade-Offs

To meet complex timing requirements involving multiple clocks, routing resources, and area constraints, the Quartus Prime software offers a close interaction between synthesis, floorplan editing, place-and-route, and timing analysis processes.

By default, the Quartus Prime Fitter works to meet the timing requirements, and reduces fitting effort once the requirements are met. Therefore, specifying realistic constraints is crucial for achieving timing closure.

Under-constraining your design can lead to sub-optimal results. Over-constraining your design might cause the Fitter to over-optimize non-critical paths at the expense of true critical paths. Over-constraining the design may also increase area and compilation time.

When designs have very high resource usage, the Fitter may struggle to find a legal placement. In such circumstances, the Fitter automatically modifies settings to try to trade off performance for area.

In high-density FPGAs, routing accounts for a major part of critical path timing. Because of this, duplicating or retiming logic can allow the Fitter to reduce delay on critical paths. The Quartus Prime software offers push-button netlist optimizations and physical synthesis options that can improve design performance at the expense of considerable increases of compilation time and area.

2. Design Optimization Overview

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Turn on only those options that help you keep reasonable compilation times and resource usage. Alternately, you can modify the HDL to manually duplicate or adjust the timing logic.

Related Information

Optimize Critical Paths on page 67

2.3.3. Power Consumption Reduction Trade-Offs

The Quartus Prime software has features that help reduce design power consumption. The power optimization options control the power-driven compilation settings for Synthesis and the Fitter. You can adjust these settings

Related Information

Power Optimization

In Quartus Prime Pro Edition User Guide: Power Analysis and Optimization

2.3.4. Compilation Time Trade-Offs

Many Fitter settings influence compilation time. Most of the default settings in the Quartus Prime software are set for reduced compilation time. You can modify these settings for your project requirements to trade-off longer compilation time for increased performance.

The Quartus Prime software supports parallel compilation in computers with multiple processors. This technique can reduce compilation times by up to 15%.

Related Information

Quartus Prime Pro Edition User Guide: Design Compilation

2.4. Design Visualization and Optimization Tools

The Quartus Prime software provides various tools to help you visualize and optimize the design settings and constraints for the best design implementation.

2.4.1. Design Visualization Tools

The Quartus Prime software provides tools that display different graphical representations of your design to help you visualize and optimize placement, connectivity, and routing congestion at various stages of the design cycle.

Table 2. Design Visualization Tools

| Tool | Description | |--------------------------|-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | Snapshot Viewer | The Compiler can preserve the results of each compilation stage as a snapshot for analysis optimization at each stage. The Snapshot Viewer allows you to easily analyze and optimize compilation results for each snapshot. The Snapshot Viewer provides centralized access to functions and tools that allow you to rapidly analyze clocking, congestion, and correct failing paths and high fan-out nets. | | RTL Viewer | Provides a schematic representation of the design before synthesis and place- and-route. | | Technology Map Viewer | Provides a schematic representation of the design implementation in the selected device architecture after synthesis and place-and-route. Optionally, you can include timing information. | | Chip Planner | Allows you to make floorplan assignments, such as Logic Lock placement constraints, and visualize critical paths and routing congestion. Click the Report Routing Utilization task to display the routing resource congestion. | | Interface Planner | Simplifies the planning of accurate constraints for physical implementation. Use Interface Planner to prototype interface implementations, plan clocks, and rapidly define a legal device floorplan. | | Design Partition Planner | Displays design entities, I/O banks, connectivity, design hierarchy, and design partition membership. Design Partition Planner can assist you in visualizing a design's structure for creating effective design partitions. |

Related Information

Design Floorplan Analysis in Chip Planner on page 166
Using Logic Lock Regions in Combination with Design Partitions on page 206
RTL Viewer Overview on page 19
Technology Map Viewer Overview on page 20
Quartus Prime Pro Edition User Guide: Design Compilation
Quartus Prime Pro Edition User Guide: Design Constraints
In Quartus Prime Pro Edition User Guide: Design Constraints

2.4.2. Design Optimization Tools

The Quartus Prime software provides tools help you identify design RTL and project settings that potentially limit performance.

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Table 3. Design Optimization Tools

| Tool | Description | To Access | |---------------------------------------------|-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|-----------------------------------------------------------------------------------| | Design Assistant | Automatically reports any violations against a standard set of recommended design guidelines, as Correct Design Assistant Rule Violations on page 76 describes. | Assignments ➤ Settings ➤ Design Assistant Rule Settings | | Fast Forward Timing Closure Recommendations | Fast Forward compilation generates design recommendations to help you to break performance bottlenecks and maximize use of Hyper-Registers to drive the highest performance in Stratix ® 10 and Agilex ™ FPGA portfolio designs, as Implement Fast Forward Timing Closure Recommendations on page 78 describes. | On the Compilation Dashboard, click Fast Forward Timing Closure Recommendations . | | Design Space Explorer II | Provides an easy and efficient way to run seed sweeps with different combinations of design settings and constraints to identify the optimal combination for your design, as Optimize Settings with Design Space Explorer II on page 107 describes. | Tools ➤ Launch Design Space Explorer II | | Assignment Back-Annotation Dialog Box | Back-annotation copies the last compilation's resource assignments to preserve your optimized implementation in subsequent compilations, as Back-Annotating Optimized Assignments on page 105 describes. | Assignments ➤ Back- Annotate Assignments |

Related Information

Quartus Prime Pro Edition User Guide: Design Compilation
•
Quartus Prime Pro Edition User Guide: Design Recommendations

2.5. Design Optimization Overview Revision History

The following revision history applies to this chapter:

3. Optimizing the Design Netlist

You can use the Quartus Prime Netlist Viewers to analyze and debug your design netlist.

Related Information

Quartus Prime Design Flow with the Netlist Viewers on page 18
RTL Viewer Overview on page 19
Technology Map Viewer Overview on page 20
Filtering in the Schematic View on page 32
Viewing a Timing Path on page 39

3.1. When to Use the Netlist Viewers: Analyzing Design Problems

You can use the Netlist Viewers to analyze and debug your design. The following simple examples show how to use the RTL Viewer and Technology Map Viewer to analyze problems encountered in the design process.

Using the RTL Viewer is a good way to view your initial synthesis results to determine whether you have created the necessary logic, and that the logic and connections have been interpreted correctly by the software. You can use the RTL Viewer to check your design visually before simulation or other verification processes. Catching design errors at this early stage of the design process can save you valuable time.

If you see unexpected behavior during verification, use the RTL Viewer to trace through the netlist and ensure that the connections and logic in your design are as expected. Viewing your design helps you find and analyze the source of design problems. If your design looks correct in the RTL Viewer, you know to focus your analysis on later stages of the design process and investigate potential timing violations or issues in the verification flow itself.

You can use the Technology Map Viewer to look at the results at the end of Analysis and Synthesis. If you have compiled your design through the Fitter stage, you can view your post-mapping netlist in the Technology Map Viewer (Post-Mapping) and your post-fitting netlist in the Technology Map Viewer. If you perform only Analysis and Synthesis, both the Netlist Viewers display the same post-mapping netlist.

In addition, you can use the RTL Viewer or Technology Map Viewer to locate the source of a particular signal, which can help you debug your design. Use the navigation techniques described in this chapter to search easily through your design. You can trace back from a point of interest to find the source of the signal and ensure the connections are as expected.

The Technology Map Viewer can help you locate post-synthesis nodes in your netlist and make assignments when optimizing your design. This functionality is useful when making a multicycle clock timing assignment between two registers in your design.

*Other names and brands may be claimed as the property of others.

Start at an I/O port and trace forward or backward through the design and through levels of hierarchy to find nodes of interest, or locate a specific register by visually inspecting the schematic.

Throughout your FPGA design, debug, and optimization stages, you can use all of the netlist viewers in many ways to increase your productivity while analyzing a design.

3.2. Quartus Prime Design Flow with the Netlist Viewers

When you first open one of the Netlist Viewers after compiling the design, a preprocessor stage runs automatically before the Netlist Viewer opens.

Click the link in the preprocessor process box to go to the Settings ➤ Compilation Process Settings page where you can turn on the Run Netlist Viewers preprocessing during compilation option. If you turn this option on, the preprocessing becomes part of the full project compilation flow and the Netlist Viewer opens immediately without displaying the preprocessing dialog box.

Figure 7. Quartus Prime Design Flow Including the RTL Viewer and Technology Map Viewer

This figure shows how Netlist Viewers fit into the basic Quartus Prime design flow.

Before the Netlist Viewer can run the preprocessor stage, you must compile your design:

To open the RTL Viewer first perform Analysis and Elaboration.
To open the Technology Map Viewer (Post-Fitting) or the Technology Map Viewer (Post-Mapping), first perform Analysis and Synthesis.

The Netlist Viewers display the results of the last successful compilation.

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Therefore, if you make a design change that causes an error during Analysis and Elaboration, you cannot view the netlist for the new design files, but you can still see the results from the last successfully compiled version of the design files.
If you receive an error during compilation and you have not yet successfully run the appropriate compilation stage for your project, the Netlist Viewer cannot be displayed; in this case, the Quartus Prime software issues an error message when you try to open the Netlist Viewer.

If the Netlist Viewer is open when you start a new compilation, the Netlist Viewer closes automatically. You must open the Netlist Viewer again to view the new design netlist after compilation completes successfully.

Note:

3.3. RTL Viewer Overview

The RTL Viewer allows you to view a register transfer level (RTL) graphical representation of Quartus Prime Pro Edition synthesis results or third-party netlist files in the Quartus Prime software.

You can view results after Analysis and Elaboration for designs that use any supported Quartus Prime design entry method, including Verilog HDL Design Files ( .v ), SystemVerilog Design Files ( .sv ), VHDL Design Files ( .vhd ), AHDL Text Design Files ( .tdf ), or schematic Block Design Files ( .bdf ).

You can also view the hierarchy of atom primitives (such as device logic cells and I/O ports) for designs that generate Verilog Quartus Mapping File ( .vqm ) or Electronic Design Interchange Format ( .edf ) files through a synthesis tool.

The RTL Viewer displays a schematic view of the design netlist after Analysis and Elaboration or after the Quartus Prime software performs netlist extraction, but before technology mapping and synthesis or fitter optimizations. This view a preliminary preoptimization design structure and closely represents the original source design.

For designs synthesized with the Quartus Prime Pro Edition synthesis, this view shows how the Quartus Prime software interprets the design files.
For designs synthesized with a third-party synthesis tool, this view shows the netlist that the synthesis tool generates.

To run the RTL Viewer for an Quartus Prime project, first analyze the design to generate an RTL netlist. To analyze the design and generate an RTL netlist, click Processing ➤ Start ➤ Start Analysis & Elaboration . You can also perform a full compilation on any process that includes the initial Analysis and Elaboration stage of the Quartus Prime compilation flow.

To open the RTL Viewer, click Tools ➤ Netlist Viewers ➤ RTL Viewer .

3.3.1. Maximizing Readability in RTL Viewer

While displaying a design, the RTL Viewer optimizes the netlist to maximize readability:

Removes logic with no fan-out (unconnected output) or fan-in (unconnected inputs) from the display.
Hides default connections such as VCC and GND.
Groups pins, nets, wires, module ports, and certain logic into buses where appropriate.
Groups constant bus connections.
Displays values in hexadecimal format.
Converts NOT gates into bubble inversion symbols in the schematic.
Merges chains of equivalent combinational gates into a single gate; for example, a 2-input AND gate feeding a 2-input AND gate is converted to a single 3-input AND gate.

3.3.2. Running the RTL Viewer

To run the RTL Viewer for an Quartus Prime project:

Analyze the design to generate an RTL netlist by clicking Processing ➤ Start ➤ Start Analysis & Elaboration .

You can also perform a full compilation on any process that includes the initial Analysis and Elaboration stage of the Quartus Prime compilation flow.

Open the RTL Viewer by clicking Tools ➤ Netlist Viewers ➤ RTL Viewer .

3.4. Technology Map Viewer Overview

The Quartus Prime Technology Map Viewer provides a technology-specific, graphical representation of FPGA designs after Analysis and Synthesis or after the Fitter maps the design into the target device.

The Technology Map Viewer shows the hierarchy of atom primitives (such as device logic cells and I/O ports) in the design. For supported device families, you can also view internal registers and look-up tables (LUTs) inside logic cells (LCELLs), and registers in I/O atom primitives.

Where possible, the Quartus Prime software maintains the port names of each hierarchy throughout synthesis. However, the software may change or remove port names from the design. For example, the software removes ports that are unconnected or driven by GND or VCC during synthesis. If a port name changes, the software assigns a related user logic name in the design or a generic port name such as IN1 or OUT1 .

You can view Quartus Prime technology-mapped results after synthesis, fitting, or timing analysis. To run the Technology Map Viewer for an Quartus Prime project, on the Processing menu, point to Start and click Start Analysis & Synthesis to synthesize and map the design to the target technology. At this stage, the Technology Map Viewer shows the same post-mapping netlist as the Technology Map Viewer (Post-Mapping). You can also perform a full compilation, or any process that includes the synthesis stage in the compilation flow.

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For designs that completed the Fitter stage, the Technology Map Viewer shows how the Fitter changed the netlist through physical synthesis optimizations, while the Technology Map Viewer (Post-Mapping) shows the post-mapping netlist. If you have completed the Timing Analysis stage, you can locate timing paths from the Timing Analyzer report in the Technology Map Viewer.

To open the Technology Map Viewer, click Tools ➤ Netlist Viewers ➤ Technology Map Viewer (Post-Fitting) or Technology Map Viewer (Post Mapping) .

Related Information

Viewing a Timing Path on page 39
View Contents of Nodes in the Schematic View on page 32

3.5. Netlist Viewer User Interface

The Netlist Viewer is a graphical user-interface for viewing and manipulating nodes and nets in the netlist.

The RTL Viewer and Technology Map Viewer each consist of these main parts:

The Netlist Navigator pane-displays a representation of the project hierarchy.
The Find pane-allows you to find and locate specific design elements in the schematic view.
The Properties pane-displays the properties of the selected block when you select Properties from the shortcut menu.
The schematic view-displays a graphical representation of the internal structure of the design.

Figure 8. RTL Viewer

Netlist Viewers also contain a toolbar that provides tools to use in the schematic view.

Use the Back and Forward buttons to switch between schematic views.
Click the Next Page or Previous Page buttons to navigate directly to the next or previous page, respectively. These buttons are helpful when a long schematic partitions to multiple pages.
The Refresh button to restore the schematic view and optimizes the layout. Refresh does not reload the database if you change the design and recompile.
Click the Find button opens and closes the Find pane.
Click the Selection Tool and Zoom Tool buttons to alternate between the selection mode and zoom mode.
Click the Fit in Window button resets the schematic view to encompass the entire design.
Click the Fit Selection in Window button resets the schematic view to encompass the entire selection.
Use the Hand Tool to change the focus of the viewer without changing the perspective.
Click the Area Selection Tool to drag a selection box around ports, pins, and nodes in an area.
Click the Netlist Navigator button to open or close the Netlist Navigator pane.
Click the Color Settings button to open the Colors pane where you can customize the Netlist Viewer color scheme.

Figure 9. Display Settings

Click the Display Settings button to open the Display pane where you can specify the following settings:
Show full name or Show only < n > characters . You can specify this separately for Node name , Port name , Pin name , or Bus index name .
Turn Show timing info on or off.
Turn Show node type on or off.
[ ] ○ Turn Show constant value on or off.
[ ] ○ Turn Show flat nets on or off.
Turn Maintain selection when expand hierarchy on or off.
Turn Enable rollover on or off.
Turn Show located objects in new tab on or off.
The Bird's Eye View button opens the Bird's Eye View window which displays a miniature version of the design and allows you to navigate within the design and adjust the magnification in the schematic view quickly.
The Show/Hide Instance Pins button can alternate the display of instance pins not displayed by functions such as cross-probing between a Netlist Viewer and Timing Analyzer. You can also use this button to hide unconnected instance pins when filtering a node results in large numbers of unconnected or unused pins. The Netlist Viewer hides Instance pins by default.
If the Netlist Viewer display encompasses several pages, the Show Netlist on One Page button resizes the netlist view to a single page. This action can make netlist tracing easier.
Click the Highlight list to apply a highlight color to the objects that you select in the schematic. Unhighlight objects with Unhighlight or Unhighlight All from the right-click menu.

You can have only one RTL Viewer, one Technology Map Viewer (Post-Fitting), and one Technology Map Viewer (Post-Mapping) window open at the same time, although each window can show multiple pages, each with multiple tabs. For example, you cannot have two RTL Viewer windows open at the same time.

Related Information

Netlist Navigator Pane on page 23
Netlist Viewers Find Pane on page 25
Properties Pane on page 24

3.5.1. Netlist Navigator Pane

The Netlist Navigator pane displays the entire netlist in a tree format based on the hierarchical levels of the design. Each level groups similar elements into subcategories.

The Netlist Navigator pane allows you to traverse through the design hierarchy to view the logic schematic for each level. You can also select an element in the Netlist Navigator to highlight in the schematic view.

Note: The Netlist Navigator pane does not list nodes inside atom primitives.

For each module in the design hierarchy, the Netlist Navigator pane displays the applicable elements listed in the following table. Click the ' + ' icon to expand an element.

Table 4. Netlist Navigator Pane Elements

| Elements | Description | |------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | Instances | Modules or instances in the design that can be expanded to lower hierarchy levels. | | Primitives | Low-level nodes that cannot be expanded to any lower hierarchy level. These primitives include: • Registers and gates that you can view in the RTL Viewer when using Quartus Prime Pro Edition synthesis. • Logic cell atoms in the Technology Map Viewer or in the RTL Viewer when using a VQM or EDIF from third-party synthesis software In the Technology Map Viewer, you can view the internal implementation of certain atom primitives, but you cannot traverse into a lower-level of hierarchy. | | Ports | The I/O ports in the current level of hierarchy. • Pins are device I/O pins when viewing the top hierarchy level and are I/O ports of the design when viewing the lower-levels. • When a pin represents a bus or an array of pins, expand the pin entry in the list view to see individual pin names. |

3.5.2. Properties Pane

You can view the properties of an instance or primitive with the Properties pane.

Figure 10. Properties Pane

To view the properties of an instance or primitive in the RTL Viewer or Technology Map Viewer, right-click the node and click Properties .

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The Properties pane contains tabs with the following information about the selected node:

The Fan-in tab displays the Input port and Fan-in Node .
The Fan-out tab displays the Output port and Fan-out Node .
The Parameters tab displays the Parameter Name and Values of an instance.
The Ports tab displays the Port Name and Constant value (for example, VCC or GND). The following table lists the possible values of a port:

Table 5. Possible Port Values

| Value | Description | |-------------|--------------------------------------------------------------| | V CC | The port is not connected and has V CC value (tied to V CC ) | | GND | The port is not connected and has GND value (tied to GND) | | -- | The port is connected and has value (other than V CC or GND) | | Unconnected | The port is not connected and has no value (hanging) |

If the selected node is an atom primitive, the Properties pane displays a schematic of the internal logic.

3.5.3. Netlist Viewers Find Pane

You can narrow the range of the search process by setting the following options in the Find pane:

Figure 11. Find Options

Click Browse (…) next to Look in to specify the hierarchy level of the search. In the Select Hierarchy Level dialog box, you can select a particular instance you want to search.
Turn on the Include subentities option to include child hierarchies of the parent instance during the search.
Under Find Options , turn on or off Match case , Use regular expressions , Find whole words only , or any combination of the three option, to further refine the parameters of the search.
Under Find In , turn on or off Instances , Ports , Nodes , All or any combination of options, to further refine the parameters of the search.

When you click the Find All button, a progress bar appears below the Find box.

All results that match the criteria you set are listed in a table. When you double-click an item in the table, the related node is highlighted in red in the schematic view.

3.6. Schematic View

The schematic view is shown on the right side of the RTL Viewer and Technology Map Viewer. The schematic view contains a schematic representing the design logic in the netlist. This view is the main screen for viewing your gate-level netlist in the RTL Viewer and your technology-mapped netlist in the Technology Map Viewer.

The RTL Viewer and Technology Map Viewer attempt to display schematic in a single page view by default. If the schematic crosses over to several pages, you can highlight a net and use connectors to trace the signal in a single page.

3.6.1. Display Schematics in Multiple Tabbed View

The RTL Viewer and Technology Map Viewer support multiple tabbed views.

With multiple tabbed view, schematics can be displayed in different tabs. Selection is independent between tabbed views, but selection in the tab in focus is synchronous with the Netlist Navigator pane.

To create a new blank tab, click the New Tab button at the end of the tab row . You can now drag a node from the Netlist Navigator pane into the schematic view.

Right-click in a tab to see a shortcut menu to perform the following actions:

Create a blank view with New Tab
Create a Duplicate Tab of the tab in focus
Choose to Cascade Tabs
Choose to Tile Tabs
Choose Close Tab to close the tab in focus
Choose Close Other Tabs to close all tabs except the tab in focus

3.6.2. Schematic Symbols

The symbols for nodes in the schematic represent elements of your design netlist. These elements include input and output ports, registers, logic gates, Altera primitives, high-level operators, and hierarchical instances.

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Note:

The logic gates and operator primitives appear only in the RTL Viewer. Logic in the Technology Map Viewer is represented by atom primitives, such as registers and LCELLs.

Table 6. Symbols in the Schematic View

This table lists and describes the primitives and basic symbols that you can display in the schematic view of the RTL Viewer and Technology Map Viewer.

| Symbol | Description | |--------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | Wire indicator and net ripper | Indicates the net signal flow direction into or out of the pin or port. There can be symbols in both directions due to automatic net bundling from the connectivity. You can click the net to highlight the signal flow details in the schematic. | | I/O Ports CLK_SEL[1:0] RESET_N | An input, output, or bidirectional port in the current level of hierarchy. A device input, output, or bidirectional pin when viewing the top-level hierarchy. The symbol can also represent a bus. Only one wire is shown connected to the bidirectional symbol, representing the input and output paths. Input symbols appear on the left-most side of the schematic. Output and bidirectional symbols appear on the right-most side of the schematic. | | I/O Connectors MEM_OE_N | An input or output connector, representing a net that comes from another page of the same hierarchy. To go to the page that contains the source or the destination, double-click the connector to jump to the appropriate page. | | OR, AND, XOR Gates always1 | An OR, AND, or XOR gate primitive (the number of ports can vary). A small circle (bubble symbol) on an input or output port indicates the port is inverted. | | MULTIPLEXER | A multiplexer primitive with a selector port that selects between port 0 and port 1 . A multiplexer with more than two inputs is displayed as an operator. |

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| Symbol | Description | |-------------------------------------------------------|-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | BUFFER OE DATAIN OUT0 | A buffer primitive. The figure shows the tri-state buffer, with an inverted output enable port. Other buffers without an enable port include LCELL, SOFT, and GLOBAL. The NOT gate and EXP expander buffers use this symbol without an enable port and with an inverted output port. | | LATCH PRE D ENA Q latch CLR | A latch/DFF (data flipflop) primitive. A DFF has the same ports as a latch and a clock trigger. The other flipflop primitives are similar: • DFFEA (data flipflop with enable and asynchronous load) primitive with additional ALOAD asynchronous load and ADATA data signals • DFFEAS (data flipflop with enable and synchronous and asynchronous load), which has ASDATA as the secondary data port | | Atom Primitive DATAA F | An atom primitive. The symbol displays the atom name, the port names, and the atom type. The blue shading indicates an atom primitive for which you can view the internal details. | | Other Primitive CPU_D[10] | Any primitive that does not fall into the previous categories. Primitives are low-level nodes that cannot be expanded to any lower hierarchy. The symbol displays the port names, the primitive or operator type, and its name. | | Instance speed_ch:speed get_ticket accel_in clk reset | An instance in the design that does not correspond to a primitive or operator (a user-defined hierarchy block). The symbol displays the port name and the instance name. | | Encrypted Instance | A user-defined encrypted instance in the design. The symbol displays the instance name. You cannot open the schematic for the lower-level hierarchy, because the source design is encrypted. |

Table 7. Operator Symbols in the RTL Viewer Schematic View

The following lists and describes the additional higher level operator symbols in the RTL Viewer schematic view.

| Symbol | Description | |-----------------------------|--------------------------------| | Add0 A[3:0] B[3:0] OUT[3:0] | An adder operator: OUT = A + B |

| Symbol | Description | |----------------------------------|-------------------------------------------------------------------------| | Mult0 A[0] B[0] OUT[0] | A multiplier operator: OUT = A ¥ B | | Div0 A[0] B[0] OUT[0] | A divider operator: OUT = A / B | | Equal3 A[1:0] B[1:0] OUT | Equals | | ShiftLeft0 A[0] COUNT[0] OUT[0] | A left shift operator: OUT = (A << COUNT) | | ShiftRight0 A[0] COUNT[0] OUT[0] | A right shift operator: OUT = (A >> COUNT) | | Mod0 A[0] B[0] OUT[0] | A modulo operator: OUT = (A%B) | | LessThan0 A[0] B[0] OUT | A less than comparator: OUT = (A<:B:A>B) | | Mux5 SEL[2:0] DATA[7:0] OUT | A multiplexer: OUT = DATA [SEL] The data range size is 2 sel range size | | continued... | |

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| Symbol | Description | |----------------------------------|---------------------------------------------------------------------------------------| | Selector1 SEL[2:0] DATA[2:0] OUT | A selector: A multiplexer with one-hot select input and more than two input signals | | Decoder0 IN[5:0] OUT[63:0] | A binary number decoder: OUT = (binary_number ( IN ) == x) for x = 0 to x = 2 n +1 -1 |

Related Information

Partition the Schematic into Pages on page 37
Follow Nets Across Schematic Pages on page 37

3.6.3. Select Items in the Schematic View

To select an item in the schematic view, ensure that the Selection Tool is enabled in the Netlist Viewer toolbar. Click an item in the schematic view to highlight in red.

Select multiple items by pressing the Shift key while selecting with the mouse.

Items selected in the schematic view are automatically selected in the Netlist Navigator pane. The folder then expands automatically if it is required to show the selected entry; however, the folder does not collapse automatically when you deselected the entries.

When you select a hierarchy box, node, or port in the schematic view, the Schematic View highlights the item in red, but not the connecting nets. When you select a net (wire or bus) in the schematic view, the Schematic View highlights all connected nets in red.

Once you select an item, you can perform different actions on it based on the contents of the shortcut menu which appears when you right-click your selection.

Related Information

Netlist Navigator Pane on page 23

3.6.4. Shortcut Menu Commands in the Schematic View

When you right-click a selected instance or primitive in the schematic view, the Netlist Viewer displays a shortcut menu.

If the selected item is a node, you see the following options:

Click Expand to Upper Hierarchy to displays the parent hierarchy of the node in focus.
Click Copy ToolTip to copy the selected item name to the clipboard. This command does not work on nets.
Click Hide Selection to remove the selected item from the schematic view. This command does not delete the item from the design, merely masks it in the current view.
Click Filtering to display a sub-menu with options for filtering your selection.

3.6.5. Filtering in the Schematic View

Filtering allows you to filter out nodes and nets in a netlist to view only the logic elements of interest to you.

You can filter a netlist by selecting hierarchy boxes, nodes, or ports of a node, that are part of the path you want to see. The following filter commands are available:

Sources -displays the sources of the selection.
Destinations -displays the destinations of the selection.
Sources & Destinations -displays the sources and destinations of the selection.
Selected Nodes -displays only the selected nodes.
Between Selected Nodes -displays nodes and connections in the path between the selected nodes.
Bus Index -Displays the sources or destinations for one or more indexes of an output or input bus port.
Filtering Options -Displays the Filtering Options dialog box:
Stop filtering at register -Turning on this option directs the Netlist Viewer to filter out to the nearest register boundary.
Filter across hierarchies -Turning on this option directs the Netlist Viewer to filter across hierarchies.
Maximum number of hierarchy levels -Sets the maximum number of hierarchy levels that the schematic view can display.

To filter a netlist, select a hierarchy box, node, port, net, or state node, right-click in the window, point to Filter and click the appropriate filter command. The Netlist Viewer generates a new page showing the netlist that remains after filtering.

3.6.6. View Contents of Nodes in the Schematic View

In the RTL Viewer and the Technology Map Viewer, you can view the contents of nodes to see their underlying implementation details.

You can view LUTs, registers, and logic gates. You can also view the implementation of RAM and DSP blocks in certain devices in the RTL Viewer or Technology Map Viewer. In the Technology Map Viewer, you can view the contents of primitives to see their underlying implementation details.

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Figure 12. Wrapping and Unwrapping Objects

If you can unwrap the contents of an instance, a plus symbol appears in the upper right corner of the object in the schematic view. To wrap the contents (and revert to the compact format), click the minus symbol in the upper right corner of the unwrapped instance.

one wire_top:one_wire inst top

In the schematic view, the internal details in an atom instance cannot be selected as individual nodes. Any mouse action on any of the internal details is treated as a mouse action on the atom instance.

Note:

Figure 13. Nodes with Connections Outside the Hierarchy

In some cases, the selected instance connects to something outside the visible level of the hierarchy in the schematic view. In this case, the net appears as a dotted line. Double-click the dotted line to expand the view to display the destination of the connection .

Figure 14. Display Nets Across Hierarchies

In cases where the net connects to an instance outside the hierarchy, you can select the net, and unwrap the node to see the destination ports.

Figure 15. Show Connectivity Details

You can select a port, pin, bus port or bus pin and click Connectivity Details in the context menu for that object.

You can double-click objects in the Connectivity Details window to navigate to them quickly. If the plus symbol appears, you can further unwrap objects in the view. This can be very useful when tracing a signal in a complex netlist.

3.6.7. Moving Nodes in the Schematic View

Rearrange items in the schematic view by dragging to destination.

To move a node from one area of the netlist to another, select the node and hold down the Shift key. Legal placements appear as shaded areas within the hierarchy. Click to drop the selected node.

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Figure 16. Legal Placement when Moving Nodes

To restore the schematic view to its default arrangement, right-click and click Refresh .

3.6.8. View LUT Representations in the Technology Map Viewer

You can view different representations of a LUT by right-clicking the selected LUT and clicking Properties .

You can view the LUT representations in the following three tabs in the Properties dialog box:

The Schematic tab-the equivalent gate representations of the LUT.
The Truth Table tab-the truth table representations.

LUT representations in the Tech Map Viewer are only available for Arria ® 10 devices and Cyclone ® 10 GX devices in the Quartus Prime Pro Edition software.

Related Information

Properties Pane on page 24

3.6.9. Zoom Controls

Use the Zoom Tool in the toolbar, or mouse gestures, to control the magnification of your schematic on the View menu.

By default, the Netlist Viewer displays most pages sized to fit in the window. If the schematic page is very large, the schematic is displayed at the minimum zoom level, and the view is centered on the first node. Click Zoom In to view the image at a larger size, and click Zoom Out to view the image (when the entire image is not displayed) at a smaller size. The Zoom command allows you to specify a magnification percentage (100% is considered the normal size for the schematic symbols).

Note:

You can use the Zoom Tool on the Netlist Viewer toolbar to control magnification in the schematic view. When you select the Zoom Tool in the toolbar, clicking in the schematic zooms in and centers the view on the location you clicked. Right-click in the schematic to zoom out and center the view on the location you clicked. When you select the Zoom Tool, you can also zoom into a certain portion of the schematic by selecting a rectangular box area with your mouse cursor. The schematic is enlarged to show the selected area.

Within the schematic view, you can also use the following mouse gestures to zoom in on a specific section:

zoom in -Dragging a box around an area starting in the upper-left and dragging to the lower right zooms in on that area.
zoom -0.5 -Dragging a line from lower-left to upper-right zooms out 0.5 levels of magnification.
zoom 0.5 -Dragging a line from lower-right to upper-left zooms in 0.5 levels of magnification.
zoom fit -Dragging a line from upper-right to lower-left fits the schematic view in the page.

Related Information

Filtering in the Schematic View on page 32

3.6.10. Navigating with the Bird's Eye View

To open the Bird's Eye View, on the View menu, click Bird's Eye View , or click the Bird's Eye View icon in the toolbar.

Figure 17. Birds Eye View Button on Chip Planner Toolbar

Show Delays Button

Viewing the entire schematic can be useful when debugging and tracing through a large netlist. The Quartus Prime software allows you to quickly navigate to a specific section of the schematic using the Bird's Eye View feature, which is available in the RTL Viewer and Technology Map Viewer.

The Bird's Eye View shows the current area of interest:

Select an area by clicking and dragging the indicator or right-clicking to form a rectangular box around an area.
Click and drag the rectangular box to move around the schematic.
Resize the rectangular box to zoom-in or zoom-out in the schematic view.

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3.6.11. Partition the Schematic into Pages

For large design hierarchies, the RTL Viewer and Technology Map Viewer partition your netlist into multiple pages in the schematic view.

When a hierarchy level is partitioned into multiple pages, the title bar for the schematic window indicates which page is displayed and how many total pages exist for this level of hierarchy. The schematic view displays this as Page < current page number > of < total number of pages >.

Related Information

Netlist Viewer User Interface on page 21

3.6.12. Follow Nets Across Schematic Pages

Input and output connector symbols indicate nodes that connect across pages of the same hierarchy. Double-click a connector to trace the net to the next page of the hierarchy.

Note:

After you double-click to follow a connector port, the Netlist Viewer opens a new page, which centers the view on the particular source or destination net using the same zoom factor as the previous page. To trace a specific net to the new page of the hierarchy, Altera recommends that you first select the necessary net, which highlights it in red, before you double-click to navigate across pages.

Related Information

Schematic Symbols on page 26

3.7. Cross-Probing to a Source Design File and Other Quartus Prime Windows

The RTL Viewer and Technology Map Viewer allow you to cross-probe to the source design file and to various other windows in the Quartus Prime software.

You can select one or more hierarchy boxes, nodes, state nodes, or state transition arcs that interest you in the Netlist Viewer and locate the corresponding items in another applicable Quartus Prime software window. You can then view and make changes or assignments in the appropriate editor or floorplan.

To locate an item from the Netlist Viewer in another window, right-click the items of interest in the schematic or state diagram, point to Locate , and click the appropriate command. The following commands are available:

Locate in Assignment Editor
Locate in Pin Planner
Locate in Chip Planner
Locate in Resource Property Editor
Locate in Technology Map Viewer
Locate in RTL Viewer
Locate in Design File

The options available for locating an item depend on the type of node and whether it exists after placement and routing. If a command is enabled in the menu, it is available for the selected node. You can use the Locate in Assignment Editor command for all nodes, but assignments might be ignored during placement and routing if they are applied to nodes that do not exist after synthesis.

The Netlist Viewer automatically opens another window for the appropriate editor or floorplan and highlights the selected node or net in the newly opened window. You can switch back to the Netlist Viewer by selecting it in the Window menu or by closing, minimizing, or moving the new window.

3.8. Cross-Probing to the Netlist Viewers from Other Quartus Prime Windows

You can cross-probe to the RTL Viewer and Technology Map Viewer from other windows in the Quartus Prime software. You can select one or more nodes or nets in another window and locate them in one of the Netlist Viewers.

You can locate nodes between the RTL Viewer and Technology Map Viewer, and you can locate nodes in the RTL Viewer and Technology Map Viewer from the following Quartus Prime software windows:

Project Navigator
Chip Planner
Resource Property Editor
Node Finder
Assignment Editor
Messages Window
Compilation Report
Timing Analyzer (supports the Technology Map Viewer only)

To locate elements in the Netlist Viewer from another Quartus Prime window, select the node or nodes in the appropriate window; for example, select an entity in the Entity list on the Hierarchy tab in the Project Navigator, or select nodes in the Timing Closure Floorplan, or select node names in the From or To column in the Assignment Editor. Next, right-click the selected object, point to Locate , and click Locate in RTL Viewer or Locate in Technology Map Viewer . After you click this command, the Netlist Viewer opens, or is brought to the foreground if the Netlist Viewer is open. In addition, the Locate history pane displays a list of the items that you locate. Use the Locate history pane to easily rerun cross-probing directly within the RTL Viewer or Technology Map Viewer. The Show located objects in new tab option always displays the found items in a new tab, as Netlist Viewer User Interface on page 21 describes.

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Figure 18. Locate History Pane

Note: The first time the window opens after a compilation, the preprocessor stage runs before the Netlist Viewer opens.

The Netlist Viewer shows the selected nodes and, if applicable, the connections between the nodes. The display is similar to what you see if you right-click the object, then click Filter ➤ Selected Nodes using Filter across hierarchy . If the nodes cannot be found in the Netlist Viewer, a message box displays the message: Can't find requested location .

3.9. Viewing a Timing Path

After completing a full design compilation, including the timing analyzer stage, you can see a visual representation of a timing path cross-probe from a timing report. For details about generating the timing report, refer to the Quartus Prime Pro Edition User Guide: Timing Analyzer .

When you locate the timing path from the Timing Analyzer to the Technology Map Viewer, the interconnect and cell delay associated with each node appears on top of the schematic symbols. The total slack of the selected timing path appears in the Page Title section of the schematic.

To open the report from the Compilation Report Table of Contents, click Timing Analyzer GUI ➤ Report Timing , and double-click the timing corner.
To open the report from the Timing Analyzer , open the Report Timing folder in the Report pane, and double-click the timing corner.
In the Summary of Paths tab, right-click a row in the table and select Locate Path ➤ Locate in Technology Map Viewer . In the Technology Map Viewer, the schematic page displays the nodes along the timing path with a summary of the total delay.

Related Information

Quartus Prime Pro Edition User Guide: Timing Analyzer

3.10. Optimizing the Design Netlist Revision History

The following revision history applies to this chapter:

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4. Netlist Optimizations and Physical Synthesis

The Quartus Prime software offers netlist optimizations during synthesis, and physical synthesis optimization during fitting, that can improve the performance of your design. Synthesis netlist optimizations operate with the atom netlist of your design, which describes a design in terms of specific primitives. This chapter provides guidelines for applying synthesis and physical synthesis optimization settings.

You can access a range of global synthesis and physical synthesis optimization settings from the Compiler Settings page:

Table 8. Synthesis Netlist Optimization and Physical Synthesis Options

| Options | Location/Description | |------------------------------------------------|-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | Enable synthesis netlist optimization settings | Enable synthesis optimization options (for example, Synthesis Effort ) in the Advanced Synthesis Settings dialog box. Click Assignments ➤ Settings ➤ Compiler Settings ➤ Advanced Settings (Synthesis) to access these options. | | Enable physical synthesis options | Enable physical synthesis options (for example, Advanced Physical Synthesis ) in the Advanced Fitter Settings dialog box. Click Assignments ➤ Settings ➤ Compiler Settings ➤ Advanced Settings (Fitter) to access these settings. |

Note:

Because the node names for primitives in the design can change when you use physical synthesis optimizations, you should evaluate whether your design depends on fixed node names. If you use a verification flow that might require fixed node names, such as the Signal Tap Logic Analyzer, formal verification, or the Logic Lock based optimization flow (for legacy devices), disable physical synthesis options.

4.1. Physical Synthesis Optimizations

The Quartus Prime Fitter places and routes the logic cells to ensure critical portions of logic are close together and use the fastest possible routing resources. However, routing delays are often a significant part of the typical critical path delay. Physical synthesis optimizations take into consideration placement information, routing delays, and timing information to determine the optimal placement. The Fitter then focuses timing-driven optimizations at those critical parts of the design. The tight integration of the synthesis and fitting processes is known as physical synthesis.

The following sections describe the physical synthesis optimizations available in the Quartus Prime software, and how they can help improve performance and fitting for the selected device.

Related Information

Compiler Settings Page (Settings Dialog Box)

In Quartus Prime Help

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4.1.1. Disabling or Enabling Physical Synthesis Optimization

Physical synthesis optimization improves circuit performance by performing combinational and sequential optimization and register duplication.

The Compiler performs physical synthesis optimization by default during place and route. You can disable or enable physical synthesis optimization and related options by following these steps:

To disable or enable physical synthesis optimization:

Click Assignments ➤ Settings ➤ Compiler Settings .
To enable retiming, combinational optimization, and register duplication, click Advanced Settings (Fitter) .
Enable Advanced Physical Synthesis .
View physical synthesis results in the Netlist Optimizations report under Compilation Report ➤ Fitter section.

4.1.2. Physical Synthesis Options

The Quartus Prime software provides physical synthesis optimization options to improve fitting results. To access these options, click Assignments ➤ Settings ➤ Compiler Settings ➤ Advanced Settings (Fitter) .

Note:

To disable global physical synthesis optimizations for specific elements of your design, assign the Netlist Optimizations logic option to Never Allow to the specific nodes or entities.

Table 9. Physical Synthesis Options

| Option | Description | |-----------------------------|----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | Advanced Physical Synthesis | Uses the physical synthesis engine to perform combinational and sequential optimization during fitting to improve circuit performance. | | Netlist Optimizations | You can use the Assignment Editor to apply the Netlist Optimizations logic option. Use this option to disable physical synthesis optimizations for parts of your design. This option is available only for Arria 10 and Cyclone 10 GX devices. | | Allow Register Duplication | Allows the Compiler to duplicate registers to improve design performance. When you enable this option, the Compiler copies registers and moves some fan-out to this new node. This optimization improves routability and can reduce the total routing wire in nets with many fan-outs. If you disable this option, this disables optimizations that retime registers. This setting affects Analysis & Synthesis and the Fitter. This option is available only for Arria 10 and Cyclone 10 GX devices. | | Allow Register Merging | Allows the Compiler to remove registers that are identical to other registers in the design. When you enable this option, in cases where two registers generate the same logic, the Compiler deletes one register, and the remaining registers fan-out to the deleted register's destinations. This option is useful if you want to prevent the Compiler from removing intentional use of duplicate registers. If you disable register merging, the Compiler disables optimizations that retime registers. This setting affects Analysis & Synthesis and the Fitter. |

4.2. Applying Netlist Optimizations

The improvement in performance when using netlist optimizations is design dependent. If you have restructured your design to balance critical path delays, netlist optimizations might yield minimal improvement in performance.

You may have to experiment with available options to see which combination of settings works best for a particular design. Refer to the messages in the compilation report to see the magnitude of improvement with each option, and to help you decide whether you should turn on a given option or specific effort level.

Turning on more netlist optimization options can result in more changes to the node names in the design; bear this in mind if you are using a verification flow, such as the Signal Tap Logic Analyzer or formal verification that requires fixed or known node names.

To find the best results, you can use the Quartus Prime Design Space Explorer II (DSE) to apply various sets of netlist optimization options.

Related Information

Optimize Settings with Design Space Explorer II on page 107

4.2.1. WYSIWYG Primitive Resynthesis

For designs synthesized with a third-party tool, the Perform WYSIWYG primitive resynthesis option allows you to apply optimizations to the synthesized netlist.

The Perform WYSIWYG primitive resynthesis option directs the Quartus Prime software to un-map the logic elements (LEs) in an atom netlist to logic gates, and then re-map the gates back to Altera-specific primitives. Third-party synthesis tools generate either an .edf or .vqm atom netlist file using Altera-specific primitives. When you turn on the Perform WYSIWYG primitive resynthesis option, the Quartus Prime software uses device-specific techniques during the re-mapping process. This feature re-maps the design using the Optimization Technique specified for your project ( Speed , Area , or Balanced ).

The Perform WYSIWYG primitive resynthesis option unmaps and remaps only logic cells, also referred to as LCELL or LE primitives, and regular I/O primitives (which may contain registers). Double data rate (DDR) I/O primitives, memory primitives, digital signal processing (DSP) primitives, and logic cells in carry chains are not remapped. This process does not process logic specified in an encrypted .vqm file or an .edf file, such as third-party intellectual property (IP).

The Perform WYSIWYG primitive resynthesis option can change node names in the .vqm file or .edf file from your third-party synthesis tool, because the primitives in the atom netlist are broken apart and then re-mapped by the Quartus Prime software. The re-mapping process removes duplicate registers. Registers that are not removed retain the same name after re-mapping.

Any nodes or entities that have the Netlist Optimizations logic option set to Never Allow are not affected during WYSIWYG primitive resynthesis. You can use the Assignment Editor to apply the Netlist Optimizations logic option. This option disables WYSIWYG resynthesis for parts of your design.

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Note:

Primitive node names are specified during synthesis. When netlist optimizations are applied, node names might change because primitives are created and removed. HDL attributes applied to preserve logic in third-party synthesis tools cannot be maintained because those attributes are not written into the atom netlist, which the Quartus Prime software reads.

If you use the Quartus Prime software to synthesize your design, you can use the Preserve Register (preserve) and Keep Combinational Logic (keep) attributes to maintain certain nodes in the design.

Figure 19. Quartus Prime Flow for WYSIWYG Primitive Resynthesis

4.3. Scripting Support

You can run procedures and make settings described in this chapter in a Tcl script. You can also run some procedures at a command prompt. For detailed information about scripting command options, refer to the Quartus Prime Command-Line and Tcl API Help browser. To run the Help browser, type the following command at the command prompt:

quartus_sh --qhelp

You can specify many of the options described in this section on either an instance or global level, or both.

Use the following Tcl command to make a global assignment:

set_global_assignment -name <QSF variable name> <value>

Use the following Tcl command to make an instance assignment:

set_instance_assignment -name <QSF variable name> <value> -to <instance name>

Related Information

Quartus Prime Pro Edition User Guide: Scripting

Quartus Prime Pro Edition User Guide: Design Optimization

4.3.1. Synthesis Netlist Optimizations

The project .qsf file preserves the settings that you specify in the GUI. Alternatively, you can edit the .qsf directly. The .qsf file supports the following synthesis netlist optimization commands. The Type column indicates whether the setting is supported as a global setting, an instance setting, or both.

Table 10. Synthesis Netlist Optimizations and Associated Settings

| Setting Name | Quartus Prime Settings File Variable Name | Values | Type | |---------------------------------------|---------------------------------------------|------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|------------------| | Perform WYSIWYG Primitive Resynthesis | ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP | ON , OFF | Global, Instance | | Optimization Mode | OPTIMIZATION_MODE | BALANCED , HIGH PERFORMANCE EFFORT , HIGH PERFORMANCE EFFORT WITH MAXIMUM PLACEMENT EFFORT , HIGH PERFORMANCE WITH AGGRESSIVE POWER EFFORT , SUPERIOR PERFORMANCE , SUPERIOR PERFORMANCE WITH MAXIMUM PLACEMENT EFFORT , AGGRESSIVE AREA , HIGH PLACEMENT ROUTABILITY EFFORT , HIGH PACKING ROUTABILITY EFFORT , OPTIMIZE NETLIST FOR ROUTABILITY , AGGRESSIVE POWER , | Global, Instance | | Power-Up Don't Care | ALLOW_POWER_UP_DONT_CARE | ON , OFF | Global |

4.3.2. Physical Synthesis Optimizations

Table 11. Physical Synthesis Optimizations and Associated Settings

| Setting Name | Quartus Prime Settings File Variable Name | Values | Type | |-----------------------------|---------------------------------------------|----------|--------| | Advanced Physical Synthesis | ADVANCED_PHYSICAL_SYNTHESIS | ON , OFF | Global |

4.4. Netlist Optimizations and Physical Synthesis Revision History

The following revision history applies to this chapter:

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5. Area Optimization

This chapter describes techniques for efficient use of device resources.

5.1. Resource Utilization Information

Determining device utilization provides useful information regardless of whether the design achieved a successful fit. If the compilation results in a no-fit error, resource utilization information helps to analyze the fitting problems in the design. If the fitting is successful, this information allows you to determine if design changes introduce fitting difficulties. Additionally, you can determine the impact of the resource utilization in the timing performance. The Compilation Report provides information about resource usage.

5.1.1. Flow Summary Report

The Flow Summary section of the compilation report indicates whether the design exceeds the available device resources, and reports resource utilization, including pins, memory bits, DSP blocks, and PLLs.

Figure 20. Flow Summary Report

The Fitter can spread logic throughout the device, which may lead to higher overall utilization. As the device fills up, the Fitter automatically searches for logic functions with common inputs to place in one ALM. The number of packed registers also

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increases. Therefore, a design that has high overall utilization might still have space for extra logic if the logic and registers can be packed together more tightly. In those cases, you can benefit by a report that provides more details.

5.1.2. Fitter Reports

The Fitter generates detailed reports for each stage of place and route. The Fitter section of the Compilation Report includes reports detailing the Fitter's use of device resources.

The Fitter Resource Usage Summary report summarizes how the Fitter utilizes logic resources of the target device when implementing your design, such as the number of bits in each type of memory block. This report also summarizes the usage of global clocks, PLLs, DSP blocks, and other device-specific resources.

Related Information

Quartus Prime Pro Edition User Guide: Design Compilation

5.1.2.1. Route Stage Reports

The Route stage reports ( Compilation Report ➤ Fitter ➤ Route Stage ) provide details about the various types of device resources that the Fitter allocates during routing. These details include reports on the following types of routing information:

The type, number, and overall use percentage of each device resource
Nets with the highest wire count
Delay chain summary information
Global wire utilization information
The top congested hierarchies and nets

Figure 21. Example Routing Usage Summary

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5.1.2.1.1. Nets with Highest Wire Count Report

The Nets with Highest Wire Count report ( Route Stage ➤ Nets with Highest Wire Count ) lists in descending order the nets that use the highest number of wires in the design and their fan-out count. You can use this report to identify and evaluate the high fan-out nets in the design. The Nets with Highest Wire Count report generates whether or not the design routes successfully.

Figure 22. Example Nets with Highest Wire Count Report

5.1.2.1.2. Delay Chain Summary Report

A delay chain is a series of LCELL or EXP primitives or I/O delay chains in the I/O block that you use to create an intentional delay or asynchronous pulse. A delay chain is generally unreliable because the best-case delay of an LCELL or EXP cannot be guaranteed. This delay chain configuration also increases the sensitivity of the design to operating conditions.

The Delay Chain Summary report ( Route Stage ➤ Delay Chain Summary ) summarizes information about the delay chains in your design. This report lists the node name and pin type in the chain. Delay chains appear in terms of their delay chain fan-out setting and actual delay in ps.

Figure 23. Example Delay Chain Summary Report (Truncated)

5.1.2.1.3. Top Congested Hierarchies and Nets Reports

If your design fails to route, you can use the Top Congested Hierarchies and Top Congested Nets reports to determine the most congested hierarchies and nets in the design. View these reports under Compilation Report ➤ Fitter ➤ Route Stage .

Use context menu commands to locate directly to the reported hierarchies and nets in the Text Editor, Assignment Editor, Pin Planner, Chip Planner, and other editors. Optimize your design in the reported areas to reduce the congestion and successfully route the design.

Figure 24. Example Top Congested Hierarchies Report (Truncated)

Figure 25. Example Top Congested Nets Report (Truncated)

5.1.2.1.4. Global Route Reports

A global routing congested region is an area of the FPGA where short wire usage in a particular direction exceeds the capacity of that region. A congested net is a net that passes through a global routing congested region. The Global Route reports ( Compilation Report ➤ Fitter ➤ Route Stage ➤ Global Route ) show information about the congested nets in your design.

Figure 26. Example of the Global Router Congestion Hotspot Summary Report

For example, the Global Router Congestion Hotspot Summary report shows congested net hotspots in your design organized by hierarchical node name. If the congested area is small, the Router may be successful in detouring around overused regions. However, if the congested area is large, routing may be unsuccessful. The exact threshold where the Fitter cannot route the design varies greatly by design characteristics.

Use the Global Router Congestion Hotspot Summary report to identify parts of your RTL code that are associated with routing congestion. The Global Router Wire Utilization Map shows the threshold and size of the largest congested region if the size of adjacent congested regions is below a threshold.

5.1.3. Design Assistant Recommendations

You can run the Design Assistant at various stages throughout the compilation process. Correcting Design Assistant rule violations improves the reliability, timing performance, and logic utilization of the design.

5.1.4. Analysis and Synthesis Reports

For designs synthesized with the Quartus Prime synthesis engine, you can see reports describing optimizations that occurred during compilation.

For example, in the Analysis & Synthesis section, Optimization Results folder, you can find a list of registers removed during synthesis. With this report you can estimate resource utilization for partial designs so you make sure that registers were not removed due to missing connections with other parts of the design.

Related Information

Quartus Prime Pro Edition User Guide: Design Recommendations

5.1.5. Compilation Messages

If the reports show resource usage lower than 100%, but the design does not fit, either resources are insufficient or the design contains invalid assignments. In either case, the Compiler generates a message in the Processing tab of the Messages window describing the problem. As resource utilization approaches 100%, the design becomes increasingly difficult to fit.

If the Fitter finishes unsuccessfully and runs much faster than on similar designs, a resource might be over-utilized, there might be an illegal location or timing assignment that is difficult or impossible to resolve.

If the Quartus Prime software takes too long to run when compared to similar designs, the Compiler may not be able to find a valid placement or route solution. In the Compilation Report, look for errors and warnings that indicate these types of problems.

Related Information

Viewing Messages

5.1.6. Chip Planner Visualization

The Chip Planner can help you find areas of the device that have routing congestion for specific types of routing resources. If you find areas with very high congestion, analyze the cause of the congestion. Issues such as high fan-out nets not using global resources, an improperly chosen optimization goal (speed versus area), very restrictive floorplan assignments, or the coding style can cause routing congestion. After you identify the cause, modify the source or settings to reduce routing congestion.

Related Information

Viewing Routing Congestion in Chip Planner on page 173

5.2. Optimizing Resource Utilization

The following lists the stages after design analysis:

Optimize resource utilization-Ensure that you have already set the basic constraints
I/O timing optimization-Optimize I/O timing after you optimize resource utilization and your design fits in the desired target device
Register-to-register timing optimization

Related Information

Design Optimization Overview on page 7
Timing Closure and Optimization on page 67

5.2.1. Resource Utilization Issues Overview

Resource utilization issues can be divided into three categories:

Issues relating to I/O pin utilization or placement , including dedicated I/O blocks such as PLLs or LVDS transceivers.
Issues relating to logic utilization or placement , including logic cells containing registers and LUTs as well as dedicated logic, such as memory blocks and DSP blocks.
Issues relating to routing .

5.2.2. I/O Pin Utilization or Placement

Resolve I/O resource problems with these guidelines.

5.2.2.1. Guideline: Modify Pin Assignments or Choose a Larger Package

If a design that has pin assignments fails to fit, compile the design without the pin assignments to determine whether a fit is possible for the design in the specified device and package. You can use this approach if an Quartus Prime error message indicates fitting problems due to pin assignments.

If the design fits when all pin assignments are ignored or when several pin assignments are ignored or moved, you might have to modify the pin assignments for the design or select a larger package.

If the design fails to fit because insufficient I/Os pins are available, a larger device package (which can be the same device density) that has more available user I/O pins can result in a successful fit.

Related Information

Quartus Prime Pro Edition User Guide: Design Constraints

5.2.3. Logic Utilization or Placement

Resolve logic resource problems, including logic cells containing registers and LUTs, as well as dedicated logic such as memory blocks and DSP blocks, with these guidelines.

5.2.3.1. Guideline: Optimize Source Code

If your design does not fit because of logic utilization, then evaluate and modify the design at the source. The Design Assistant reports can help you to identify source code optimizations.

You can often improve logic significantly by making design-specific changes to your source code. This is typically the most effective technique for improving the quality of your results.

If your design does not fit into available logic elements (LEs) or ALMs, but you have unused memory or DSP blocks, check if you have code blocks in your design that describe memory or DSP functions that are not being inferred and placed in dedicated logic. You might be able to modify your source code to allow these functions to be placed into dedicated memory or DSP resources in the target device.

Ensure that your state machines are recognized as state machine logic and optimized appropriately in your synthesis tool. State machines that are recognized are generally optimized better than if the synthesis tool treats them as generic logic. In the Quartus Prime software, you can check for the State Machine report under Analysis & Synthesis in the Compilation Report. This report provides details, including the state encoding for each state machine that was recognized during compilation. If your state machine is not being recognized, you might have to change your source code to enable it to be recognized.

Related Information

AN 584: Timing Closure Methodology for Advanced FPGA Designs

Quartus Prime Pro Edition User Guide: Design Recommendations

5.2.3.2. Guideline: Optimize Synthesis for Area, Not Speed

If the Fitter cannot resolve a design due to limitations in logic resources, resynthesize the design to improve the area utilization.

First, ensure that the device and timing constraints are set correctly in the synthesis tool. Particularly when area utilization of the design is a concern, ensure that you do not over-constrain the timing requirements for the design. Synthesis tools try to meet the specified requirements, which can result in higher device resource usage if the constraints are too aggressive.

If resource utilization is an important concern, you can optimize for area instead of speed.

If you are using Quartus Prime synthesis, click Assignments ➤ Settings ➤ Compiler Settings ➤ Advanced Settings (Synthesis) and select Balanced or Area for the Optimization Technique .
The Aggressive Area Optimization Mode optimizes for area at the cost of performance.
If you want to reduce area for specific modules in the design using the Area or Speed setting while leaving the default Optimization Technique setting at Balanced , use the Assignment Editor.
In some synthesis tools, not specifying an fMAX requirement can result in less resource utilization.

Optimizing for area or speed can affect the register-to-register timing performance.

In the Quartus Prime software, the Balanced setting typically produces utilization results that are very similar to those produced by the Area setting, with better performance results. The Area setting can give better results in some cases.

The Quartus Prime software provides additional attributes and options that can help improve the quality of the synthesis results.

Related Information

Optimization Mode

5.2.3.3. Guideline: Restructure Multiplexers

Multiplexers form a large portion of the logic utilization in many FPGA designs. By optimizing your multiplexed logic, you can achieve a more efficient implementation in your Altera device.

Related Information

Restructure Multiplexers logic option

For more information about the Restructure Multiplexers option

Note:

5.2.3.4. Guideline: Perform WYSIWYG Primitive Resynthesis with Balanced or Area Setting

The Perform WYSIWYG Primitive Resynthesis logic option specifies whether to perform WYSIWYG primitive resynthesis during synthesis. This option uses the setting specified in the Optimization Technique logic option. The Perform WYSIWYG Primitive Resynthesis logic option is useful for resynthesizing some or all of the WYSIWYG primitives in your design for better area or performance. However, WYSIWYG primitive resynthesis can be done only when you use third-party synthesis tools.

Note: The Balanced setting typically produces utilization results that are very similar to the Area setting with better performance results. The Area setting can give better results in some cases. Performing WYSIWYG resynthesis for area in this way typically reduces register-to-register timing performance.

Related Information

Perform WYSIWYG Primitive Resynthesis logic option For information about this logic option

5.2.3.5. Guideline: Use Register Packing

The Auto Packed Registers option implements the functions of two elements into one logic element by combining the register of one element, in which only the register is used with the LUT of another element, in which only the LUT is used.

Remember:

DSP register packing is not always possible. For a list of conditions that prevent register packing, refer to the "Fixed Point DSP Register Packing Summary and Fixed Point DSP Register Packing Details" section of Fitter Feature Specific Report in the Quartus Prime Pro Edition help.

DSP Register Packing Entity Assignment

In addition, you can control DSP register packing at the entity level by specifying the DSP Register Packing entity assignment in the Assignment Editor, or with the corresponding DSP_REGISTER_PACKING assignment in the project .qsf . DSP Register Packing specifies how aggressively the Fitter optimizes DSP performance by automatically packing registers into the internal registers of the specified DSP blocks. With the default Balanced setting, the Fitter packs registers into the specified DSP blocks that improve timing. With Always enabled, the Fitter aggressively pack registers into the specified DSP blocks, unless your constraints or other legality restrictions prevent packing. With Disable enabled, registers do not pack into the specified DSP blocks. The following is the equivalent .qsf assignment:

set_instance_assignment -name DSP_REGISTER_PACKING -to \ <to> -entity <name> <value>

DSP_REGISTER_PACKING_LEVEL Entity Assignment

In addition, you can enter the DSP_REGISTER_PACKING_LEVEL entity assignment directly in the project .qsf to specify the maximum number of register stages desired for a specific DSP. DSP_REGISTER_PACKING_LEVEL specifies the maximum number of registers that you want to pack in the specified DSP instance. The following are DSP_REGISTER_PACKING_LEVEL setting values:

0 -equivalent to disabling DSP register packing operation of the DSP.
1 -the Fitter tries to pack one layer of registers from the DSP's input side.
2 -the Fitter tries to add an additional layer of registers from the DSP's output side.
3 or 4 -the Fitter tries to add one or two layers of the pipeline registers from the input side.

If the Compiler cannot implement the packing level you specify, the Compiler issues a warning message indicating that the assignment is not respected. the Fixed Point DSP Register Packing Details report also describes the reasons the packing level cannot be met. The following is the equivalent .qsf assignment:

set_instance_assignment -name DSP_REGISTER_PACKING_LEVEL -to \ <to> -entity <entity name> <value>

Fixed Point DSP Register Packing Summary Report and Fixed Point DSP Register Packing Details Report

After running the Compiler's Plan stage, the Compilation Report includes the Fixed Point DSP Register Packing Summary report, and the Fixed Point DSP Register Packing Details report. These reports provide information about the use of DSP blocks in your design, including DSP register packing data. The summary report lists how many DSP blocks are fully registered, partially registered, or unregistered.

The Fixed Point DSP Register Packing Details report also indicates the names of the registers packed into register banks, the register usage (fully registered, partially registered, or unregistered), and the reasons preventing any register packing. Viewing these register name details in the report allows you to readily identify registers for packing assignments.

Related Information

DSP_REGISTER_PACKING Assignment, Quartus Prime Pro Edition Settings File Reference Manual

For complete command syntax and options

DSP_REGISTER_PACKING_LEVEL Assignment, Quartus Prime Pro Edition Settings File Reference Manual

For complete command syntax and options

Fixed Point DSP Register Packing Summary and Fixed Point DSP Register Packing Details, Quartus Prime Pro Edition Help

For details about reason preventing register packing

5.2.3.6. Guideline: Remove Fitter Constraints

A design with conflicting constraints or constraints that are difficult to meet may not fit in the targeted device. For example, a design might fail to fit if the location or Logic Lock assignments are too strict and not enough routing resources are available on the device.

To resolve routing congestion caused by restrictive location constraints or Logic Lock region assignments, use the Routing Congestion task in the Chip Planner to locate routing problems in the floorplan, then remove any internal location or Logic Lock region assignments in that area. If your design still does not fit, the design is overconstrained. To correct the problem, remove all location and Logic Lock assignments and run successive compilations, incrementally constraining the design before each compilation. You can delete specific location assignments in the Assignment Editor or the Chip Planner. To remove Logic Lock assignments in the Chip Planner, in the Logic Lock Regions Window, or on the Assignments menu, click Remove Assignments. Turn on the assignment categories you want to remove from the design in the Available assignment categories list.

Related Information

Analyzing and Optimizing the Design Floorplan on page 164

5.2.3.7. Guideline: Flatten the Hierarchy During Synthesis

Synthesis tools typically provide the option of preserving hierarchical boundaries, which can be useful for verification or other purposes. However, the Quartus Prime software optimizes across hierarchical boundaries so as to perform the most logic minimization, which can reduce area in a design with no design partitions.

5.2.3.8. Guideline: Re-target Memory Blocks

If the Fitter cannot resolve a design due to memory resource limitations, the design may require a type of memory that the device does not have.

For memory blocks created with the Parameter Editor, edit the RAM block type to target a new memory block size.

The Compiler can also infer ROM and RAM memory blocks from the HDL code, and the synthesis engine can place large shift registers into memory blocks by inferring the Shift register (RAM-based) IP core. When you turn off this inference in the synthesis tool, the synthesis engine places the memory or shift registers in logic instead of memory blocks. Also, turning off this inference prevents registers from being moved into RAM, improving timing performance,

Depending on the synthesis tool, you can also set the RAM block type for inferred memory blocks. In Quartus Prime synthesis, set the ramstyle attribute to the desired memory type for the inferred RAM blocks. Alternatively, set the option to logic to implement the memory block in standard logic instead of a memory block.

Review the Resource Utilization by Entity report in the report file to determine whether there is an unusually high register count in any of the modules corresponding with an unexpectedly low RAM block count. Some coding styles prevent the Quartus Prime software from inferring RAM blocks from the source code because of the blocks' architectural implementation, forcing the software to implement the logic in flip-flops.

For example, an asynchronous reset on a register bank might make the register bank incompatible with the RAM blocks in the device architecture, so Compiler implements the register bank in flip-flops. It is often possible to move a large register bank into RAM by slight modification of associated logic.

Using the appropriate memory can also help reduce resource use. For example, a shallow but wider memory may be more suitable for MLABs, rather than for M20K memory blocks.

Related Information

Quartus Prime Pro Edition User Guide: Design Recommendations
Agilex 7 Embedded Memory User Guide
Stratix 10 Embedded Memory User Guide
Arria 10 Embedded Memory User Guide

5.2.3.9. Guideline: Use Physical Synthesis Options to Reduce Area

The physical synthesis options available at Assignments ➤ Settings ➤ Compiler Settings ➤ Advanced Settings (Fitter) help you decrease resource usage. When you enable physical synthesis, the Quartus Prime software makes placement-specific changes to the netlist that reduce resource utilization for a specific Altera device.

Note:

Physical synthesis increases compilation time. To reduce the impact on compilation time, you can apply physical synthesis options to specific instances.

Related Information

Advanced Fitter Settings Dialog Box

5.2.3.10. Guideline: Retarget or Balance DSP Blocks

A design might not fit because it requires more DSP blocks than the target FPGA device has available.

You can implement all DSP block functions with logic cells, so you can retarget some of the DSP blocks to logic to obtain a fit.

If the DSP function was created with the parameter editor, open the parameter editor and edit the function so it targets logic cells instead of DSP blocks. The Quartus Prime software uses the DEDICATED_MULTIPLIER_CIRCUITRY IP core parameter to control the implementation.

DSP blocks also can be inferred from your HDL code for multipliers, multiply-adders, and multiply-accumulators. You can turn off this inference in your synthesis tool. When you are using Quartus Prime synthesis, you can disable inference by turning off the Auto DSP Block Replacement logic option for your entire project. Click Assignments ➤ Settings ➤ Compiler Settings ➤ Advanced Settings (Synthesis) . Turn off Auto DSP Block Replacement . Alternatively, you can disable the option for a specific block with the Assignment Editor.

The Quartus Prime software also offers the DSP Block Balancing logic option, which implements DSP block elements in logic cells or in different DSP block modes. The default Auto setting allows DSP block balancing to convert the DSP block slices automatically as appropriate to minimize the area and maximize the speed of the

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design. You can use other settings for a specific node or entity, or on a project-wide basis, to control how the Quartus Prime software converts DSP functions into logic cells and DSP blocks. Using any value other than Auto or Off overrides the DEDICATED_MULTIPLIER_CIRCUITRY parameter used in IP core variations.

For designs with large number of low-precision arithmetic operations, such as additions and multiplications, you can enable fractal synthesis optimizations. Fractal synthesis optimizations are useful for high-throughput, arithmetic-intensive designs that exceed all available DSP resources. These optimizations are beneficial in designs with large numbers of low-precision arithmetic operations, such as additions and multiplications.

Related Information

Fractal Synthesis Optimizations, Quartus Prime Pro Edition User Guide: Design Compilation

5.2.3.11. Guideline: Use a Larger Device

If a successful fit cannot be achieved because of a shortage of routing resources, you might require a larger device.

5.2.3.12. Guideline: Reduce Global Signal Congestion

For Stratix 10 and Arria 10 devices, you can refer to the generated Global Signal Visualization report to see global signal routing and clock sector utilization in an interactive heat map.

The presence of too many signals in a clock sector can result in congestion and routing failures in the Fitter's place stage. Use the Global Signal Visualization Report to debug global signal routing congestion and global signal placement and routing failures.

The interactive heat map shows the number of signals in use for a given clock sector. If these global signals are clocks, use clock region assignments to move clocks away from the affected clock sectors.

5.2.3.13. Guideline: Report Pipelining Information

Pipelining the design can be useful for providing resources for retiming and improving performance. However, excessive pipelining can unnecessarily consume area. Use the report_pipeline function to identify areas in the design with excess pipelining.

Related Information

Quartus Prime Pro Edition User Guide: Design Optimization

5.2.4. Routing

Resolve routing resource problems with these guidelines.

5.2.4.1. Guideline: Set Auto Packed Registers to Sparse or Sparse Auto

The Auto Packed Registers option reduces LE or ALM count in a design. You can set this option by clicking Assignment ➤ Settings ➤ Compiler Settings ➤ Advanced Settings (Fitter) .

Related Information

Auto Packed Registers logic option

5.2.4.2. Guideline: Set Fitter Aggressive Routability Optimizations to Always

The Fitter Aggressive Routability Optimization option is useful if your design does not fit due to excessive routing wire utilization.

If there is a significant imbalance between placement and routing time (during the first fitting attempt), it might be because of high wire utilization. Turning on the Fitter Aggressive Routability Optimizations option can reduce your compilation time.

On average, this option can save up to 6% wire utilization, but can also reduce performance by up to 4%, depending on the device.

Related Information

Fitter Aggressive Routability Optimizations logic option

5.2.4.3. Guideline: Increase Router Effort Multiplier

The Router Effort Multiplier controls how quickly the router tries to find a valid solution. The default value is 1.0 and legal values must be greater than 0.

Numbers higher than 1 help designs that are difficult to route by increasing the routing effort.
Numbers closer to 0 (for example, 0.1) can reduce router runtime, but usually reduce routing quality slightly.

Experimental evidence shows that a multiplier of 3.0 reduces overall wire usage by approximately 2%. Using a Router Effort Multiplier higher than the default value can benefit designs with complex datapaths with more than five levels of logic. However, congestion in a design is primarily due to placement, and increasing the Router Effort Multiplier does not necessarily reduce congestion.

Any Router Effort Multiplier value greater than 4 only increases by 10% for every additional 1. For example, a value of 10 is actually 4.6.

Note:

5.2.4.4. Guideline: Remove Fitter Constraints

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and run successive compilations, incrementally constraining the design before each compilation. You can delete specific location assignments in the Assignment Editor or the Chip Planner. To remove Logic Lock assignments in the Chip Planner, in the Logic Lock Regions Window, or on the Assignments menu, click Remove Assignments. Turn on the assignment categories you want to remove from the design in the Available assignment categories list.

Related Information

Analyzing and Optimizing the Design Floorplan on page 164

5.2.4.5. Guideline: Optimize Synthesis for Routability

You can specify Compiler optimization modes that optimize for routability over speed.

If resource utilization is an important concern, you can optimize for routability rather than speed.

The High-Placement Routability Effort , High Packing Routability Effort , and Optimize Netlist for Routability Optimization modes apply optimizations that improve routability of the design.

The Quartus Prime software provides additional attributes and options that can help improve the quality of your synthesis results.

Related Information

Optimization Mode

5.2.4.6. Guideline: Optimize Source Code

If your design does not fit because of routing problems and the methods described in the preceding sections do not sufficiently improve the routability of the design, you can modify the design at the source to achieve the desired results.

You can often improve results significantly by making design-specific changes to your source code, such as duplicating logic or changing the connections between blocks that require significant routing resources.

You can use the Design Assistant to help you identify areas in the design that can benefit from optimization. For example, the following Design Assistant rules identify registers in the design with high tension span, for which register duplication simplifies place and route.

You can also view the Global Router Wire Utilization Map report to identify instances and nets that utilize many global wire resources.

Related Information

Design Assistant Rules List
Design Assistant Design Rule Checking, Quartus Prime Pro Edition User Guide: Design Recommendations
Global Router Wire Visualization Map, Quartus Prime Pro Edition User Guide: Design Recommendations

5.2.4.7. Guideline: Use a Larger Device

If a successful fit cannot be achieved because of a shortage of routing resources, you might require a larger device.

5.3. Scripting Support

You can run procedures and assign settings described in this chapter in a Tcl script. You can also run procedures at a command prompt. For detailed information about scripting command options, refer to the Quartus Prime command-line and Tcl API Help browser.

To run the Help browser, type the following command at the command prompt:

quartus_sh --qhelp

You can specify many of the options described in this section either in an instance, or at a global level, or both.

Use the following Tcl command to make a global assignment:
Use the following Tcl command to make an instance assignment:

set_global_assignment -name <QSF variable name> <value>

set_instance_assignment -name <QSF variable name> <value> -to <instance name>

If the < value > field includes spaces (for example, 'Standard Fit'), you must enclose the value in straight double quotation marks.

Related Information

Quartus Prime Pro Edition Settings File Reference Manual For information about all settings and constraints in the Quartus Prime software.
Quartus Prime Pro Edition User Guide: Scripting

5.3.1. Initial Compilation Settings

Use the Quartus Prime Settings File ( .qsf ) variable name in the Tcl assignment to make the setting along with the appropriate value. The Type column indicates whether the setting is supported as a global setting, an instance setting, or both.

Table 12. Advanced Compilation Settings

| Setting Name | .qsf File Variable Name | Values | Type | |----------------------------------|----------------------------------|--------------------------------|--------| | Placement Effort Multiplier | PLACEMENT_EFFORT_MULTIPLIER | Any positive, non-zero value | Global | | Router Effort Multiplier | ROUTER_EFFORT_MULTIPLIER | Any positive, non-zero value | Global | | Router Timing Optimization level | ROUTER_TIMING_OPTIMIZATION_LEVEL | NORMAL , MINIMUM , MAXIMUM | Global | | Final Placement Optimization | FINAL_PLACEMENT_OPTIMIZATION | ALWAYS , AUTOMATICALLY , NEVER | Global |

Note:

5.3.2. Resource Utilization Optimization Techniques

This table lists QSF assignments and applicable values for Resource Utilization Optimization settings:

Table 13. Resource Utilization Optimization Settings

| Setting Name | .qsf File Variable Name | Values | Type | |------------------------------------------------|-------------------------------------|---------------------------------------------------------------------------------|------------------| | Auto Packed Registers | QII_AUTO_PACKED_REGISTERS | AUTO, OFF, NORMAL, MINIMIZE AREA, MINIMIZE AREA WITH CHAINS,SPARSE, SPARSE AUTO | Global, Instance | | Perform WYSIWYG Primitive Resynthesis | ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP | ON, OFF | Global, Instance | | Optimization Technique | OPTIMIZATION_TECHNIQUE | AREA, SPEED, BALANCED | Global, Instance | | Speed Optimization Technique for Clock Domains | SYNTH_CRITICAL_CLOCK | ON, OFF | Instance | | State Machine Encoding | STATE_MACHINE_PROCESSING | AUTO, ONE-HOT, GRAY, JOHNSON, MINIMAL BITS, ONE-HOT, SEQUENTIAL, USER-ENCODE | Global, Instance | | Auto RAM Replacement | AUTO_RAM_RECOGNITION | ON, OFF | Global, Instance | | Auto ROM Replacement | AUTO_ROM_RECOGNITION | ON, OFF | Global, Instance | | Auto Shift Register Replacement | AUTO_SHIFT_REGISTER_RECOGNITION | ON, OFF | Global, Instance | | Auto Block Replacement | AUTO_DSP_RECOGNITION | ON, OFF | Global, Instance | | Number of Processors for Parallel Compilation | NUM_PARALLEL_PROCESSORS | Integer between 1 and 16 inclusive, or ALL | Global |

5.4. Area Optimization Revision History

The following revision history applies to this chapter:

| Document Version | Quartus Prime Version | Changes | |--------------------|-------------------------|------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | 2022.01.07 | 21.4 | • Corrected syntax error in Scripting Support topic. • Added link to Fitter Reports topic. • Added new Design Assistant Recommendations topic. • Revised Compilation Messages topic. • Added Chip Planner Visualization topic. • Added reference to Design Assistant to Guideline: Optimize Source Code topic. • Revised Guideline: Optimize Synthesis for Area, Not Speed topic to mention Aggressive Area Optimization Mode. • Revised Guideline: Optimize Synthesis for Area, Not Speed topic to mention Aggressive Area Optimization Mode and remove Speed Optimization Technique for Clock Domains reference. • Revised Guideline: Retarget Memory Blocks topic to mention use of appropriate embedded memory IP. • Revised Guideline: Retarget or Balance DSP Blocks topic to mention use of fractal synthesis. • Added Guideline: Report Pipelining Information topic. • Added reference to Global Router Wire Utilization Map report to Guideline: Optimize Source Code topic. • Removed references to obsolete Timing Optimization Advisor. | | 2018.10.18 | 18.1 | • Corrected broken link to Optimization Modes Help topic. | | 2018.09.24 | 18.1 | • Divided topic: Resource Utilization into topics: Resource Utilization Information , Flow Summary Report , Fitter Reports , Analysis and Synthesis Reports , and Compilation Messages . | | 2018.07.03 | 18 | Fixed typo and added links in topic Guideline: Retarget Memory Blocks . | | 2017.05.08 | 17 | • Removed information about deprecated Integrated Synthesis • Revised topics: Resolving Resource Utilization Issues , Guideline: Optimize Synthesis for Area, Not Speed | | 2016.10.31 | 16.1 | • Implemented Intel rebranding. | | 2016.05.02 | 16 | • Removed information about deprecated physical synthesis options. | | 2015.11.02 | 15.1 | Changed instances of Quartus II to Intel Quartus Prime . | | 2014.12.15 | 14.1 | Updated location of Fitter Settings, Analysis & Synthesis Settings, and Physical Synthesis Optimizations to Compiler Settings. | | June 2014 | 14 | • Removed Cyclone III and Stratix III devices references. • Removed Macrocell-Based CPLDs related information. • Updated template. | | May 2013 | 13 | Initial release. |

6. Timing Closure and Optimization

This chapter describes techniques to improve timing performance when designing for Altera FPGA devices. The application of techniques varies between designs and target FPGA device. Applying each technique does not improve results in all cases.

The default settings and options in the Quartus Prime software provide the most balanced trade-off between compilation time, resource utilization, and timing performance. You can then adjust these settings to determine whether a different mix of settings might provide better results for your design.

6.1. Optimize Multi Corner Timing

Process variations and changes in operating conditions can result in path delays that are significantly smaller than those in the slow corner timing model. As a consequence, the design can present hold time violations on those paths, and in rare cases, additional setup time violations.

In addition, designs targeting newer device families (with smaller process geometry) do not always present the slowest circuit performance at the highest operating temperature. The temperature at which the circuit is slowest depends on the selected device, the design, and the compilation results. The Quartus Prime software manages this new dependency by providing newer device families with three different timing corners-Slow 85°C corner, Slow 0°C corner, and Fast 0°C corner. For other device families, two timing corners are available-Fast 0°C and Slow 85°C corner.

The Optimize multi-corner timing option directs the Fitter to meet timing requirements at all process corners and operating conditions. The resulting design implementation is more robust across process, temperature, and voltage variations. This option is on by default, and increases compilation time by approximately 10%.

When this option is off, the Fitter optimizes designs considering only slow-corner delays from the slow-corner timing model (slowest manufactured device for a given speed grade, operating in low-voltage conditions).

6.2. Optimize Critical Paths

Critical paths are timing paths in your design that have a negative slack and may require optimization. These timing paths can span from device I/Os to internal registers, registers to registers, or from registers to device I/Os.

The slack of a path determines its criticality; slack appears in the timing analysis report, which you can generate using the Timing Analyzer.

Design analysis for timing closure is a fundamental requirement for optimal performance in highly complex designs. The analytical capability of the Chip Planner helps you close timing on complex designs.

*Other names and brands may be claimed as the property of others.

Related Information

Critical Path Delay Reduction Trade-Offs on page 12

6.2.1. Viewing Critical Paths

Viewing critical paths in the Chip Planner shows why a specific path is failing. You can see if any modification in the placement can reduce the negative slack. To display paths in the floorplan, perform a timing analysis and display results on the Timing Analyzer.

6.3. Optimize Critical Chains

Critical chains are design paths that limit further register retiming optimization. You can use the Hyper-Aware design flow to shorten design cycles and optimize critical chain performance for Stratix 10 and Agilex FPGA portfolio devices. The Hyper-Aware design flow maximizes use of Hyper-Registers by combining automated register retiming with implementation of targeted timing closure recommendations (Fast Forward compilation). This sum of techniques drive the highest performance for Hyperflex ® architecture designs.

A critical chain reports the design paths that limit further register retiming optimization. The Quartus Prime Pro Edition software provides the Hyper-Retimer critical chain reports to help you improve design performance. You can focus on higher level optimization, because the Hyper-Retimer uses Hyper-Registers to evenly balance slacks on all the registers in a critical chain.

Related Information

Hyperflex Architecture High-Performance Design Handbook

6.3.1. Viewing Critical Chains

Looking at the critical chain shows the exact logic that limits retiming operations in your design. For example, you can see if the retiming is limited by your RTL code, or by the constraints you applied on the design. Quartus Prime Pro Edition reports one critical chain per clock domain and clock domain crossing.

The critical chain is available at two different stages in the Hyper Aware Design Flow:

In the Retiming Limit Details Report-this report for the retiming stage in the Hyper Aware Design Flow, and is enabled by default.
In the Fast Forward Compilation Report-Click Fast Forward Timing Closure Recommendations on the Compilation Dashboard to run..
You can also graphically visualize the critical chains in the Technology Map Viewer.

Related Information

Hyperflex Architecture High-Performance Design Handbook
Stratix 10 HyperFlex Design: Analyzing Critical Chains (OS10CRCHNS) Online Course

6.4. Design Evaluation for Timing Closure

As you move towards completion of your design, you can begin evaluating your design for timing closure. Follow the techniques in this section to evaluate whether your design is likely to close timing. If your design requires further steps for timing closure, you can use the analysis techniques in this section to determine whether RTL changes can help you to close timing.

6.4.1. Review Messages

After compiling your design, review the messages in each section of the compilation report. Most designs that fail timing start out with other problems that the Fitter reports as warning messages during compilation. Determine what causes a warning message, and whether to fix or ignore the warning.

After reviewing the warning messages, review the informational messages. Take note of anything unexpected, for example, unconnected ports, ignored constraints, missing files, or other unexpected conditions.

6.4.2. Evaluate Fitter Netlist Optimizations

You can specify options that direct the Fitter to perform optimizations to the design netlist. Specify global options, such as register packing, duplicating or deleting logic cells, or inverting signals by clicking Assignments ➤ Settings ➤ Compiler Settings ➤ Advanced Settings (Fitter) .

Figure 27. Netlist Optimizations Report

6.4.3. Evaluate Optimization Results

After checking what optimizations were done and how they improved performance, evaluate the runtime it took to get the extra performance. To reduce compilation time, review the physical synthesis and netlist optimizations over a couple of compilations, and edit the RTL to reflect the changes that physical synthesis performed. If a particular set of registers consistently get retimed, edit the RTL to retime the registers the same way. If the changes are made to match what the physical synthesis algorithms did, the physical synthesis options can be turned off to save compile time while getting the same type of performance improvement.

6.4.4. Evaluate Resource Usage

Evaluate the device resources that the design consumes, including global and nonglobal signal usage, routing utilization, and clustering difficulty. Determine whether you approach capacity for any type of resource that might limit performance.

6.4.4.1. Evaluate Global and Non-Global Usage

For Arria 10 and Cyclone 10 GX designs that contain many clocks, evaluate global and non-global signals to determine whether global resources are used effectively, and if not, consider making changes. After running the Fitter, refer to the Global and Other Fast Signals report to review data on these signals.

Note:

Stratix 10 and Cyclone 10 GX devices do not contain regional clocks, but use local routing.

The figure shows an example of inefficient use of a global clock.

Figure 28. Inefficient Use of a Global Clock in Arria 10 Design-Single Fan-Out from Global Clock

If you assign these resources to a Regional Clock, the Global Clock becomes available for another signal. You can ignore signals with an empty value in the Global Line Name column as the signal uses dedicated routing, and not a clock buffer. The NonGlobal High Fan-Out Signals report lists the highest fan-out nodes not routed on global signals. Reset and enable signals appear at the top of the list.

If there is routing congestion in the design, and there are high fan-out non-global nodes in the congested area, consider using global or regional signals to fan-out the nodes, or duplicate the high fan-out registers so that each of the duplicates can have fewer fan-outs. Use the Chip Planner to locate high fan-out nodes, to report routing congestion, and to determine whether the alternatives are viable.

6.4.4.2. Evaluate Routing Usage

Review routing usage reported in the Fitter Resource Usage Summary report.

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Figure 29. Fitter Resource Usage Summary Report

Average interconnect usage reports the average amount of interconnect that is used, out of what is available on the device. Peak interconnect usage reports the largest amount of interconnect used in the most congested areas.

Designs with an average value below 50% typically do not have any problems with routing. Designs with an average between 50-65% may have difficulty routing. Designs with an average over 65% typically have difficulty meeting timing unless the RTL tolerates a highly utilized chip. Peak values at or above 90% are likely to have problems with timing closure; a 100% peak value indicates that all routing in an area of the device has been used, so there is a high possibility of degradation in timing performance.

6.4.4.3. Evaluate Wires Added for Hold

During routing the Fitter may add wire between register paths to increase delay to meet hold time requirements. The Fitter reports how much routing delay was added in the Estimated Delay Added for Hold Timing report. Excessive additional wire can indicate an error with the constraint. The cause of such errors is typically incorrect multicycle transfers between multi-rate clocks, and between different clock networks.

Review the specific register paths in the Estimated Delay Added for Hold Timing report to determine whether the Fitter adds excessive wire to meet hold timing.

Figure 30. Estimated Delay Added for Hold Timing Report

An example of an incorrect constraint which can cause the router to add wire for hold requirements is when there is data transfer from 1x to 2x clocks. Assume the design intent is to allow two cycles per transfer. Data can arrive any time in the two destination clock cycles by adding a multicycle setup constraint as shown in the example:

set_multicycle_path -from 1x -to 2x -setup -end 2

The timing requirement is relaxed by one 2x clock cycle, as shown in the black line in the waveform in the figure.

Figure 31. Timing Requirement Relaxed Waveform

The default hold requirement, shown with the dashed blue line, can force the router to add wire to guarantee that data is delayed by one cycle. To correct the hold requirement, add a multicycle constraint with a hold option.

set_multicycle_path -from 1x -to 2x -setup -end 2 set_multicycle_path -from 1x -to 2x -hold -end 1

The orange dashed line in the figure above represents the hold relationship, and no extra wire is required to delay the data.

The router can also add wire for hold timing requirements when data transfers in the same clock domain, but between clock branches that use different buffering. Transferring between clock network types happens more often between the periphery and the core. The following figure shows data is coming into a device, a periphery clock drives the source register, and a global clock drives the destination register. A global clock buffer has larger insertion delay than a periphery clock buffer. The clock delay to the destination register is much larger than to the source register, hence extra delay is necessary on the data path to ensure that it meets its hold requirement.

Figure 32. Clock Delay

To identify cases where a path has different clock network types, review the path in the Timing Analyzer, and check nodes along the source and destination clock paths. Also, check the source and destination clock frequencies to see whether they are the

Note:

same, or multiples, and whether there are multicycle exceptions on the paths. Finally, ensure that all cross-domain paths that are false by intent have an associated false path exception.

If you suspect that routing is added to fix real hold problems, you can disable the Optimize hold timing advanced Fitter setting ( Assignments ➤ Settings ➤ Compiler Settings ➤ Advanced Settings (Fitter) ➤ Optimize hold timing ). Recompile the design with Optimize hold timing disabled, and then rerun timing analysis to identify and correct any paths that fail hold time requirements.

Disable the Optimize hold timing option only when debugging your design. Ensure to enable the option (default state) during normal compiles. Wire added for hold is a normal part of timing optimization during routing and is not always a problem.

6.4.5. Evaluate Other Reports and Adjust Settings Accordingly

6.4.5.1. Difficulty Packing Design

In the Fitter Resource Section, under the Resource Usage Summary , review the Difficulty Packing Design report. The Difficulty Packing Design report details the effort level (low, medium, or high) of the Fitter to fit the design into the device, partition, and Logic Lock region.

As the effort level of Difficulty Packing Design increases, timing closure gets harder. Going from medium to high can result in significant drop in performance or increase in compile time. Consider reducing logic to reduce packing difficulty.

6.4.5.2. Review Ignored Assignments

The Compilation Report includes details of any assignments that the Fitter ignores. The Fitter may ignore assignments if they refer to nodes names that change, but assignments are not updated accordingly. Make sure that the Fitter is not ignoring any valid assignments.

6.4.5.3. Review Non-Default Settings

The Synthesis and Fitter reports list all settings set to a non-default value during the compilation. Review the non-default settings to ensure benefit.

6.4.5.4. Review the Design Floorplan

Use the Chip Planner for reviewing placement. You can use the Chip Planner to locate hierarchical entities, using colors for each located entity in the floorplan. Look for logic that seems out of place, based on where you expect it to be

For example, logic that interfaces with I/Os should be close to the I/Os, and logic that interfaces with an IP or memory should be close to the IP or memory.

Figure 33. Floorplan with Color-Coded Entities

The following notes describe use of the visualization in Floorplan with Color-Coded Entities :

The green block is spread apart. Check to see if those paths are failing timing, and if so, what connects to that module that could affect placement.
The blue and aqua blocks are spread out and mixed together. Check if connections between the two modules contribute to this.
The pink logic at the bottom must interface with I/Os at the bottom edge. Check fan-in and fan-out of a highlighted module by using the buttons on the task bar. Look for signals that go a long way across the chip and see if they are contributing to timing failures.
Check global signal usage for signals that affect logic placement, and verify if the Fitter placed logic feeding a global buffer close to the buffer and away from related logic. Use settings like high fan-out on non-global resource to pull logic together.
Check for routing congestion. The Fitter spreads out logic in highly congested areas, making the design harder to route.

6.4.5.5. Adjust Placement Effort

You can increase the Assignments ➤ Settings ➤ Compiler Settings ➤ Advanced Settings (Fitter) ➤ Placement Effort Multiplier value to spend additional compilation time and effort in Place stage of the Fitter.

Adjust the multiplier after reviewing and optimizing other settings and RTL. Try an increased value, up to 4, and reset to default if performance or compile time does not improve.

6.4.5.6. Adjust Fitter Effort

Fitter Optimization mode settings allow you to specify whether the Compiler focuses optimization efforts for performance, resource utilization, power, or compile times.

By default, the Fitter Optimization mode is set to Balanced (Normal flow) mode, which reduces Fitter effort and compilation time as soon as timing requirements are met. You can optionally select another Optimization mode to target performance, area, routability, power, or compile time.

To increase Fitter effort further, you can also enable the Assignments ➤ Settings ➤ Compiler Settings ➤ Advanced Settings (Fitter) ➤ Fitter Effort option. The default Auto Fit setting reduces Fitter effort once timing requirements are met. Standard Fit (highest effort) setting uses maximum effort regardless of the design's requirements, leading to higher compilation time and more timing margin.

6.4.5.7. Review Timing Constraints

Ensure that you constrain all clocks with the correct frequency requirements.

To confirm the proper application of timing constraints, run the Design Assistant and then review and correct any timing constraint rule violations. In addition, you can review the Ignored Constraints report to locate any constraints assigned to invalid node names in the design. These invalid node names are most commonly caused by changes that you make in the design hierarchy that are not yet reflected in the constraint. Similarly, review the Report Unconstrained Paths report to locate unconstrained paths. Add constraints as necessary so that the Compiler can fully optimize the design.

6.4.6. Evaluate Clustering Difficulty

You can evaluate clustering difficulty to help reach timing closure. You can monitor clustering difficulty whenever you add logic and recompile. Use the clustering information to gauge how much timing closure difficulty is inherent in your design.

If your design is full but clustering difficulty is low or medium, your design itself, rather than clustering, is likely the main cause of congestion.
Conversely, congestion occurring after adding a small amount of logic to the design, can be due to clustering. If clustering difficulty is high, this contributes to congestion regardless of design size.

6.4.7. Revise and Recompile

Look for obvious problems that you can fix with minimal effort. To identify where the Compiler had trouble meeting timing, perform seed sweeping with about five compiles. Doing so shows consistently failing paths. Consider recoding or redesigning that part of the design.

To reach timing closure, a well written RTL can be more effective than changing your compilation settings. Seed sweeping can also be useful if the timing failure is very small, and the design has already been optimized for performance improvements and is close to final release. Additionally, seed sweeping can be used for evaluating changes to compilation settings. Compilation results vary due to the random nature of fitter algorithms. If a compilation setting change produces lower average performance, undo the change.

Sometimes, settings or constraints can cause more problems than they fix. When significant changes to the RTL or design architecture have been made, compile periodically with default settings and without Logic Lock regions, and re-evaluate paths that fail timing.

6.5. Timing Optimization

You can use the techniques and tools in this section to optimize timing when your design does not meet its timing requirements. Also, refer to the design recommendations in Optimizing for Timing Closure, Quartus Prime Pro Edition User Guide: Design Recommendations .

6.5.1. Correct Design Assistant Rule Violations

After running any stage of the Compiler, review the Design Assistant reports to analyze any design rule violations and view recommendations to correct failing paths. When enabled, the Quartus Prime Design Assistant automatically runs during compilation and reports any violations against a set of recommended design guidelines. Design Assistant rules include Timing Closure, Clocking, CDC, reset, and floorplanning.

You can customize the Design Assistant for your design characteristics and reporting requirements. Run Design Assistant in Compilation Flow mode to view the violations relevant for Compiler stages. Run in analysis mode from tools like the Timing Analyzer and Chip Planner to cross-probe from an individual rule violation to more information.

Follow these steps to enable and run Design Assistant and view results following compilation:

Click Assignments ➤ Settings ➤ Design Assistant Rules Settings .

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Figure 34. Design Assistant Rules Settings

To enable Design Assistant checking during compilation, turn on Enable Design Assistant execution during compilation .
To run Design Assistant during compilation, run one or more modules of the Compiler. Design Assistant reports results for each stage in the Compilation Report.
To view the results for each rule, click the rule in the Rules list. A description of the rule and design recommendations for correction appear.
For timing path-related rule violations, right-click the node or path, and then click Report Timing (Extra Info) or Report Path (Extra Info) . The Timing Analyzer loads and automatically displays the Report Timing or Report Path data related to the rule violation, allowing you to probe every aspect of the violation. Report Path can report timing even for paths that are cut.

Figure 35. Cross Probing From Design Assistant Rule Violations to Timing Analyzer

Related Information

Quartus Prime Pro Edition User Guide: Design Recommendations

6.5.2. Implement Fast Forward Timing Closure Recommendations

In traditional FPGA timing closure flows, the starting point for most design analysis is the critical path. Due to the nature of Hyperflex architecture and the availability of the Hyper Retimer, it is best to start you timing closure activities from the Retiming Limit Report. Provide the Hyper-Retimer as many optimization opportunities as possible, before having to look into more time intensive and potentially manual timing closure techniques.

Related Information

Hyperflex Architecture High-Performance Design Handbook

6.5.2.1. Retiming Limit Details Report

Use the Retiming Limit Details report to get specific information on what is currently limiting the Hyper Retimer from performing more optimizations.

The Retiming Limit Details report specifies:

Clock Transfer: Clock domain, or the clock domain transfer for which the critical chain applies
Limiting Reason: Design conditions which prevent further optimizations from happening.
Critical Chain Details: Timing paths associated with the timing restrictions.

6.5.2.1.1. Using the Retiming Limit Details Report

To access the Retiming Limit Details report:

In the Reports tab, double-click Retiming Limit Details under Fitter ➤ Retime Stage .
To locate the critical chain in the Technology Map Viewer, right-click any path and click Locate Critical Chain in Technology Map Viewer .

The Technology Map Viewer displays a schematic representation of the complete critical chain after place, route and register retiming.

Figure 36. Critical Chain in Technology Map Viewer

6.5.2.2. Fast Forward Timing Closure Recommendations

When running Fast Forward compilation, the Compiler removes signals from registers to allow mobility within the netlist for subsequent retiming. Fast Forward compilation generates design-specific timing closure recommendations, and predicts maximum performance with removal of all timing restrictions.

After you complete Fast Forward explorations, you can determine which recommendations to implement to provide the most benefit. Implement appropriate recommendations in your RTL, and recompile the design to achieve the performance levels that Fast Forward reports.

The Fast Forward Details Report provides the following information:

Table 14. Fast Forward Details Report Information

| Name | Description | |-----------------------------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | Step | Displays the various Fast Forward optimization steps, starting from the pre- optimization base compilation. • Each step comes with its associated critical chain. • Each step corresponds to a new optimization cumulative to the previous step. | | Fast Forward Optimization | Analyzed Summary of the optimizations necessary to implement each step. | | Estimated f MAX | Estimated f MAX performance after you implement the recommendations for this step in your design. This is cumulative, and step n represents the potential f MAX after implementing all previous steps. | | Optimization Analyzed | (cumulative) List of all the consecutive optimization steps applied. | | Recommendation for Critical Chain | Lists recommended changes to your designs. These recommendations are geared towards removing retiming limitations, and allowing register movement. |

6.5.2.2.1. Generating Fast Forward Timing Closure Recommendations

To generate Fast Forward timing closure recommendations:

On the Compilation Dashboard, click Fast Forward Timing Closure Recommendations .

The Compiler runs prerequisite synthesis or Fitter stages as needed, and generates timing closure recommendations in the Compilation Report.

View timing closure recommendations in the Compilation Report to evaluate design performance, and implement key RTL performance improvements.

The Quartus Prime Pro Edition software allows you to automate or refine Fast Forward analysis:

To run Fast Forward compilation during each full compilation, click Assignments ➤ Settings ➤ Compiler Settings ➤ HyperFlex , and turn on Run Fast Forward Timing Closure Recommendations during compilation .
To modify how Fast Forward compilation interprets specific I/O and block types, click Assignments ➤ Settings ➤ Compiler Settings ➤ HyperFlex Advanced Settings .

6.5.2.2.2. Implementing Fast Forward Recommendations

After implementing timing closure recommendations in your design, you can rerun the Retime stage to obtain the predictive performance gains.

You can continue exploring performance and implementing RTL changes to your code until you reach the desired performance target. Once you have completed all the modifications you want to do, continue your timing closure activities with the traditional techniques explained in this document.

For more information about implementing Fast Forward timing closure recommendations in your design, refer to the Implement Fast Forward Recommendations section of the Hyperflex Architecture High Performance Design Handbook

6.5.3. Review Timing Path Details

Reporting the timing paths and routing details can help uncover correctable timing and routing delays and other conditions that prevent retiming registers for higher performance.

6.5.3.1. Report Timing

The Timing Analyzer's Reports ➤ Timing Slack ➤ Report Timing… command allows you to specify settings to report the timing of any path or clock domain in the design. The equivalent scripting command is report_timing .

Figure 37. Report Timing Report

You can specify diverse options to customize the reporting. You can specify the Clocks and Targets that the report displays, the Analysis Type to run, whether to display Extra Info in the report, and the Output options for the report. For example, you can increase the number of paths to report, add a Target filter , and add a From Clock .

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Figure 38. Report Timing Dialog Box (Top Section)

Figure 39. Report Timing Dialog Box (Bottom Section)

Table 15. Report Timing Settings

| Option | Description | |------------------------------------------|-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | Clocks | From Clock and To Clock filter paths in the report to show only the launching or latching clocks you specify. | | Targets | Specifies the target node for From Clock and To Clock to report paths with only those endpoints. Specify an I/O or register name or I/O port for this option. The field also supports wildcard characters. For example, to report only paths within a specific hierarchy: report_timing -from |egress:egress_inst| \ -to |egress:egress_inst| -(other options) When the From , To , or Through boxes are empty, the Timing Analyzer assumes all possible | | Analysis type | The Analysis type options are Setup , Hold , Recovery , or Removal . The Timing Analyzer reports the results for the type of analysis you select. | | Paths | Specifies the number of paths to display by endpoint and slack level. The default value for Report number of paths is 10, otherwise, the report can be very long. Enable Pairs only to list only one path for each pair of source and destination. Limit further with Maximum number of paths per endpoints . You can also filter paths by entering a value in the Maximum slack limit field. | | Extra Info | Provides additional data that is relevant for diagnosing timing failure root cause, such as setup slack breakdown, and unexpected routing detours caused by congestion and hold time fix-up. Specify whether to include None , Basic , or All extra information in the report. The Extra Info tab data can help you identify potential, unnecessary routing detours, as well as placement or circuit issues that restrict the path f MAX performance. Refer to Setup Slack Breakdown On the Extra Info Tab on page 83. • All -report includes Extra Info tab that reports extra information for source timing endpoints that pass through the unregistered output of a RAM or DSP block, or for destination timing endpoints that pass through the unregistered input of a DSP block. The Data Path tab includes Estimated Delay Added for Hold and Route Stage Congestion Impact data. • Basic -report includes the Extra Info tab but no extra information on the Data Path tab. • None -report includes no Extra Info tab or other extra information on the Data Path tab. | | Output | Specify the path types the analysis includes in output for Detail level : • Summary -level includes basic summary reports. Review the Clock Skew column in the Summary report. If the skew is less than +/-150ps, the clock tree is well balanced between source and destination. • Path only -displays all the detailed information, except the Data Path tab displays the clock tree as one line item. • Path and Clock -displays the same as Path only with respect to the clock. • Full path -when higher clock skew is present, enable the Full path option. This option breaks the clock tree into greater detail, showing every cell, including the input buffer, PLL, global buffer (called CLKCTRL_ ), and any logic. Review this data to determine the cause of clock skew in your design. Use the Full path option for I/O analysis because only the source clock or destination clock is inside the FPGA, and therefore the delay is a critical factor to meet timing. | | Show routing | Shows routing data in the report. | | Split the report by operating conditions | For the operating condition timing corners, subdivides the data by each operating condition. | | Report panel name | Specifies the name of the report panel. You can optionally enable File name to write the information to a file. If you append .htm or .html as a suffix, the Timing Analyzer produces the report as HTML. If you enable File name , you can Overwrite or Append the file with latest data. | | Tcl command | Displays the Tcl syntax that corresponds with the GUI options you select. You can copy the command from the Console into a Tcl file. |

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Figure 40. Extra Info Tab

Setup Slack Breakdown On the Extra Info Tab

The Extra Info tab contains other timing metrics to help you diagnose timing closure issues, including Setup Slack Breakdown for the path.

The slack of a path specifies the margin by which the path meets its timing requirement. The setup slack breakdown is a numeric value that the Timing Analyzer calculates from the following timing requirements and path element delays:

Figure 41. Setup Slack Breakdown Calculations

A path can fail timing requirements for many varied reasons. For example, the clock relationship can be impossibly tight, or there can be excessive routing delays that alone cause failure for the timing path. Calculating the intrinsic margin of a timing path, and then comparing that margin to other delays of the path, can help identify the specific reasons why a path fails its timing requirement.

The Extra Info tab can help you identify potential significant or unexpected routing detours caused by congestion and hold time fix-up. The Extra Info tab can also report extra information for source timing endpoints that pass through the unregistered output of a RAM or DSP block, or for destination timing endpoints that pass through the unregistered input of a DSP block.

You can review the Extra Info data and Locate Path or Locate Chip Area in Chip Planner, Technology Map Viewer, or Resource Property Viewer to determine whether to make changes to improve placement and routing.

Some delay elements are more sensitive to a path's placement and routing than others. Intrinsic delays that are part of Setup Slack Breakdown are less sensitive to placement and routing, and are inherent in the RTL and timing requirements. Nonintrinsic delays are the other delays that are sensitive to placement and routing.

Table 16. Extra Info Tab Data

| Extra Info Data | Description | |----------------------------------|----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | Intrinsic Margin | Reports the intrinsic and non-intrinsic timing elements that comprise the timing path slack value. Intrinsic margin is a numeric value that the Timing Analyzer calculates from the timing requirements and path element delays. The Timing Analyzer also derives the slack of the path from the same requirements and delays, but with a different calculation. Intrinsic delays are less sensitive to placement and routing, and are inherent in the RTL and timing requirements. Non-intrinsic delays are the other delays that are sensitive to placement and routing. | | From Node Info | Specifies the node Type, any Retiming Restriction, and any Power-Up "Don't Care" attributes for the From Node. Consider removing the retiming restriction to allow retiming and improve performance for timing closure. | | To Node Info | Specifies the node Type, any Retiming Restriction, and any Power-Up "Don't Care" attributes for the To Node. Consider removing the retiming restriction to allow retiming and improve performance for timing closure. | | Max Fanout | Reports the maximum fan-out of register and combinational nodes in the path. | | Route Stage Congestion Impact | Reports whether routing has a Low , Medium , or High impact on congestion. A Low value suggests timing issues are not congestion related. A High value suggests competition for scarce routing resources plays a role in poor timing. | | Estimated Delay Added for Hold | Reports the estimated amount of delay added on to the fastest delay route to satisfy hold. This value can help you determine whether delays are routing congestion or Hold related. | | Sufficient Setup Margin for Hold | Reports whether the setup margin is suitable for the hold timing. Yes , indicates that the setup margin is sufficient. No indicates that the setup margin is insufficient for hold timing. | | Source/Destination Bounding Box | Reports the lower-left and upper-right coordinates for the boundary box enclosing the source and destination registers. In an ideal case, the Source/Destination Bounding Box , Cell Bounding Box , and Interconnect Bounding Box values are roughly the same, and the relative areas are approximately 1.0. If the cell bounding box size grows relative to the Source/Destination Bounding Box , that can indicate a potential unnecessary routing detour on the path. | | Source/Destination Area Covered | Reports the total area covered in terms of LABs. | | Source/Destination Relative Area | Reports the area for the source and destination, relative to the Source/Destination Bounding Box . The value is always 1.0, which equals the same size. | | Cell Bounding Box | Reports the lower-left and upper-right coordinates for the boundary box enclosing the source and destination registers, and any cells in the path. | | Cell Area Covered | Reports the area for the cell, relative to the Source/Destination Bounding Box . A value of 1.0 equals the same size. A value greater than 1.0 can indicate a path has a cell outside of the space between the registers in the path. |

The following describe the interpretation of timing conditions indicated by the Setup Slack Breakdown :

When the Setup Slack Breakdown is less than 0 -the path has such a tight timing relationship, a significant difference in microparameters, or such significant clock source uncertainty, that the path fails before the addition of any delay. Review the SDC constraints to verify that the timing relationship is correct. An incorrect relationship can exist between unrelated clocks that lack the proper timing cut. Ensure that parameterizable hard blocks (such as 20K RAM and DSP blocks) are fully registered. Investigate clock sources to verify that the clocks use global signals for routing.
When the clock skew exceeds the Setup Slack Breakdown -address the clock transfer to meet timing on the path. You may need to create clock region assignments. You might also need to redesign cross-clock transfers to switch from synchronous to asynchronous implementation, such as with a FIFO or other handshake.
When the cell delay is greater than its intrinsic margin -reduce the cell delay, as the path would fail timing even if the clocks are perfect and use no routing wires. Rewrite RTL to reduce the logic depth, restructure logic to allow the Compiler to use faster LUT inputs, or unblock retiming optimizations. The Compiler can automatically retime registers to reduce logic depth, but only in ways that maintain functionality and that the device architecture supports. To unblock the Hyper-Retimer, remove asynchronous resets and initial conditions.
When the interconnect delay is greater than its intrinsic margin -the path would fail timing even if the clocks are perfect, and there is no logic. This occurs if registers are too far apart, or a timing path detours around a congested chip area. Review the fan-in and fan-out of registers that are far apart. Apply Logic Lock regions so the Fitter places the registers closer together. Use Logic Lock regions only after determining why placement is initially poor.

Related Information

Hyperflex Architecture High-Performance Design Handbook

6.5.3.2. Report Logic Depth

The Timing Analyzer's Reports ➤ Design Metrics ➤ Report Logic Depth... command allows you to report the number of logic levels within a clock domain. This value typically corresponds to the number of look-up tables (LUTs) that a path passes through.

The equivalent scripting command is report_design_metrics -logic_depth . Report Logic Depth shows the distribution of logic depth among the critical paths, allowing you to identify areas where you can reduce logic levels in your RTL.

Figure 42. Report Logic Depth (Histogram)

Figure 43. Report Paths of Depth 3

Call report logic depth by topology for each clock, intraclock only.

Figure 44. Summary of Paths

Close timing with accurate histogram cross probing.

You can specify various options to customize the reporting.

Table 17. Report Logic Depth Settings

| Option | Description | |-------------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | Clocks | From Clock and To Clock filter paths in the report to show only the launching or latching clocks you specify. | | Targets | Specifies the target node for From Clock and To Clock to report logic depth with only those endpoints. Specify an I/O or register name or I/O port for this option. The field also supports wildcard characters. When the From , To , or Through boxes are empty, the Timing Analyzer assumes all possible targets in the device. The Through option limits the report for paths that pass through combinatorial logic, or a particular pin on a cell. | | Analysis type | The Setup , Hold , Recovery , and Removal analyses report the logic depths of the top X paths by slack. Topology analysis reports the logic depths of the top X paths by logic depth. | | Paths | Specifies the number of paths to display by endpoint and slack level. The default value for Report number of paths is 10, otherwise, the report can be very long. Enable Pairs only to list only one path for each pair of source and destination. Limit further with Maximum number of paths per endpoints . You can also filter paths by entering a value in the Maximum slack limit field. | | Detail | Specify whether to display on Histogram or full Path level of detail. | | Report panel name | Specifies the name of the report panel. You can optionally enable File name to write the information to a file. If you append .htm or .html as a suffix, the Timing Analyzer produces the report as HTML. If you enable File name , you can Overwrite or Append the file with latest data. | | Tcl command | Displays the Tcl syntax that corresponds with the GUI options you select. You can copy the command from the Console into a Tcl file. |

6.5.3.3. Report Neighbor Paths

The Timing Analyzer's Reports ➤ Design Metrics ➤ Report Neighbor Paths... command helps you to determine the root cause of critical paths (for example, high logic level, retiming limitation, sub-optimal placement, I/O column crossing, hold fixup, time borrowing, or others). The equivalent scripting command is report_design_metrics -neighbor_paths .

Figure 45. Report Neighbor Paths Report

Report Neighbor Paths reports the most timing-critical paths in the design, including associated slack, additional path summary information, and path bounding boxes. Report Neighbor Paths shows the most timing-critical Path Before and Path After each critical Path . You can optionally view multiple before and after paths. Retiming or logic balancing of the Path can simplify timing closure if there is negative slack on the Path , but positive slack on the Path Before or Path After .

Table 18. Report Neighbor Path Dialog Box Settings

| Option | Description | |---------------|-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | Clocks | From Clock and To Clock filter paths in the report to show only the launching or latching clocks you specify. | | Targets | Specifies the target node for From Clock and To Clock to report neighbor paths with only those endpoints. Specify an I/O or register name or I/O port for this option. The field also supports wildcard characters. When the From , To , or Through boxes are empty, the Timing Analyzer assumes all possible targets in the device. The Through option limits the report for paths that pass through combinatorial logic, or a particular pin on a cell. | | Analysis type | The Analysis type options are Setup , Hold , Recovery , or Removal . The Timing Analyzer reports the results for the type of analysis you select. | | Paths | Specifies the number of paths to display by endpoint and slack level. The default value for Report number of paths is 10, otherwise, the report can be very long. Enable Pairs only to list only one path for each pair of source and destination. Limit further with Maximum number of paths per endpoints . You can also filter paths by entering a value in the Maximum slack limit field. | | continued... | continued... |

| Option | Description | |---------------------------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | Report Number of Neighbor Paths | Specifies the number of neighbor paths to report, allowing you to view a number of the top adjacent paths entering the critical path, and the top paths exiting the critical path. | | Report panel name | Specifies the name of the report panel. You can optionally enable File name to write the information to a file. If you append .htm or .html as a suffix, the Timing Analyzer produces the report as HTML. If you enable File name , you can Overwrite or Append the file with latest data. | | Tcl command | Displays the Tcl syntax that corresponds with the GUI options you select. You can copy the command from the Console into a Tcl file. | | Extra Info | Specifies extra info. |

6.5.3.4. Report Register Spread

The Timing Analyzer's Reports ➤ Design Metrics ➤ Report Register Spread command analyzes the final placement to identify registers with sinks pulling them in various directions. These registers are potential candidates for duplication. The equivalent scripting command is report_register_spread .

Registers that drive in opposite directions and connect to high fan-out can have placement-warping effects on the floorplan that impact fMAX. The placement-warping may not cause timing failures. Therefore, you can view this report to identify such registers. Taking steps to address the registers listed in the report can make placement of the design easier and improve fMAX performance.

You can automate duplication of registers with the DUPLICATE_REGISTER and DUPLICATE_HIERARCHY_DEPTH .qsf assignments, or you can manually modify RTL to duplicate registers or refactor logic. Refer to "Automatic Register Duplication: Hierarchical Proximity" in Quartus Prime Pro Edition User Guide: Design Optimization .

Figure 46. Report Register Spread Report

You can specify various options to customize the report.

Table 19. Report Register Spread Settings

| Option | Available Settings | |-------------|---------------------------------------------------------------| | Spread Type | Specifies the type of spread data in the report: continued... |

| Option | Available Settings | |----------------------------|-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | | • Tension -reports the sum over each sink of the distance from it to the centroid of all the sinks. • Angle -reports how far around the source register the fan-outs wrap, expressed from 0 to 360 degrees. This value corresponds to 360 minus the maximum angle between any two angularly adjacent sinks. This metric complements Tension by identifying registers which are surrounded by their sinks in all directions, and not those registers only being pulled in a few directions. • Span -reports the maximum 1-dimensional delta between the left bottom-most sink and the right top-most sink. • Area -reports the coverage of the sinks by number of LABs on the FPGA device. This option multiplies the span of the sinks in both X- and Y- dimensions. This metric complements Span by incorporating both dimensional spans of the sinks, and not only the maximum sink. • Count -reports registers with the largest sink counts. | | Sink Type | Specifies the type of sink in the report: • Endpoint -the nodes (usually registers) that terminate timing paths from a register. • Immediate Fanout -the immediately connected nodes of the register. For example, lookup tables, other registers, RAM, or DSP blocks. | | From Clock | Filters paths in the report to show only the launching clocks you specify. | | To Clock | Filters paths in the report to show only the latching clocks you specify, allowing you to debug one clock at a time. | | Report number of registers | Specifies the number of registers to display in the report. The default value for Report number of registers is 10. | | Report panel name | Specifies the name of the report panel. You can optionally enable File name to write the information to a file. If you append .htm or .html as a suffix, the Timing Analyzer produces the report as HTML. If you enable File name , you can Overwrite or Append the file with latest data. | | Tcl command | Displays the Tcl syntax that corresponds with the GUI options you select. You can copy the command from the Console into a Tcl file. |

Figure 47. Report Register Spread Types

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Figure 48. Report Register Spread Dialog Box

6.5.3.4.1. Understanding Report Register Spread Data

It is helpful to understand the concept of tension in utilizing Report Register Spread data. Tension is the sum over each sink of the distance from it to the centroid of all the sinks. The tension value is therefore dependent on the number of sinks.

What Is a Good Tension Value?

There is no absolute threshold for a good or bad tension value. A register's tension value depends on the number of fan-outs, their distance, and the degree to which the fan-outs go in opposite directions. When tension is high, duplicating the registers with high tension can be the easiest way to reduce the tension value.

Figure 49. Register Tension Values in Report Register Spread

| Report Register Spread (endpoint tension | Report Register Spread (endpoint tension | Report Register Spread (endpoint tension | Report Register Spread (endpoint tension | |--------------------------------------------|--------------------------------------------|---------------------------------------------------|--------------------------------------------| | | de | de | de | | Endpoint Centroid | Endpoint Centroid | Total Distance of Endpoints to Centroid (Tension) | Average Distance | | (94,86) | (94,86) | 13785 | 12 | | (94,86) | (94,86) | 13782 | 12 | | (94,86) | (94,86) | 13456 | 12 | | (94,86) | (94,86) | 13453 | | | (94,86) | (94,86) | 13440 | | | (94,86) | (94,86) | 13404 | | | (94,86) | (94,86) | 13404 | | | (94,86) | (94,86) | 13404 | 12 | | (94,86) | (94,86) | 13404 | 12 | | ((94,86) | ((94,86) | 13404 | 12 |

Duplicate a Register to Reduce Tension Value

You can use Report Register Spread in combination with other design information to make effective changes. For example, in a design suffering from routing congestion, congested logic is sometimes pulled together by registers that are also near the top of the tension list.

You can use Report Register Spread to cross-reference the registers listed near the top of the tension data with design hierarchies affected by congestion. You can then duplicate a register near the top of the tension list to allow the congested logic to spread farther apart, thereby reducing congestion.

Selecting Registers for Duplication

The best candidate registers for duplication are those with a single data fan-in because such nodes are unlikely to have much additional congestion to feed other register copies. Registers that have complex support logic (high numbers of fan-in signals) are poor candidates for duplication because all the fan-in sources then have to feed other copies of the register.

Consider the following guidelines in selecting registers for duplication:

Review the way the fan-outs are distributed physically and logically. For the best performance improvement, fan-outs that connect to a new duplicate should be in a similar physical location on the chip.
If a register with high tension fans out to two separate instances, on opposite sides of the chip, you should make a duplicate for each instance.
If a register with high tension fans out to a cloud of related registers (like an enable signal to a pipeline stage in a bus), it can be difficult to segment the fanouts in a way that correlates to their physical placement. The individual bits of a pipeline stage of a bus might not have any attraction or inherent connectivity to a specific physical part of the chip.

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Consider an example register from the tension report with the following fan-out pattern in Chip Planner:

Figure 50. Example Fan-Out Pattern in Chip Planner

The best case scenario is for the fan-outs in the upper-right quadrant of the Chip Planner to be logically separate from the fan-outs in the lower-left quadrant. You can achieve this by creating a duplicate of the register and connecting the fan-outs in the upper-right quadrant to one register, and the fan-outs in the lower-left quadrant to the other register.

6.5.3.5. Report Route Net of Interest

The Timing Analyzer's Reports ➤ Design Metrics ➤ Report Route Net of Interest... command allows you to report the nets that require the most effort from the router. The report shows the percentage of total router effort for the nets reported. The equivalent scripting command is report_route_net_of_interest .

This report allows you to identify nets that should not require significant router effort. For example, you might expect that low speed management interface nets are not timing critical, and therefore not require much router effort. However, if Report Route Net of Interest reports that some nets in the low speed management interface require significant effort from the router, you can investigate that further. The investigation can determine whether the timing constraints are correct, whether the fan-out is significant and can reduce through driver duplication, or whether the net passes through congested areas.

Figure 51. Report Route Net of Interest Report

Figure 52. Report Route Net of Interest Dialog Box

From the Route Net of Interest Report in the Timing Analyzer GUI, you can right-click on any net and run Report Timing for more details about the net, its slack, and any of the net's paths.

Table 20. Report Route Net of Interest Settings

| Option | Available Settings | |-------------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | Nets | Specifies the Maximum number of nets to report . The default value is 50. | | Report panel name | Specifies the name of the report panel. You can optionally enable File name to write the information to a file. If you append .htm or .html as a suffix, the Timing Analyzer produces the report as HTML. If you enable File name , you can Overwrite or Append the file with latest data. | | Tcl command | Displays the Tcl syntax that corresponds with the GUI options you select. You can copy the command from the Console into a Tcl file. |

6.5.3.6. Report Retiming Restrictions

The Timing Analyzer's Reports ➤ Design Metrics ➤ Report Retiming report_retiming_restrictions is the equivalent scripting command.

Restrictions... command allows you to report the occurrences of design conditions that restrict Hyper-Retiming, such as Power-up "Care" restrictions, and don't touch or preserve attributes for each port. You can refer to this report to improve the circuit and remove retiming restrictions that limit circuit performance.

Figure 53. Report Retiming Restrictions Report

For table entries with two number values, the number in parentheses indicates the number of retiming restrictions in the specific entity alone. The number listed outside of parentheses indicates the number of retiming restrictions in the specific entity and all of its sub-entities in the hierarchy .

Related Information

Retiming Restrictions and Workarounds, Hyperflex Architecture High-Performance Design Handbook

6.5.3.7. Report Pipelining Information

The Timing Analyzer's Reports ➤ Design Metrics ➤ Report Pipelining Information... command allows you to generate a report that can help you to identify potential areas of over-pipelining in your design. Excessive pipelining unnecessarily consumes area. The equivalent scripting command is report_pipelining_info .

Report Pipelining Information... does not perform any functional analysis in making the recommended pipeline stage adjustment. You must be aware of any potential functional changes from removing pipeline stages. There may be circumstances when all the stages in a register pipeline are necessary for functional reasons. The report helps to identify location with more registers than necessary for covering distance.

Figure 54. Report Pipelining Information Report

Figure 55. Report Detailed Pipelining

The detailed report shows every register in a tree structure. Over- or under-pipelining recommendations are in the main report. The following shows every single register inside the bus chain in a tree structure:

Figure 56. Detailed Pipelining Result

To help identify potential over-pipelining, Report Pipelining Information reports:

The recommended pipeline stage adjustment across bus
The minimum total slack of one bit across bus
The minimum average slack of one bit across bus
The distance between the registers
The width of buses in your design
The number of sequential registers
The number of registers on the bus

The Recommended Pipeline Stage Adjustment Across Bus reports the number of registers that you can remove from the bus for each bit. The Average Distance Per Stage, Max Distance Per Stage, and Min Distance Per Stage columns report the Manhattan distance measured in logic array blocks (LABs). The Bus Average Depth, Bus Max Depth, and Bus Min Depth columns report the number of sequential, single fan-out registers. For registers that have more than one clock source, the report lists the fastest one.

The 1+ sign under Recommended Pipeline Stage Adjustment Across Bus column means that the bus might need to add more registers to meet timing requirement. Refer to the Fast Forward Timing Closure Recommendations report.

If the report identifies a large register chain with multiple sequential registers, and the distance between registers is low, that condition can suggest over-pipelining. You may be able to remove some registers to recover some of the device area and reduce congestion.

The following options are available for this report:

Figure 57. Report Pipelining Information Dialog Box

Table 21. Report Pipelining Information Settings

| Option | Available Settings | |-------------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | Pipeline | Specifies the thresholds for reporting a register pipeline. You can define the Minimum average bus depth , the Minimum bus width , and the Maximum number of rows that the report includes. | | Report panel name | Specifies the name of the report panel. You can optionally enable File name to write the information to a file. If you append .htm or .html as a suffix, the Timing Analyzer produces the report as HTML. If you enable File name , you can Overwrite or Append the file with latest data. | | Tcl command | Displays the Tcl syntax that corresponds with the GUI options you select. You can copy the command from the Console into a Tcl file. |

6.5.3.8. Report CDC Viewer

The Timing Analyzer's Reports ➤ Clock Domain Crossings ➤ Report CDC Viewer... command allows you to configure and display a custom clock domain crossing report and the Clock Domain Crossing (CDC) Viewer. The CDC Viewer graphically displays the setup, hold, recovery, or removal analysis of all clock transfers in your design. The equivalent scripting command is report_cdc_viewer .

Table 22. Report Clock Domain Crossing Viewer Settings

| Option | Description | |-------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | Clocks | From Clock and To Clock filter paths in the report to show only the launching or latching clocks you specify. | | Analysis type | Options are Setup , Hold , Recovery , or Removal . The Timing Analyzer reports the results for the type of analysis you select. | | Transfers | Specifies the type of clock transfers to include or exclude from the report, including Timed transfers , Fully cut transfers , Clock groups, Inactive clocks , and Non-crossing transfers . You can specify the Maximum slack limit and Grid options for the report. | | Detail level | Full shows all details of the report and Summary filters the details and shows summary data. | | Report panel name | Specifies the name of the report panel. You can optionally enable File name to write the information to a file. If you append .htm or .html as a suffix, the Timing Analyzer produces the report as HTML. If you enable File name , you can Overwrite or Append the file with latest data, and specify Grid or List format. Note: In grid format reports, clocks with non-crossing transfers always appear if they have transfers between other clocks. | | Tcl command | Displays the Tcl syntax that corresponds with the GUI options you select. You can copy the command from the Console into a Tcl file. |

You can specify the following options to customize CDC Viewer reporting:

Table 23. CDC Viewer Report Controls

| Control | Description | |------------------------------|-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | From Clock: and To Clock: | Filters the display according to the clock names you specify. Click From Clock: or To Clock: to search for specific clock names. | | Legend | Defines the status colors. A color coded grid displays the clock transfer status. The clock headers list each clock with transfers in the design. The GUI truncates long clock names, but you can view the full name in a tool tip or by resizing the clock header cell. The GUI represents the generated clocks as children of the parent clock. A '+' icon next to a clock name indicates the presence of generated clocks. Clicking on the clock header displays the generated clocks associated with that clock. | | Toggle Data | The text in each transfer cell contains data specific to each transfer. Turn on or off display of the following types of data: • Number of timed endpoints between clocks- the number of timed, endpoint- unique paths in the transfer. A path being 'timed' means that analysis occurs on that path. Only paths with unique endpoints count towards this total. • Number of cut endpoints between clocks- the number of cut endpoint-unique paths, instead of timed paths. These paths are cut by either a false path or clock group assignment. Timing analysis skips such paths. • Worst-case slack between clocks- the worst-case slack among all endpoint-unique paths in the transfer. • Total negative slack between clocks- the sum of all negative slacks among all endpoint-unique paths in this transfer. • Tightest relationship between clocks- the lowest-value setup, hold, recovery, or removal relationship between the two clocks in this transfer. | | Show Filters and Show Legend | Turns on or off Filters and Legend . |

Each block in the grid is a transfer cell. Each transfer cell uses color and text to display important details of the paths in the transfer. The color coding represents the following states:

Table 24. Transfer Cell Content

| Cell Color | Color Legend | |--------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | Black | Indicates no transfers. There are no paths crossing between the source and destination clock of this cell. | | Green | Indicates passing timing. All timing paths in this transfer, that have not been cut, meet their timing requirements. | | Red | Indicates failing timing. One or more of the timing paths in the transfer do not meet their timing requirements. If the transfer is between unrelated clocks, the paths likely require a synchronizer chain. | | Blue | Indicates clock groups. The source and destination clocks of these transfers are cut by means of asynchronous clock groups. | | Gray | Indicates a cut transfer. All paths in this transfer are cut by false paths. Therefore, timing analysis does not consider these paths. | | Orange | Indicates inactive clocks. One of the clocks in the transfer is an inactive clock (with the set_active_clocks command). The Timing Analyzer ignores such transfers. |

Right-click menus allow you to perform operations on transfer cells and clock headers. When the operation is a Timing Analyzer report or SDC command, a dialog box opens containing the contents of the transfer cell.

Table 25. Transfer Cell Right-Click Menus

| Command | Description | |---------------------------------------|----------------------------------------------------------------------------------------------| | Copy | Copies the contents of the transfer cell or clock header to the clipboard. | | Report Timing | Reports timing. Not available for transfer cells with no valid paths (gray or black cells). | | Report Endpoints | Reports endpoints. Not available for transfer cells with no cut paths (gray or black cells). | | Report False Path | Reports false paths. Not available for transfer cells with no valid paths (black cells). | | Report Exceptions | Reports exceptions. Only available for clock group transfers (blue cells). | | Report Exceptions (with clock groups) | Reports exceptions with clock groups. Only available for clock group transfers (blue cells). | | Set False Path | Sets a false path constraint. | | Set Multicycle Path | Sets a multicycle path exception. | | Set Min Delay | Sets a min delay constraint. | | Set Max Delay | Sets a max delay constraint. | | Set Clock Uncertainty | Sets a clock uncertainty constraint. |

Table 26. Clock Header Right-Click Menus

| Command | Description | |----------------------------------|-----------------------------------------------------------------------------------------------------------------------------------------------------| | Copy (include children) | Copies the name of the clock header, and the names of each of its derived clocks. This option only appears for clock headers with generated clocks. | | Expand/Collapse All Rows/Columns | Shows or hides all derived clocks in the grid. | | continued... | continued... |

| Command | Description | |-----------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | Create Slack Histogram | Generates a slack histogram report for the clock you select. | | Report Timing From/To Clock | Generates a timing report for the clock you select. If you do not expand the clock to display derived clocks, the timing report includes all clocks that derive from the clock. To prevent this, expand the clock before right-clicking it. | | Remove Clock(s) | Removes the clock you select from the design. If you do not expand the clock, timing analysis removes all clocks that derive from the clock. |

You can view CDC Viewer output in any of the following formats:

A report panel in the Timing Analyzer
Output in the Timing Analyzer Tcl console
A plain-text file
An HTML file you can view in a web browser.

Related Information

Tips for Analyzing Failing Clock Paths that Cross Clock Domains on page 150

6.5.3.9. Timing Closure Recommendations

The Report Timing Closure Recommendations command in the Timing Analyzer Task pane analyzes paths and provides specific recommendations based on path characteristics. Since Design Assistant now provides more targeted timing closure recommendations, Report Timing Closure Recommendations is marked for deprecation.

6.5.3.10. Global Network Buffers

Routing paths allow you to identify global network buffers that fail timing. Buffer locations names reflect the network they drive.

CLK_CTRL_Gn -for Global driver
CLK_CTRL_Rn -for Regional driver

Buffers that access the global networks are in the center of each side of the device. Buffering to route a core logic signal on a global signal network causes insertion delay. Trade-offs to consider for global and non-global routing are source location, insertion delay, fan-out, distance a signal travels, and possible congestion if the signal demotes to local routing.

6.5.3.10.1. Source Location

If you cannot move the register feeding the global buffer closer, then consider changing either the design logic or the routing type.

6.5.3.10.2. Insertion Delay

If the design requires a global signal, consider adding half a cycle to timing by using a negative-edge triggered register to generate the signal, and use a multicycle setup constraint.

Figure 58. Negative-Edge Triggered Register

Figure 59. Multicycle Setup Constraint

6.5.3.10.3. Fan-Out

Nodes with very high fan-out that use local routing tend to pull logic that they drive close to the source node. This can make other paths fail timing. Duplicating registers can help reduce the impact of high fan-out paths. Consider manually duplicating and preserving these registers. Using a MAX_FANOUT assignment may make arbitrary groups of fan-out nodes, whereas a designer can make more intelligent fan-out groups.

6.5.3.10.4. Global Signal Assignment

You can use the Global Signal assignment to control the global signal usage on a persignal basis. For example, if a signal needs local routing, you set the Global Signal assignment to Off .

6.5.3.11. Resets and Global Networks

The Compiler often routes reset signals on global networks. Sometimes, the use of a global network causes recovery failures. Consider reviewing the placement of the register that generates the reset and the routing path of the signal.

6.5.3.12. Suspicious Setup

Suspicious setup failures include paths with very small or very large requirements.

One typical cause is math precision error. For example, 10Mhz/3 = 33.33 ns per period. In three cycles, the time is 99.999 ns vs 100.000 ns. Setting a maximum delay can provide an appropriate setup relationship.

Another cause of failure are paths that must be false by design intent, such as:

Asynchronous paths handled through FIFOs, or
Slow asynchronous paths that rely on handshaking for data that remain available for multiple clock cycles.

To prevent the Fitter from having to meet unnecessarily restrictive timing requirements, consider adding false or multicycle path statements.

6.5.3.13. Auto Shift Register Replacement

During synthesis, the Compiler can convert shift registers or register chains into RAMs to save area. However, conversion to RAM often reduces speed. The Compiler names the converted registers with the prefix "altshift_taps".

If paths that fail timing begin or end in shift registers, consider disabling the Auto Shift Register Replacement option. Do not convert registers that are intended for pipelining.
For shift registers that are converted to a chain, evaluate area/speed trade off of implementing in RAM or logic cells.
If a design uses nearly the full device capacity, you can save area by shifting register conversion to RAM, benefiting non-critical clock domains. You can change the settings from the default AUTO to OFF globally, or on a register or hierarchy basis.

6.5.3.14. Clocking Architecture

For better timing results, place all registers driven by a regional clock in one quadrant of the chip. You can review the clock region boundaries in the Chip Planner.

Timing failure can occur when the I/O interface at the top of the device connects to logic driven by a regional clock which is in one quadrant of the device, and placement restrictions force long paths to and from I/Os to logic across quadrants.

Use a different type of clock source to drive the logic, such as global, which covers the whole device, or dual-regional which covers half the device. Alternatively, you can reduce the frequency of the I/O interface to accommodate the long path delays. You can also redesign the pinout of the device to place all the specified I/Os adjacent to the regional clock quadrant. This issue can happen when register locations are restricted, such as with Logic Lock regions, clocking resources, or hard blocks (memories, DSPs, IPs).

The Extra Fitter Information tab in the Timing Analyzer timing report informs you when placement is restricted for nodes in a path.

Related Information

Viewing Available Clock Networks in Chip Planner on page 171

6.5.4. Try Optional Fitter Settings

This section focuses only on the optional timing-optimization Fitter settings, which are the Optimize Hold Timing , Optimize Multi-Corner Timing , and Fitter Aggressive Routability Optimization .

Caution:

The settings that best optimize different designs might vary. The group of settings that work best for one design does not necessarily produce the best result for another design.

Related Information

Advanced Fitter Setting Dialog Box Help Topic In Quartus Prime Help

6.5.4.1. Optimize Hold Timing

The Optimize Hold Timing option directs the Quartus Prime software to optimize minimum delay timing constraints.

When you turn on Optimize Hold Timing in the Advanced Fitter Settings dialog box, the Quartus Prime software adds delay to paths to ensure that your design meets the minimum delay requirements. If you select I/O Paths and Minimum TPD Paths , the Fitter works to meet the following criteria:

Hold times (tH) from the device input pins to the registers
Minimum delays from I/O pins to I/O registers or from I/O registers to I/O pins
Minimum clock-to-out time (tCO) from registers to output pins

If you select All Paths , the Fitter also works to meet hold requirements from registers to registers, as highlighted in blue in the figure, in which a derived clock generated with logic causes a hold time problem on another register.

Figure 60. Optimize Hold Timing Option Fixing an Internal Hold Time Violation

However, if your design still has internal hold time violations between registers, you can manually add delays by instantiating LCELL primitives, or by making changes to your design, such as using a clock enable signal instead of a derived or gated clock.

Related Information

Quartus Prime Pro Edition User Guide: Design Recommendations

6.5.4.2. Fitter Aggressive Routability Optimization

The Fitter Aggressive Routability Optimizations logic option allows you to specify whether the Fitter aggressively optimizes for routability. Performing aggressive routability optimizations may decrease design speed, but may also reduce routing wire usage and routing time.

This option is useful if routing resources are resulting in no-fit errors, and you want to reduce routing wire use.

Quartus Prime Pro Edition User Guide: Design Optimization

The table lists the settings for the Fitter Aggressive Routability Optimizations logic option.

Table 27. Fitter Aggressive Routability Optimizations Logic Option Settings

| Settings | Description | |---------------|----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | Always | The Fitter always performs aggressive routability optimizations. If you set the Fitter Aggressive Routability Optimizations logic option to Always , reducing wire utilization may affect the performance of your design. | | Never | The Fitter never performs aggressive routability optimizations. If improving timing is more important than reducing wire usage, then set this option to Automatically or Never . | | Automatically | The Fitter performs aggressive routability optimizations automatically, based on the routability and timing requirements of the design. If improving timing is more important than reducing wire usage, then set this option to Automatically or Never . |

6.5.5. Back-Annotating Optimized Assignments

The Compiler maps the elements of your design to specific device resources during fitting. After compilation, you can back-annotate (copy) the Compiler's resource assignments to preserve that same implementation in subsequent compilations. Backannotation can simplify timing closure by allowing you to lock down placement of your optimized results.

Locking down placement of large blocks related to Clocks, RAMs, and DSPs can produce higher fMAX with less noise. Large blocks like RAMs and DSPs have heavier connectivity than regular LABs, complicating movement during placement. When a seed produces good results from suitable RAM and DSP placement, you can capture that placement with back-annotation. Subsequent compiles can then benefit from the high quality RAM and DSP placement from the good seed.

Figure 61. Back-Annotate Assignments Dialog Box

To back-annotate (copy) the device resource assignments from the last compilation to the project .qsf (or to a Tcl file) for use in the next compilation:

Run a full compilation, or run the Fitter through at least the Place stage.
Click Assignments ➤ Back-Annotate Assignments .
Under Assignments to back-annotate , specify whether you want to preserve Pin assignments , RAM assignments , DSP assignments , Clock assignments , and Clock Spine assignments in the back-annotation.
In Filter , specify a text string (including wildcards) if you want to filter backannotated assignments by entity name.
Under Output , specify whether to save the back-annotated assignments to the .qsf or to a Tcl file. A default Tcl file name displays.

Alternatively, you can run back-annotation with the following quartus_cdb executable. The Shell command field displays the shell command constructed by the options that you specify in the GUI.

quartus_cdb chiptrip_nf --back_annotate --pin --ram --dsp --clocks \ --spines --file "<file>.tcl"

Note: Check available arguments by running quartus_cdb <project> --back_annotate --help .

6.5.6. Optimize Settings with Design Space Explorer II

The Design Space Explorer II tool ( Tools ➤ Launch Design Space Explorer II ) helps you to find the optimal project settings for the performance, power, and resource optimization goals that you specify in the tool. Design Space Explorer II (DSE II) processes your design using different combinations of settings and constraints based on the goals you specify, and then reports the best combination of settings and constraints for the design. DSE II supports parallel processing, allowing you to distribute the multi-compilation workload across distributed remote resources.

In DSE II, an exploration point represents one collection of Synthesis, Fitter, and placement settings. A design exploration signifies a group of exploration points that DSE II compiles and compares results from. Each design exploration can contain different Fitter seeds. If a design is close to meeting timing or area requirements, you can try compiling different seeds in DSE II to find a seed that meets timing or area requirements. You can choose to enable All Compilation Strategies to explore the results for every compilation strategy at once.

Figure 62. Design Space Explorer II

You can run DSE II at any step in the design process; however, because large changes in a design can neutralize gains achieved from optimizing settings, Altera recommends that you run DSE II late in the design cycle.

Note:

When comparing the results of different seed sweeps with DSE II, changing any of the following variables can cause differences in the compilation results between seed sweeps, resulting in a somewhat different fit in each case:

The number or type of CPUs that DSE II uses to perform the seed sweeps
Any change to the operating system
Any change to source file content or location
Any change to the Compiler settings or Timing Analyzer settings

For more information, refer to Fitter Seed on page 149.

Related Information

Using Design Space Explorer
21 Minute Online Course
Setting Up Remote Farm Using Design Space Explorer II, Quartus Prime Pro Edition User Guide: Getting Started

6.5.6.1. Remote Compilation Services

6.5.6.1.1. Running Quartus DSE on Kubernetes Clusters

Kubernetes is an open-source container orchestration platform that automates the deployment, scaling, and management of containerized applications across clusters of computers.

Kubernetes offers significant advantages. It can automatically distribute computeintensive compilation jobs across available hardware resources, provide fault tolerance by restarting failed compilations, and enable efficient resource utilization by scheduling multiple jobs based on system capacity.

Many public cloud service providers offer Kubernetes as a managed service. These include Google Cloud's Google Kubernetes Engine (GKE), Amazon Web Services' Elastic Kubernetes Service (EKS), and Microsoft's Azure Kubernetes Service (AKS). DSE is designed to work with all major public cloud-managed Kubernetes services.

In Kubernetes, a worker pool (also called a node pool) is a group of machines that run your applications and jobs. You can create different worker pools with various specifications to match your workload requirements. To reduce costs, the DSE worker pool should automatically scale down to zero nodes when no compilation jobs are running. To make this work properly, the worker pool must only run DSE jobs and nothing else. Kubernetes provides a feature called "taints and tolerations" to control which pods can run on specific nodes. DSE is already configured to work with the quartus.altera.com taint. When you create your node pool, add the quartus.altera.com taint to enable this feature.

Without this taint, Kubernetes control pods might be placed on your DSE worker nodes. This creates a problem because control pods may run continuously and never stop, so the node pool never become empty. As a result, auto-scaling cannot remove empty nodes even when no compilation jobs are running.

The solution ensures that DSE compilation jobs run on dedicated high-performance nodes with high CPU and memory, while Kubernetes control pods run on separate, lower-cost nodes. This allows worker nodes to scale down to zero when all compilation jobs finish, so you only pay for resources when you actually need them.

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The following are steps to configure and set up DSE to work with Kubernetes clusters.

Public Cloud Kubernetes Cluster on Azure AKS Example

The following script creates a Kubernetes cluster on Azure using their AKS (Azure Kubernetes Service) managed service.

Prerequisites: This example assumes you already have:

An active Azure subscription.
The Azure CLI tool installed on your system.
Successfully logged in to Azure using the az login command.

Optional Performance Enhancement: For faster container image downloads, this example uses Azure's artifact streaming feature. Note that this feature is currently in preview and requires the aks-preview extension to be installed.

export DSE_CLUSTER_NAME=<cluster name> export DSE_NODE_RESOURCE_GROUP=<node resource group> export DSE_RESOURCE_GROUP=<resource group> export MYACR=<container registry> # Artifact streaming is still in preview and requires the aks-preview extension. # This step can be skipped once Azure makes artifact stream a production feature. az extension add --name aks-preview az feature register --namespace Microsoft.ContainerService --name ArtifactStreamingPreview az group create \ --location westus \ --name $DSE_RESOURCE_GROUP MYACR=mycontainerregistry az acr create --name $MYACR \ --resource-group myContainerRegistryResourceGroup --sku premium az aks create \ --name $DSE_CLUSTER_NAME \ --resource-group $DSE_RESOURCE_GROUP \ --enable-artifact-streaming \ --enable-cluster-autoscaler \ --kubernetes-version 1.31 \ --max-count 5 \ --min-count 1 \ --network-plugin kubenet \ --network-policy calico \ --no-ssh-key \ --node-count 1 \ --node-resource-group $DSE_NODE_RESOURCE_GROUP \ --node-vm-size Standard_D2ds_v5 \ --nodepool-name agentpool \ --attach-acr $MYACR az aks nodepool add \ --cluster-name $DSE_CLUSTER_NAME \ --name userpool16 \ --resource-group $DSE_RESOURCE_GROUP \ --enable-artifact-streaming \ --enable-cluster-autoscaler \ --labels quartus.altera.com=enabled \ --max-count 8 \ --min-count 0 \ --node-count 0 \ --node-osdisk-size 128 \

--node-taints quartus.altera.com=enabled:NoSchedule \ --node-vm-size Standard_D16s_v5 \ --scale-down-mode Deallocate

After creating the cluster or if user has an Azure AKS cluster already this command downloads the kubeconfig file:

az aks get-credentials \ --name $DSE_CLUSTER_NAME \ --resource-group $DSE_RESOURCE_GROUP

Kubernetes Cluster Setup

Requirements:

DSE requires permission to launch Kubernetes jobs within your cluster. You can grant this permission by creating a Kubernetes Service Account. This is a one-time setup process.

Option 1: Create a Service Account

For DSE to launch worker pods inside a cluster, it needs to use a Service Account to obtain the necessary permissions. A Kubernetes manifest template is provided at the following location:

<quartus installation dir>/quartus/common/python/lib/site-packages/quartus/dse/ plugins/farms/kube_job_serviceaccount_template.json

Steps to configure:

Copy the template file : Make a copy of
kube_job_serviceaccount_template.json to your working directory.
Customize the configuration : Update the copied file with values appropriate for your cluster settings, such as the namespace value.

In the example below, the JSON file will create a Service Account called "quartusdse" in the "validation" namespace.

{ "apiVersion": "v1", "items": [ { "apiVersion": "v1", "kind": "ServiceAccount", "metadata": { "name": "quartus-dse" } }, { "apiVersion": "rbac.authorization.k8s.io/v1", "kind": "Role", "metadata": { "name": "quartus-dse", "namespace": "validation" }, "rules": [ { "apiGroups": [ "" ], "resources": [ "pods", "pods/log",

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"events" ], "verbs": [ "create", "get", "delete", "list", "watch" ] }, { "apiGroups": [ "batch" ], "resources": [ "jobs" ], "verbs": [ "create", "get", "delete", "list", "watch" ] } ] }, { "apiVersion": "rbac.authorization.k8s.io/v1", "kind": "RoleBinding", "metadata": { "name": "quartus-dse", "namespace": "validation" }, "roleRef": { "apiGroup": "rbac.authorization.k8s.io", "kind": "Role", "name": "quartus-dse" }, "subjects": [ { "kind": "ServiceAccount", "name": "quartus-dse", "namespace": "validation" } ] } ], "kind": "List" }

Create the service account : To apply the configuration and create the service account, run:

kubectl --namespace <namespace> apply -f <serviceaccount.json>

Option 2: Enable Automatic Service Account Creation

DSE can automatically create the Service Account for you. To enable this feature, your user account must have permission to access the Kubernetes RBAC (Role-Based Access Control) API. Specifically, you need access to the rbac.authorization.k8s.io/v1 API.

Requirements:

Your Kubernetes user must have cluster administrator privileges or equivalent RBAC permissions.
The cluster must have RBAC enabled.

This option is more convenient as it eliminates the manual Service Account creation step but it requires higher-level permissions in your Kubernetes cluster.

Container Image with Quartus

DSE requires a container image that includes the appropriate version of Quartus Prime installed, or is configured with correct mounts to access Quartus Prime from the host system. Additionally, this image must have the kubectl utility installed for Kubernetes operations.

Public Container Images

Altera publishes official Quartus Prime container images on Docker Hub. The following images are available Quartus Prime Pro Edition software version 25.3 for different device families:

All families (full compile support for all device families): docker.io/ alterafpga/quartuspro-v25.3:all
Agilex 3 (optimized for Agilex 3 designs): docker.io/alterafpga/ quartuspro-v25.3:agilex3
Agilex 5 (optimized for Agilex 5 designs): docker.io/alterafpga/quartusprov25.3:agilex5
Agilex 7 (optimized for Agilex 7 designs): docker.io/alterafpga/quartusprov25.3:agilex7

Related Information

Altera Docker Hub

6.5.6.1.2. Running Design Space Exploration with Kubernetes

The procedures below demonstrate how to set up and configure DSE with Kubernetes.

Launch Quartus Design Space Explorer

Run quartus_dsew to start the Design Space Explorer.
Open your project using the Open Project button or select one from the recently used projects list.

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Setup Kubernetes Configuration

Click Setup in the left toolbar.
For Compilation Type , select Remote and choose Kubernetes from the dropdown menu.
Enable out-of-network mode by setting Remote Cluster to on .

Service Account Configuration

Enter a Service Account name that your cluster administrator has created. The Service Account enables workflows running inside the cluster to get permission to launch additional pods and jobs.

If your cluster administrator has not created a Service Account but has enabled RBAC API access for your user account, you can allow DSE to create the Service Account automatically. Set Create Service Account to on .

Kubectl Configuration

Under Full path to kubectl , enter the complete file path for the kubectl executable. If kubectl is already in your system PATH, you can leave this field blank.

Kubeconfig File Setup

In the Kubeconfig File field, enter the full path to your kubeconfig file. This file contains user credentials and cluster connection information.

Namespace Configuration

A cluster can have one or more namespaces that partition the cluster resources. Enter the name of the namespace you plan to use.

Security Note - Protecting Your Kubeconfig File

The kubeconfig file contains sensitive user credentials and must be protected:

On Linux : Use chmod 600 <kubeconfig file> to make it accessible only to the file owner Example: chmod 600 ~/.kube/config
On Windows : Use the icacls command to restrict access to your user account only:
Change Windows ACLs on kubeconfig file to disable inherited permission from parent folders. icacls %USERPROFILE%.kube\config /inheritance:r # Resets and grant full control of kubeconfig file to current Windows user icacls %USERPROFILE%.kube\config /grant:r "%USERNAME%:F"

Image Pull Policy

In Pull image before running , select how to download the container image:

Leave blank to pull the image only once.
Set to Always to allow Kubernetes to download a new image if available.

Container Image Setup

In the Container Image with Quartus installed field, enter the name of the container image to use. This container provides a specific version of Quartus Prime for your compilations.

Example images: docker.io/alterafpga/quartusprov25.3:agilex5

Initial Working Directory

Set the Initial Work Directory to specify where DSE should run within the container.

Example: /tmp/run1

Compute Resource Requirements

CPU Limit : Sets the number of CPUs to request from the cluster.
Memory Limit : Sets the memory requirements for compilation Example: 64Gi for 64 Gigabytes.

Time Limit

Active Deadline Seconds sets a time limit for how long the exploration can run. Jobs that do not finish within this time will be automatically terminated. The default value is 86400 seconds (1 day). On public cloud platforms, this helps control cloud costs by preventing runaway jobs.

License Server

Use the LM_LICENSE_FILE entry to specify the license server(s) that Quartus should use within the cluster.

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How DSE Connects to Kubernetes

When the DSE GUI starts, it launches a local quartus_dse process to manage the remote DSE execution. This local process uses the kubectl command to launch quartus_dse within the Kubernetes cluster. The kubectl tool reads the kubeconfig file to retrieve the Kubernetes API Server address for your cluster. In managed Kubernetes clusters from public cloud providers, this server is accessible from anywhere on the internet, with authentication handled using certificates stored in the kubeconfig file. Since the Kubernetes pod running quartus_dse operates behind a firewall and is not directly accessible from external networks, DSE uses kubectl to request that the Kubernetes API server establish a port-forward connection from the pod to your local machine. This port-forward feature makes the remote pod reachable using localhost:<local port> on your computer. DSE establishes this connection using the command kubectl --kubeconfig <path to kubeconfig> -namespace <namespace> port-forward pod/quartus-dse-quartus-dse<unique id> <free local port>:50123 , which creates a secure tunnel that allows your local DSE GUI to communicate with the remote quartus_dse process running in the Kubernetes cluster.

Configure Exploration

Access the Exploration Panel : Select the Exploration panel from the left toolbar.
Set Exploration Name : Enter a descriptive name for your exploration run in the Exploration name field.
Choose Compilation Type : For Compilation type , select Full compilation .
Setup Exploration Points : Expand the Exploration Points section to configure your exploration:

Design exploration : Choose this option to run explorations with different seeds or compilation strategies.
Single compilation : Choose this option if you only want to compile the design once.

You can select different strategies or focus on seed variations. In the Seeds section, enter the number of seeds to run in the Create field.

Optional: Skip Base Compilation : Check Skip base exploration point if you do not need to run the base compile step.
Design File Setup : By default, DSE creates a design archive (* .qar ) file when Create design archive Quartus Prime project is selected. If you already have a .qar file, select Use existing design archive (.qar) option and specify the file path to your existing archive file. These options are available under the Design File Setup menu.
Select Results to Save : In the Select results menu, choose one of the following options from the Select results to save dropdown:

Project archive (.qar) - Returns all generated project archives.
Best Project archive (.qar) - Returns only the best-performing project archive.

Start the Exploration : Click the Start button to begin the exploration.
Confirmation : A message box will appear indicating that the exploration is running. Once it launches successfully, you can click the Dismiss button to close the notification.
Check Status : Right-click on the column headers to enable additional columns and show more information such as Kubernetes Job ID and the Pod name. The Pod is displayed as the hostname. You can use the Job ID with the kubectl command-line tool to get more detailed information about the job status and troubleshoot any issues.
Review Results : Click on Results to review the various design metrics collected, as detailed in Viewing DSE II Results. CSV versions of the reports are automatically downloaded to <project>/dse/dse<run name>/output/ and the QAR files are downloaded to <project>/dse/dse<run name>/ worker_<id>_results/ .

Known Limitations : The Report and Timing Analyzer buttons do not work in QAR mode. The project files are contained within the QAR archive and need to be extracted before you can access the individual project files.

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By following these configuration steps, you can leverage the scalability and costefficiency of Kubernetes to run your FPGA compilation workloads. The combination of proper node pool configuration, service account setup, and container image selection ensures optimal performance while minimizing cloud costs through automatic scaling.

6.5.6.2. Running DSE II Settings Exploration

To run DSE II settings exploration to identify the optimum settings combination for your design goals, follow these steps:

Specify all timing constraints for the design using supported SDC formats or in the Quartus Prime Timing Analyzer.
Start the DSE II tool by clicking Tools ➤ Launch Design Space Explorer II If you have an open project in the Quartus Prime software and launch DSE II, a dialog box appears asking if you want to close the Quartus Prime software. Click Yes .
In the Project page, specify the Quartus Prime project and project revision that you want to explore.
In the Setup page, specify whether you want to perform a local or a remote exploration, and configure any remote computing resources, as Specifying DSE II Computing Resources on page 118 describes.
In the Exploration page, specify your performance, power, and/or routability goals for settings optimization, as DSE II Optimization Parameters (Exploration Page) on page 123 describes.
When the DSE II Project , Setup , and Exploration options are complete, click Start .
When DSE II exploration is complete, review results on the Results page, as Viewing DSE II Results on page 124 describes.

Figure 63. DSE II Project Page Specifies Project Settings

6.5.6.3. Specifying DSE II Computing Resources

You can configure DSE II to take advantage of distributed computing resources to run multi-compilation design explorations more efficiently. In the DSE II GUI, the Setup page allows you to select a DSE II Compilation Type of Local or Remote and supported Remote options.

If you have a laptop or standard computer, you can use the single compilation feature to compile your design on a workstation with higher computing performance and memory capacity.

Alternatively, you can distribute the DSE II iterative compilation workload across different computing resources via one of the following supported remote hosts methods:

Kubernetes -run DSE II in a managed Kubernetes cluster running outside of your network such as on Microsoft Azure* or in a cluster on premise.
LSF -run DSE II in a Load Sharing Facility (LSF) remote farm. The LSF manages, monitors, and analyzes workloads and networks different computers into a single system.
PBSPro -run DSE II in the Altair PBS Professional* (PBSPro) workload manager and scheduler.
Slurm -run DSE II in the free and open-source Slurm job scheduler for Linux and Unix-like kernels.
SSH -run DSE II in Secure Shell (SSH) that allows secure communication between multiple computers and allows access and management of networked systems.
SunGrid (Beta) -run DSE II in Sun Grid Engine (SGE) job scheduling system that manages and distributes computational workloads across a cluster of computers.
Torque -run DSE II in the Adaptive Computing TORQUE job scheduling system that manages and distributes computational workloads across a cluster of computers.

When running on a compute farm, you can direct DSE II to safely exit after submitting all the jobs while the compilations continue to run until completion. Optionally, you can receive an e-mail when the compilations are complete.

If you launch jobs using SSH, the remote host must enable public and private key authentication. For private keys encrypted with a pass phrase, the remote host must run the ssh key agent to decrypt the private key, so the quartus_dse executable can access the key.

6.5.6.3.1. DSE II Setup Page Settings

DSE II provides the following options for configuring your DSE II setup:

Compilation Type Settings

Choose one of the following options for specifying the type of computing resources to use for DSE II compilation processing. DSE II supports parallel processing, allowing you to distribute the multi-compilation workload across distributed remote resources.

Table 28. Compilation Type Settings

| Compilation Type | Description | |--------------------|----------------------------------------------------------------------------------| | Local | Compile from the host machine. | | Remote | The available options are: Kubernetes (beta) LSF PBSPro Slurm SSH SunGrid (Beta) | | Remote | Torque | | Remote | | | Remote | | | Remote | | | Remote | | | Remote | | | Remote | |

Kubernetes Remote Farm Settings

The following settings are available for this option.

Table 29. Kubernetes Remote Farm Settings

| Parameter | Comments | |------------------------|-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | Remote Cluster (Beta) | Specify on if the machine is outside of the Kubernetes cluster and does not share a network. This option is a beta feature in the current release. (1) | | Service Account Name | Specifies the Kubernetes Service Account to use. This account needs to enable permissions verbs create , get , and delete on jobs, pods, pods/log and events. DSE II can create a new Service Account with required permissions if you do not specify one, but this requires that you already have rbac.authorization.k8s.io/v1 API access. (2) | | Create Service Account | Specify on to create a new Kubernetes Service Account with the name quartus-dse on the specified namespace or default namespace. Create quartus-dse role to allow verbs create , get , and delete on jobs, pods, pods/log and events. Bind this role to the quartus-dse service account. | | Full path to kubectl | Specifies the full path to the kubectl executable. The default value is kubectl and assumes is the PATH . | | Kubeconfig File | Specifies the kubeconfig file that you use to login to the Kubernetes cluster. | | Namespace | Specifies the Kubernetes cluster namespace that you are operating in. | | CPU limit | Specifies as decimal value a limit on the number of CPUs that you use. Default value is 2. | | continued... | continued... |

| Parameter | Comments | |---------------------------------------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | CPU Request | Specifies as decimal value the number of CPUs that you require. Default value is 2 . A lower number schedules a job. Once assigned to node, if more CPU resources are available, DSE II uses up to the CPU limit . | | Set environment variables | Accepts a comma separated list of name=value pairs. | | Memory limit | Specifies the memory limit as <value><unit> . Units can be Gi and Mi . Example is 32Gi . | | Memory request | Specifies the memory that you want to request as <value><unit> . Units can be Gi and Mi . Example is 32Gi . If more memory resources are available, DSE II uses up to the Memory limit . | | Pull image before running | Accepts string of Always , IfNotPresent , Never . Default value is ifNotPresent . | | Container image | Specifies the container image with the Quartus Prime software installation. For example: altera/quartuspro-v25.1 | | Only run on a specific node | Specifies the node that you want to run DSE II exploration. | | Select the nodes to run based on node label | Specifies the node label to use the node. For example, mylabel = myteam | | LM_LICENSE_FILE | Specifies the LM_LICENSE_FILE environment setting. Default value is the current local setting. | | Initial Work Directory | Specifies the initial directory for the remote job. For example: /data/user/my_project | | Active Deadline Seconds | Specifies in seconds a time limit the job is allowed to work. The job terminates unless it finishes in the time you specify. Default value is 86400 seconds (24 hours). | | Time to live after finished | Specifies in seconds the time job is allowed to remain in Kubernetes after the job finishes. The TTL control cleans up the job if you specify a time. | | Do not delete pod | Specify on to prevent deletion of the pod from the cluster after it terminates. You can use this option to diagnose problems. | | Keep Manifest Files | Specifies on to retain the Kubernetes manifest .json files that DSE II creates. You can use this option to diagnose problems. | | Additional Remote Settings | Optional field for other Kubernetes remote settings. |

LSF Remote Settings

The following settings are available for this option:

Table 30. LSF Remote Farm Settings

| Parameter | Comments | |------------------------|-------------------------------------------------------------------------------------------------------------------------------------------------------| | Resource Requirements | Specify memory requirements for the machines that run jobs. Example: "rusage[mem=1000] " (including quotes) * Require 1000 MB RAM for submitted jobs. | | Queues | One or more comma-separated queues. | | Quartus Root Directory | Specifies the Quartus Prime software installation location. For example: /altera/25.1/quartus | | LM_LICENSE_FILE | Specifies the LM_LICENSE_FILE environment setting. Default value is the current local setting. | | continued... | continued... |

| Parameter | Comments | |------------------------------|------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | Initial Work Directory | Specifies the initial directory for the remote job. For example: /data/user/my_project | | Environment Variables | Specifies options to control environment propagation and specific environment variables. For example: | | Local to Remote Path Mapping | Specifies the shared directory mapping between the local and remote host. Use format localpath;remote_path . Windows to Linux example: | | Priority | Sets the job priority level from 0 (lowest priority) to 300 (highest priority). Default value is 150. | | Standard Output File | Specifies the file to store standard output. You can include Job ID using %J or Index ID using %I in the directory or filename. | | Error Output File | Specifies the file to store standard error output. You can include Job ID using %J or Index ID using %I in the directory or filename. | | Processor Limits | Specifies the minimum number of processors, and optionally the maximum number of processors for the job. For example, specifying 2 sets a minimum number of two processors. Specifying 3,5 sets a minimum of three and a maximum of five processors. | | Additional remote settings | Specify other settings |

PBSPro Remote Farm Settings

The following settings are available for this option:

Table 31. PBSPro Remote Farm Settings

| Parameter | Comments | |--------------------------------------------|------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | Queues | Specifies the name of the job you that you want to use. | | Priority | Sets the job priority level from -1024 (lowest priority) to 1024 (highest priority). | | Resource, Architecture, Memory Requirement | Specifies the architecture, license, or memory requirements for the job. For example: select=mem=16gb:ncpus=4 | | Email | Specifies a comma separated list of email addresses to receive status emails. | | Additional Arguments to qsub | Optional field for other qsub remote settings. | | Quartus Root Directory | Specifies the Quartus Prime software installation location. For example: /altera/25.1/quartus | | LM_LICENSE_FILE | Specifies the LM_LICENSE_FILE environment setting. Default value is the current local setting. | | Environment Variables | Specifies a comma separated list of environment variables to pass to the job. Enclose values with single or double quote if it includes a comma. For example: a=1 , b='ab" , c=3 . | | Initial Work Directory | Specifies the initial directory for the remote job. For example: /data/user/my_project |

Slurm Remote Farm Settings

The following settings are available for this option:

Table 32. Slurm Remote Farm Settings

| Parameter | Comments | |--------------------------------|-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | Cluster | Specifies a comma separate list of clusters to use for the job. | | Partition | Specifies a comma separate list of partitions to use for the job. | | Memory per Node | Specifies the architecture, license, or memory requirements for the job. For example: select=mem=16gb:ncpus=4 | | CPUs per task | Specifies the maximum number of CPUs to use for each task. | | CPU Sockets per Node | Specifies the maximum number of CPUs to use for each node. | | CPU Cores per Sockets | Specifies the maximum number of CPU cores to use for each socket. | | Priority | Specifies the job priority as numeric value or TOP to specify highest priority possible. Highest value numbers are highest priority. | | Generic resources | Specifies the architecture, license, or memory requirements for the job. For example: select=mem=16gb:ncpus=4 | | Constraint | Specifies node features as required by Slurm administrator. | | Modules | Specifies command separated list of modules. A module configures one or more environment settings. One of the modules must configure the QUARTUS_ROOTDIR and add the Quartus Prime software to the PATH . | | Email | Specifies a comma separated list of email addresses to receive status emails. | | Additional Arguments to sbatch | Optional field for specifying additional options for Slurm. | | Quartus Root Directory | Specifies the Quartus Prime software installation location. For example: /altera/25.1/quartus | | LM_LICENSE_FILE | Specifies the LM_LICENSE_FILE environment setting. Default value is the current local setting. | | Environment Variables | Specifies a comma separated list of environment variables to pass to the job. Enclose values with single or double quote if it includes a comma. For example: a=1 , b='ab" , c=3 . | | Initial Work Directory | Specifies the initial directory for the remote job. For example: /data/user/my_project | | Standard Output File | Specifies the file to store standard output. You can include Job ID using %J or Index ID using %I in the directory or filename. | | Licenses | Specifies the path to any required licenses for the job. |

SunGrid (Beta) Remote Farm Settings

The following settings are available for this option:

Table 33. SunGrid Remote Farm Settings

| Parameter | Comments | |--------------------------------------------|----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | Environment Variables | Specifies a comma separated list of environment variables to pass to the job. For example, DEBUG=1 , SIZE=LARGE . | | Queues | Specifies the name of the job you that you want to use. | | Priority | Sets the job priority level from -1024 (lowest priority) to 1024 (highest priority). | | Resource, Architecture, Memory Requirement | Specifies the architecture, license, or memory requirements for the job. For example: h_vmem=750M, h_cpu=0:45:0 uses a machine with minimum of 750M and runs job no longer than 45 minutes. | | Email | Specifies a comma separated list of email addresses to receive status emails. | | Parallel Processor | Specifies the minimum number of processors, and optionally the maximum number of processors for the job. For example, specifying 4-16 sets a minimum number of four processors and a maximum of 16 processors. | | Additional remote settings | Specify other settings |

Torque Remote Farm Settings

The following settings are available for this option:

Table 34. Torque Remote Farm Settings

| Parameter | Comments | |--------------------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | Environment Variables | Specifies a comma separated list of environment variables to pass to the job. For example, DEBUG=1 , SIZE=LARGE . | | Queues | Specifies the name of the job you that you want to use. | | Priority | Sets the job priority level from -1024 (lowest priority) to 1024 (highest priority). | | Resource, Architecture, Memory Requirement | Specifies the architecture, license, or memory requirements for the job. For example: h_vmem=750M, h_cpu=0:45:0 uses a machine with minimum of 750M and runs job no longer than 45 minutes. | | Email | Specifies a comma separated list of email addresses to receive status emails. | | Additional Arguments to qsub | Specifies any additional arguments. | | Additional remote settings | Specify other settings |

6.5.6.4. DSE II Optimization Parameters (Exploration Page)

DSE II provides a collection of predefined exploration spaces on the Exploration page that allow you to target settings optimization for your performance, power, and routability goals. To target all areas of optimization at once, turn on All Compilation Strategies .

Additionally, you can define a set of compilation seeds in the Seeds field. The number of explorations points is the number of seeds multiplied by the number of exploration modes.

Note: The availability of predefined spaces depends on the device family that the design targets.

Figure 64. DSE II Exploration Page Specifies Optimization Goals

Related Information

Exploration Page (Design Space Explorer II) In Quartus Prime Help

6.5.6.5. Viewing DSE II Results

DSE II compares the compilation results to determine the best Quartus Prime software settings for the design. The Report page displays a categorized summary of results.

During settings exploration, DSE II selects the best, worst-case slack value from among all timing corners across all exploration points. If you want to optimize for worst-case setup slack or hold slack, specify related timing constraints in the Quartus Prime software.

Timing Closure and Optimization

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DSE II Reports

DSE II has reporting tools that help you quickly determine important design metrics, such as worse-case slack, across all exploration points.

Figure 65. DSE II Results Page Reports Best Project Settings

Saving DSE II Results

By default, DSE II saves all the compilation data. You can save disk space by limiting the type of files that you want to save after a compilation finishes. These settings are in the Exploration page, Results section.

DSE II provides a performance data report for all points it explores and saves the information in a project-name.dse.rpt file in the project directory. DSE II archives the settings of the exploration points in Quartus Prime Archive Files ( .qar ).

Related Information

Report Page (Design Space Explorer II) In Quartus Prime Help

6.5.7. Aggregating and Comparing Compilation Results with Exploration Dashboard

You can use the Exploration Dashboard ( quartus_edw ) in the Quartus Prime Pro Edition software to aggregate and compare compilation results between multiple Quartus Prime projects or sets of compilation results.

The Exploration Dashboard allows you to easily coordinate and view the compilation and timing results from multiple projects running on separate instances of the Quartus Prime software. For example, you can analyze and compare versions of the same design that differ by RTL changes, or perhaps only differ by project settings. The Exploration Dashboard provides the power and flexibility to support multi-project analysis for a diverse range of work flows and analysis tasks. (3)

The Exploration Dashboard interfaces with multiple Quartus Prime projects simultaneously in a single workspace to help you close timing by aggregating and comparing results from multiple seeds or multiple versions of your design.

Aggregating compilation results-Exploration Dashboard reports what is common in all the compilation results for a version of your design.
Comparing compilation results-Exploration Dashboard reports the differences between different versions of your design.

Figure 66. Exploration Dashboard Use Model

Use the Exploration Dashboard to quickly compare the aggregated compilation results from multiple projects or sets of results to determine the best implementation and impact of changes. The Exploration Dashboard supports use cases like the following:

Identify all of the failing timing paths, in all seeds, after completing a seed sweep.
Determine whether the average fMAX improves after RTL optimization.
Track a scorecard of design performance as the project proceeds towards completion.
Compare compilation results across Quartus Prime software versions.

(3) Exploration Dashboard is pre-production status in Quartus Prime Pro Edition v.24.1, and supports analysis of compilation results generated with Quartus Prime Pro Edition software version 21.1 through version 24.1. Other versions may function but are not verified.

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For example, you can use Exploration Dashboard to report timing on all of your various compilation seeds, and view the path from all seeds in a single report view. Exploration dashboard allows you to compare historical results against new data. This allows you to track improvement over time on critical design metrics, such as Fmax and power.

The Exploration Dashboard is currently a Tcl-based API that employs an objectproperty model to aggregate and compare objects across multiple compilation databases that store results from your different compilations.

For a step-by-step tutorial using the Exploration Dashboard GUI and an example design, refer to AN 1006: Multi-Project Analysis with Exploration Dashboard .

Related Information

AN 1006: Multi-Project Analysis with Exploration Dashboard

6.5.7.1. Aggregation Use Case

Aggregation helps you see all the results from your compiles in one workspace. For example, you can use aggregation to determine whether particular timing failures occur commonly or occasionally. Focusing your optimization work on failures that occur commonly has higher impact than focusing on failures that occur occasionally.

Aggregation is helpful because of the stochastic nature of the Quartus Prime Compiler. This stochastic nature means that the Compiler employs random heuristics in some decision-making processes. These heuristics perform well on average, but certain sequences can have unusually good or bad outcomes.

Often, the seed value that governs these random decisions is a project input that you can change to explore for a given design without changing the design. Because these random decisions are sensitive to specific netlist topologies, constraints, and design file content ordering, various different project element changes can result in the 'seed effect' without any meaningful change to the design. Therefore, any given compilation result is not a precise measure of the quality of the design. While an individual compilation is the only source of programming files, you can run multiple compilations with different seed values in parallel, with each project containing its own seed value, to obtain the best results.

When performing aggregation, you are usually looking for common trends and limitations among the results. Since the compiles that you analyze with aggregation are different compilations of the exact same design, any random differences between the projects should cancel out, and any fundamental issues should recur.

Nevertheless, there can be certain projects and seeds that are outliers. You can then compare to the aggregate of the remaining projects. You can use this method to either explain unusually good or unusually bad results in the outlier projects in comparison with typical results.

6.5.7.2. Comparison Use Case

Comparison of compilation results can be helpful in determining the set of conditions or properties that are different between two sets of compilation results. For example, you can compare the differences between sets of compilation results that you

Note:

generate at different times from the similar source files. From the perspective of the Quartus Prime Compiler, such projects are technically different. You can also export Exploration Dashboard results for further mathematical analysis in other tools.

Comparison allows you to determine whether certain design changes result in the compilation results that you want. You can compare the aggregate-before results to the aggregate-after results. Exploration Dashboard can analyze multiple seeds of each version of the design together first, and then compare the common results across versions of the design. In comparison use cases, the goal is to decide if the design changes made the design better or worse overall.

Figure 67. Visualization of Fmax Aggregation and Comparison Analysis

Visualization of Fmax Aggregation and Comparison Analysis illustrates an example of aggregation followed by comparison. In this example use-case:

The designer first compiles 'Version1' of their design four times through four different seed values.
The designer next makes some changes to the design for 'Version2'.
The designer compiles 'Version2' four times.

To determine if the 'Version2' design changes improve the design performance overall, the designer can follow these steps:

Aggregate the Fmax results from each version by taking the geometric mean (geomean) of the Fmax across seeds.
Compare the geomean values and conclude that 'Version2' has an expected +12% improvement to Fmax compared to "Version1".

The Exploration Dashboard is instrumental in this comparison because no other individual seed versus seed comparison can show this result. Comparison of the individual compilation results can lead to a different conclusion.

6.5.7.3. Exploration Dashboard Object-Property Model

The Exploration Dashboard operates on an object-property model that defines the following roles, responsibilities, and properties of the major object types:

Figure 68. Visualization of the Objects in the Exploration Dashboard Environment

Table 35. Exploration Dashboard Terms

| Term | Description | |-------------------|----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | Workspace | The workspace is a single container for all other Exploration Dashboard objects, reports, and results. The workspace governs all persistence, namespace, and portability requirements of Exploration Dashboard flows. The properties of the workspace govern global settings and behaviors that do not pertain to any individual group or project. | | Project Handle | Corresponds 1:1 with a Compiler database and the necessary configurations to access it. The purpose of the Project Handle is to launch a new Quartus Prime software process and send commands and data back and forth over a communication channel. | | Project Group | Provides a method to refer to and work with an arbitrary subset of the Project Handles that are loaded in the workspace. Each project group can contain any number of projects. Each project ID present in a group's projects property corresponds to a project object that is guaranteed to have that group's ID present in its groups property. | | Compiler database | The database that preserves the compilation results from one previous run of the Compiler. |

Note:

For the complete Exploration Dashboard Tcl API, refer to ::quartus::qed in the Quartus Prime Pro Edition User Guide: Scripting .

Related Information

::quartus::qed, Quartus Prime Pro Edition User Guide: Scripting

6.5.7.3.1. Base Exploration Dashboard Properties

This section describes the Exploration Dashboard objects and properties that you can configure and use for aggregating and comparing compilation results in the Exploration Dashboard.

The following base objects and properties are common across all objects and accessible using set_property and get_property .

Table 36. Base Exploration Dashboard Objects and Properties

| Property Name | Property Type | Property Description | Default Value | Read- Only | Comments | |-----------------|----------------------------------------|---------------------------------------|--------------------------------------------------------------------|--------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------| | type | Either: project , group , or workspace | Type of the object | N/A (must be specified) | True | | | id | string | Identifier associated with the object | Automatically generated based on the type (for example, project_1) | | All IDs must be globally unique within a Workspace. Constructing an object causes an error if you specify an ID that is already allocated to another object. | | user_data | string | Arbitrary data you want to store | N/A | | You can optionally access user_data using methods described below. |

::qed::set_user_data and ::qed::get_user_data Specializations

In addition to set_property and get_property user_data also supports the set_user_data and get_user_data specializations for access. These specializations allow for more convenience when using the recommended (but unrequired) method of managing user_data like a Tcl dictionary.

For example, you can use the qed::get_property command to retrieve the value of the user_data property. You could then treat it as a dict and use dict get or dict set commands to manipulate the value, and optionally store any changes with the qed::set_property command .

The following shows equivalent examples using the two methods discussed:

::qed::get_user_data <object> -key <key> is equivalent to: set tmp [::qed::get_property <object> -property user_data] dict get $tmp <key> Similarly, ::qed::set_user_data <object> -key <key> -value <value> is equivalent to: set tmp [qed::get_property <object> -property user_data] dict set tmp <key> <value> ::qed::set_property <object> -property user_data -value $tmp

6.5.7.3.2. Project Handle Properties

The main purpose of Project Handle objects is to configure, launch, and manage a connection to a single project compilation database.

Table 37. Project Handle Properties

| Property Name | Property Type | Property Description | Default Value | Read- Only | Comments | |-------------------|----------------------------------------------|--------------------------------------------------------------------------------------------------------------------------|-----------------|--------------|------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | qpf_path | String (must be a valid path to a .qpf file) | Project file corresponding to the project and database to open and interface with | N/A | | | | project_directory | String | Directory name of the project file you interface with | N/A | True | Derived from the qpf_path value | | project_name | String | Base name of the project file being interfaced with | N/A | True | Derived from the qpf_path value | | revision_name | String | Revision name to specify | N/A | | If unspecified, Exploration Dashboard assumes that the revision name is the default revision name for the project. This updates when you set the qpf_path property. | | connection_status | Enum | Reflects the state of the communication channel after the launch_connection or disconnect methods complete successfully. | CLOSED | True | Can be one of STARTING , READY , CLOSED , RUNNING , TIMEOUT , or ANY | | groups | List of Project Group IDs | Set of groups to which the project belongs. | N/A | | A project can be in any number of groups. Each group ID present in a project's groups property corresponds to a group object that is guaranteed to have that project's ID present in its projects property . Project groups properties are kept consistent with group projects properties). Note: All projects must be in at least one group. Running sanitize_workspace creates and places all ungrouped projects into a default group. | | db_state | Enum | Indicates whether the project's compilation database is loaded or not | Unloaded | True | Can be one of unloaded or loaded . |

6.5.7.3.3. Project Group Objects and Properties

The main purpose of a Project Group is to provide a convenient way to refer to and work with an arbitrary subset of the Project Handles that are loaded in the workspace.

Table 38. Project Group Objects and Properties

| Property Name | Property Type | Property Description | Default Value | Read-Only | Comments | |-----------------|---------------------------|----------------------------------------|-----------------|-------------|----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | projects | List of Project Group IDs | Set of projects belonging to the group | N/A | | A group can contain any number of projects. Each project ID present in a group's projects property corresponds to a project object that is guaranteed to have that group's ID present in its groups property (group projects properties are kept consistent with project groups properties). |

6.5.7.3.4. Workspace Objects and Properties

The main purpose of a workspace is to act as a single container for all other Exploration Dashboard objects, reports, and results. The workspace also handles persistence, namespace, and portability for Exploration Dashboard flows.

Table 39. Workspace Objects and Properties

| Property Name | Property Type | Property Description | Default Value | Read- Only | Comments | |-------------------|-----------------|---------------------------------------------------------------------------------------------------------------|-----------------|--------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | default_gro up_id | Valid Group ID | ID of the default group that sanitize_workspace uses to ensure all projects are placed in at least one group. | default_group_1 | | The default group ID is reserved upon workspace construction, but the default group itself isn't constructed until required by sanitize_workspace . You can modify this property to designate a specific group as the default group for un- grouped projects. |

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6.5.7.4. Starting the Exploration Dashboard

To start the Exploration Dashboard using the Tcl API, follow these steps:

To start the Exploration Dashboard, perform one of the following:

To start Exploration Dashboard in shell mode with the Quartus Prime Pro Edition software, type the following command:
To start the Exploration Dashboard in GUI mode with the Quartus Prime Pro Edition software, type the following command:

To create a group in the workspace, type the following command and specify a group name:
To add project objects to the workspace for exploration, type the following command to specify the type of object (project), a unique ID (for example based on the seednumber ), and the path to the .qpf file:

quartus_ed -s

quartus_edw

::qed::create_object -type group <group name>

::qed::create_object -type <project|group> -qpf_path <qpf path> <id>

The following commands show examples of this syntax:

::qed::create_object -type project -qpf_path ../seed2/top.qpf seed2

The Exploration Dashboard creates the id if unspecified. Repeat this step for each project object that you want to add to the workspace for aggregation and comparison.

To perform workspace legality checks and modify the state of your workspace to make it legal, type the following command:

qed::sanitize_workspace

The Exploration Dashboard is ready to receive other commands to analyze, aggregate, and compare the compilations results from the project objects in the workspace. For the complete Exploration Dashboard Tcl API, search for ::quartus::qed in the Quartus Prime Pro Edition User Guide: Scripting .

For a step-by-step tutorial using the Exploration Dashboard GUI and an example design, refer to AN 1006: Multi-Project Analysis with Exploration Dashboard .

Related Information

AN 1006: Multi-Project Analysis with Exploration Dashboard
::quartus::qed, Quartus Prime Pro Edition User Guide: Scripting

6.5.8. I/O Timing Optimization Techniques

This stage of design optimization focuses on I/O timing, including setup delay (tSU), hold time (tH), and clock-to-output (tCO) parameters.

Before proceeding with I/O timing optimization, ensure that:

Note:

The design's assignments follow the suggestions in the Initial Compilation: Required Settings section of the Design Optimization Overview chapter.
Resource utilization is satisfactory.

Complete this stage before proceeding to the register-to-register timing optimization stage. Changes to the I/O paths affect the internal register-to-register timing.

Summary of Techniques for Improving Setup and Clock-to-Output Times

The table lists the recommended order of techniques to reduce tSU and tCO times. Reducing tSU times increases hold (tH) times.

Note:

Verify which options are available to each device family

Table 40. Improving Setup and Clock-to-Output Times

| Order | Technique | Affects t SU | Affects t CO | |---------|----------------------------------------------------------------------------------------------------------------------------------------------------------------------|----------------|----------------| | 1 | Verify of that the appropriate constraints are set for the failing I/Os (refer to Initial Compilation: Required Settings ) | Yes | Yes | | 2 | Use timing-driven compilation for I/O (refer to Fast Input, Output, and Output Enable Registers ) | Yes | Yes | | 3 | Use fast input register (refer to Programmable Delays ) | Yes | N/A | | 4 | Use fast output register, fast output enable register, and fast OCT register (refer to Programmable Delays ) | N/A | Yes | | 5 | Decrease the value of Input Delay from Pin to Input Register or set Decrease Input Delay to Input Register = ON | Yes | N/A | | 6 | Decrease the value of Input Delay from Pin to Internal Cells or set Decrease Input Delay to Internal Cells = ON | Yes | N/A | | 7 | Decrease the value of Delay from Output Register to Output Pin or set Increase Delay to Output Pin = OFF (refer to Fast Input, Output, and Output Enable Registers ) | N/A | Yes | | 8 | Increase the value of Input Delay from Dual-Purpose Clock Pin to Fan-Out Destinations (refer to Fast Input, Output, and Output Enable Registers ) | Yes | N/A | | 9 | Use PLLs to shift clock edges | Yes | Yes | | 10 | Increase the value of Delay to output enable pin or set Increase delay to output enable pin (refer to Use PLLs to Shift Clock Edges ) | N/A | Yes |

I/O Timing Constraints on page 135

Optimize IOC Register Placement for Timing Logic Option on page 135

Fast Input, Output, and Output Enable Registers on page 135

Programmable Delays on page 136

Use PLLs to Shift Clock Edges on page 137

Use Fast Regional Clock Networks and Regional Clocks Networks on page 137

Spine Clock Limitations on page 137

Related Information

Initial Compiler Settings on page 8

Note:

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6.5.8.1. I/O Timing Constraints

Timing Analyzer supports the Synopsys* Design Constraints (SDC) format for constraining your design. When using the Timing Analyzer for timing analysis, use the set_input_delay constraint to specify the data arrival time at an input port with respect to a given clock. For output ports, use the set_output_delay command to specify the data arrival time at an output port's receiver with respect to a given clock. You can use the report_timing Tcl command to generate the I/O timing reports.

The I/O paths that do not meet the required timing performance are reported as having negative slack and are highlighted in red in the Timing Analyzer Report pane. In cases where you do not apply an explicit I/O timing constraint to an I/O pin, the Quartus Prime timing analysis software still reports the Actual number, which is the timing number that must be met for that timing parameter when the device runs in your system.

Related Information

Quartus Prime Pro Edition User Guide: Timing Analyzer

6.5.8.2. Optimize IOC Register Placement for Timing Logic Option

This option moves registers into I/O elements to meet tSU or tCO assignments, duplicating the register if necessary (as in the case in which a register fans out to multiple output locations). This option is turned on by default and is a global setting.

The Optimize IOC Register Placement for Timing logic option affects only pins that have a tSU or tCO requirement. Using the I/O register is possible only if the register directly feeds a pin or is fed directly by a pin. Therefore, this logic option does not affect registers with any of the following characteristics:

Note: To optimize registers with these characteristics, use other Quartus Prime Fitter optimizations.

Have combinational logic between the register and the pin
Are part of a carry chain
Have an overriding location assignment
Use the asynchronous load port and the value is not 1 (in device families where the port is available)

Related Information

Optimize IOC Register Placement for Timing Logic Option Help Topic In Quartus Prime Help

6.5.8.3. Fast Input, Output, and Output Enable Registers

You can place individual registers in I/O cells manually by making fast I/O assignments with the Assignment Editor. By default, with correct timing assignments, the Fitter places the I/O registers in the correct I/O cell or in the core, to meet the performance requirement.

If the fast I/O setting is on, the register is always placed in the I/O element. If the fast I/O setting is off, the register is never placed in the I/O element. This is true even if the Optimize IOC Register Placement for Timing option is turned on. If there is

no fast I/O assignment, the Quartus Prime software determines whether to place registers in I/O elements if the Optimize IOC Register Placement for Timing option is turned on.

You can also use the four fast I/O options ( Fast Input Register , Fast Output Register , Fast Output Enable Register , and Fast OCT Register ) to override the location of a register that is in a Logic Lock region and force it into an I/O cell. If you apply this assignment to a register that feeds multiple pins, the Fitter duplicates the register and places it in all relevant I/O elements.

For more information about the Fast Input Register option, Fast Output Register option, Fast Output Enable Register option, and Fast OCT (on-chip termination) Register option, refer to Quartus Prime Help.

Related Information

Fast Input Register logic option Help Topic
Fast Output Register logic option
Fast Output Enable Register logic option
Fast OCT Register logic option

6.5.8.4. Programmable Delays

You can use various programmable delay options to minimize the tSU and tCO times. Programmable delays are advanced options that you use only after you compile a project, check the I/O timing, and determine that the timing is unsatisfactory.

The Quartus Prime software automatically adjusts the applicable programmable delays to help meet timing requirements. For detailed information about the effect of these options, refer to the device family handbook or data sheet.

After you have made a programmable delay assignment and compiled the design, you can view the implemented delay values for every delay chain and every I/O pin in the Delay Chain Summary section of the Compilation Report.

You can assign programmable delay options to supported nodes with the Assignment Editor. You can also view and modify the delay chain setting for the target device with the Chip Planner and Resource Property Editor. When you use the Resource Property Editor to make changes after performing a full compilation, recompiling the entire design is not necessary; you can save changes directly to the netlist. Because these changes are made directly to the netlist, the changes are not made again automatically when you recompile the design. The change management features allow you to reapply the changes on subsequent compilations.

Although the programmable delays in newer devices are user-controllable, Altera recommends their use for advanced users only. However, the Quartus Prime software might use the programmable delays internally during the Fitter phase.

For details about the programmable delay logic options available for Altera devices, refer to the following Quartus Prime Help topics:

Related Information

Input Delay from Pin to Input Register logic option Help Topic
Input Delay from Pin to Internal Cells logic option Help Topic

UG-20133 | 2026.01.07

Output Enable Pin Delay logic option Help Topic
Delay from Output Register to Output Pin logic option Help Topic
Input Delay from Dual-Purpose Clock Pin to Fan-Out Destinations logic option Help Topic

In Quartus Prime Help

6.5.8.5. Use PLLs to Shift Clock Edges

Using a PLL typically improves I/O timing automatically. If the timing requirements are still not met, most devices allow the PLL output to be phase shifted to change the I/O timing. Shifting the clock backwards gives a better tH at the expense of tSU, while shifting it forward gives a better tSU at the expense of tH. You can use this technique only in devices that offer PLLs with the phase shift option.

Figure 69. Shift Clock Edges Forward to Improve tSU at the Expense of tH

You can achieve the same type of effect in certain devices by using the programmable delay called Input Delay from Dual Purpose Clock Pin to Fan-Out Destinations .

6.5.8.6. Use Fast Regional Clock Networks and Regional Clocks Networks

Regional clocks provide the lowest clock delay and skew for logic contained in a single quadrant. In general, fast regional clocks have less delay to I/O elements than regional and global clocks, and are used for high fan-out control signals. Placing clocks on these low-skew and low-delay clock nets provides better tCO performance.

Altera devices have a variety of hierarchical clock structures. These include dedicated global clock networks, regional clock networks, fast regional clock networks, and periphery clock networks. The available resources differ between the various Altera device families.

For the number of clocking resources available in your target device, refer to the appropriate device handbook.

6.5.8.7. Spine Clock Limitations

In Arria 10 and Cyclone 10 GX designs with high clock routing demands, limitations in the Quartus Prime software can cause spine clock errors. These limits do not apply to Stratix 10 or Agilex FPGA portfolio devices.

These errors can occur with designs using multiple memory interfaces and high-speed serial interface (HSSI) channels, especially with PMA Direct mode.

Global clock networks, regional clock networks, and periphery clock networks have an additional level of clock hierarchy known as spine clocks. Spine clocks drive the final row and column clocks to their registers; thus, the clock to every register in the chip is reached through spine clocks. Spine clocks are not directly user controllable.

To reduce these spine clock errors, constrain your design to use your regional clock resources better:

If your design does not use Logic Lock regions, or if the Logic Lock regions are not aligned to your clock region boundaries, create additional Logic Lock regions and further constrain your logic.
To ensure that the global promotion process uses the correct locations, assign specific pins to the I/Os using these periphery features.
By default, some Altera IP functions apply a global signal assignment with a value of dual-regional clock. If you constrain your logic to a regional clock region and set the global signal assignment to Regional instead of Dual-Regional , you can reduce clock resource contention.

Related Information

Viewing Available Clock Networks in Chip Planner on page 171

6.5.9. Register-to-Register Timing Optimization Techniques

The next stage of design optimization seeks to improve register-to-register (fMAX) timing. The following sections provide available options if the design does not meet timing requirements after compilation.

Coding style affects the performance of a design to a greater extent than other changes in settings. Always evaluate the code and make sure to use synchronous design practices.

Note: In the context of the Timing Analyzer, register-to-register timing optimization is the same as maximizing the slack on the clock domains in a design. The techniques in this section can improve the slack on different timing paths in the design.

Before performing design optimizations, understand the structure of the design as well as the effects of techniques in different types of logic. Techniques that do not benefit the logic structure can decrease performance.

Related Information

Quartus Prime Pro Edition User Guide: Design Recommendations
Design Assistant Rules List

6.5.9.1. Optimize Source Code

In many cases, optimizing the design's source code can have a very significant effect on your design performance. In fact, optimizing your source code is typically the most effective technique for improving the quality of your results and is often a better choice than using Logic Lock or location assignments.

You can use the Design Assistant to help identify areas in the design for timing optimization. Be aware of the number of logic levels needed to implement your logic while you are coding. Too many levels of logic between registers might result in critical paths failing timing. Try restructuring the design to use pipelining or more efficient coding techniques. Also, try limiting high fan-out signals in the source code. When possible, duplicate and pipeline control signals. Make sure the duplicate registers are protected by a preserve attribute, to avoid merging during synthesis.

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If the critical path in your design involves memory or DSP functions, check whether you have code blocks in your design that describe memory or functions that are not being inferred and placed in dedicated logic. You might be able to modify your source code to cause these functions to be placed into high-performance dedicated memory or resources in the target device. When using RAM/DSP blocks, enable the optional input and output registers.

Ensure that your state machines are recognized as state machine logic and optimized appropriately in your synthesis tool. State machines that are recognized are generally optimized better than if the synthesis tool treats them as generic logic. In the Quartus Prime software, you can check the State Machine report under Analysis & Synthesis in the Compilation Report. This report provides details, including state encoding for each state machine that was recognized during compilation. If your state machine is not recognized, you might have to change your source code to enable it to be recognized.

Related Information

AN 584: Timing Closure Methodology for Advanced FPGA Designs

6.5.9.2. Improving Register-to-Register Timing

The choice of options and settings to improve the timing margin (slack) or to improve register-to-register timing depends on the failing paths in the design. To achieve the results that best approximate your performance requirements, apply the following techniques and compile the design after each step:

Ensure that your timing assignments are complete and correct. For details, refer to the Initial Compilation: Required Settings section in the Design Optimization Overview chapter.
Review all Design Assistant rule violations and other warning messages from your initial compilation and check for ignored timing assignments. Design Assistant helps to identify and correct any invalid timing constraints.
Apply netlist synthesis optimization options.
To optimize for speed, apply the following synthesis options:

Optimize Synthesis for Speed, Not Area
Flatten the Hierarchy During Synthesis
Set the Synthesis Effort to High
Prevent Shift Register Inference
Use Other Synthesis Options Available in Your Synthesis Tool

To optimize for performance, turn on Advanced Physical Optimization
Try different Fitter seeds. If only a small number of paths are failing by small negative slack, then you can try with a different seed to find a fit that meets constraints in the Fitter seed noise.

Note: Omit this step if a large number of critical paths are failing, or if the paths are failing by a long margin.

To control placement, make Logic Lock assignments.
Modify your design source code to fix areas of the design that are still failing timing requirements by significant amounts.
Make location assignments, or as a last resort, perform manual placement by back-annotating the design.

You can use Design Space Explorer II (DSE) to automate the process of running different compilations with different settings.

If these techniques do not achieve performance requirements, additional design source code modifications might be required.

Related Information

Optimize Settings with Design Space Explorer II on page 107
Initial Compiler Settings on page 8

6.5.9.3. Physical Synthesis Optimizations

The Quartus Prime software offers physical synthesis optimizations that can help improve design performance regardless of the synthesis tool. You can apply physical synthesis optimizations both during synthesis and during fitting.

During the synthesis stage of the Quartus Prime compilation, physical synthesis optimizations operate either on the output from another EDA synthesis tool, or as an intermediate step in synthesis. These optimizations modify the synthesis netlist to improve either area or speed, depending on the technique and effort level you select.

To view and modify the synthesis netlist optimization options, click Assignments ➤ Settings ➤ Compiler Settings ➤ Advanced Settings (Fitter) .

If you use a third-party EDA synthesis tool and want to determine if the Quartus Prime software can remap the circuit to improve performance, use the Perform WYSIWYG Primitive Resynthesis option. This option directs the Quartus Prime software to unmap the LEs in an atom netlist to logic gates, and then map the gates back to Alteraspecific primitives. Altera-specific primitives enable the Fitter to remap the circuits using architecture-specific techniques.

The Quartus Prime Compiler optimizes the design to achieve maximum speed performance, minimum area usage, or balances high performance and minimal logic usage, according to the setting of the Optimization Technique option. Set this option to Speed or Balanced .

During the Fitter stage of the Quartus Prime compilation, physical synthesis optimizations make placement-specific changes to the netlist that improve speed performance results for the specific Altera device.

Related Information

Perform WYSIWYG Primitive Resynthesis Logic Option Help Topic
Optimization Technique Logic Option Help Topic

In Quartus Prime Help

6.5.9.4. Set Power Optimization During Synthesis to Normal Compilation

The default value for the Compiler's Power Optimization During Synthesis setting is Normal Compilation . However, if Power Optimization During Synthesis is set to Extra Effort , design performance can be affected. To avoid any possible effect, click Assignments ➤ Settings ➤ Compiler Settings ➤ Power Optimization During Synthesis to confirm the Normal Compilation setting value.

Related Information

Power Optimization

6.5.9.5. Optimize Synthesis for Performance, Not Area

Design performance varies depending on coding style, synthesis tool used, and options you specify when synthesizing. Change your synthesis options if a large number of paths are failing, or if specific paths fail by a great margin and have many levels of logic.

Identify the default optimization targets of your Synthesis tool, and set your device and timing constraints accordingly. For example, if you do not specify a target frequency, some synthesis tools optimize for area.

Optimize for performance by specifying the High Performance Effort , High Performance with Maximum Placement Effort , High Performance with Aggressive Power Effort , Superior Performance , or Superior Performance with Maximum Placement Effort optimization mode.

Related Information

Optimization Technique Logic Option Help Topic In Quartus Prime Help

6.5.9.6. Flatten the Hierarchy During Synthesis

Synthesis tools typically let you preserve hierarchical boundaries, which can be useful for verification or other purposes. However, the best optimization results generally occur when the synthesis tool optimizes across hierarchical boundaries, because doing so often allows the synthesis tool to perform the most logic minimization, which can improve performance. Whenever possible, flatten your design hierarchy to achieve the best results.

6.5.9.7. Set the Synthesis Effort to High

Synthesis tools offer varying synthesis effort levels to trade off compilation time with synthesis results. Set the synthesis effort to high to achieve best results when applicable.

6.5.9.8. Change Adder Tree Styles

Structuring adder trees appropriately to match your targeted Altera FPGA device architecture and application can provide significant improvements in your design's efficiency and performance.

A good example of an application using a large adder tree is a finite impulse response (FIR) correlator. Using a pipelined binary or ternary adder tree appropriately can greatly improve the quality of your results for such applications.

Because ALMs can implement functions of up to six inputs, you can improve the performance of certain designs by using a compressor implementation for adder trees, rather than the default balanced binary tree implementation. The expected downside tradeoff of the compressor implementation is the use of more ALM logic resources. However, the overall logic depth is lower, and the final timing characteristics improve.

Figure 70. Balanced Binary Versus Compressor Style Adder Trees

For designs that may benefit, you can apply the Use Compressor Implementation ( USE_COMPRESSOR_IMPLEMENTATION ) global, entity, or instance assignment to specify whether the Compiler synthesizes adder trees as balanced binary trees, or as compressor style trees.

You can specify this assignment in the Assignment Editor, or with the following assignment in the .qsf .

set_instance_assignment -name USE_COMPRESSOR_IMPLEMENTATION ALWAYS -to <foo>

You can specify this assignment as either a global assignment, entity assignment, or instance assignment. You can alternatively use this assignment with altera_attribute to create instance assignments as well. For example:

(* altera_attribute = "-name USE_COMPRESSOR_IMPLEMENTATION ALWAYS" *) module foo(a, b, c, o);

The following options are available for this assignment:

Table 41. Use Compressor Implementation Assignment Options

| Option | Description | |----------|-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | Always | The Compiler always synthesizes all adder trees with this assignment as compressor style trees. There is a limit of at least 2 non-constant operands before this triggers (otherwise synthesis implements a binary add or a pure-LUT implementation depending on size). | | Never | The Compiler never synthesizes the assigned adder tree as a compressor. The Compiler synthesizes the adder as either a balanced binary tree, or if sufficiently small, in pure LUTs. | | Auto | This setting currently behaves the same as the Never setting. The Compiler synthesizes the adder as either a balanced binary tree, or if sufficiently small, in pure LUTs. This setting never uses compressor style adder trees. |

6.5.9.9. Duplicate Registers for Fan-Out Control

Often, timing failures can occur due to the influence of signals that are not directly involved in the failing transfers. This condition tends to manifest when off-critical nets, most commonly with a high fan-out, span a large distance and consequentially, warp the optimization of other paths around them.

Duplicating the sources of these types of globally-influential signals can help to disperse them across many hops, or even across many clock cycles, and focus more on local transfers.

For example, by duplicating a high fan-out signal in the form of a tree of registers, you can disperse the signal over several clock cycles. As the signal progresses down the tree, it progressively feeds more into local copies of the original registers, such that any individual register's destinations are well-localized and its influence on register optimization is minimal. The key to this optimization is to determine how to assign the original signal's fan-outs among the duplicates. If any individual register requires driving a large distance, the benefit of the tree can be removed.

You can manually create a register tree and group the endpoints in the RTL by leveraging your system-level knowledge about how best to disperse the signal throughout your design, but it can be time consuming and have a widespread impact. For more information about manually creating a register tree, refer to Manual Register Duplication on page 143.

You can create register trees automatically in one of the following ways.

Estimated Physical Proximity
Hierarchical Proximity

Each method has its own methodology to determine the number of duplicates to create and how to assign the fan-outs between the duplicates.

6.5.9.9.1. Manual Register Duplication

Synthesis tools support options or attributes that specify the maximum fan-out of a register. When using Quartus Prime synthesis, you can set the Maximum Fan-Out logic option in the Assignment Editor to control the number of destinations for a node

so that the fan-out count does not exceed a specified value. You can also use the maxfan attribute in your HDL code. The software duplicates the node as required to achieve the specified maximum fan-out.

Logic duplication using Maximum Fan-Out assignments normally increases resource utilization, and can potentially increase compilation time, depending on the placement and the total resource usage within the selected device.

The improvement in timing performance that results from Maximum Fan-Out assignments is design-specific. This is because when you use the Maximum Fan-Out assignment, the Fitter duplicates the source logic to limit the fan-out, but does not control the destinations that each of the duplicated sources drive. Therefore, it is possible for duplicated source logic to be driving logic located all around the device. To avoid this situation, you can use the Manual Logic Duplication logic option.

If you are using Maximum Fan-Out assignments, benchmark your design with and without these assignments to evaluate whether they give the expected improvement in timing performance. Use the assignments only when you get improved results.

You can manually duplicate registers in the Quartus Prime software regardless of the synthesis tool used. To duplicate a register, apply the Manual Logic Duplication logic option to the register with the Assignment Editor.

Some Fitter optimizations may cause a small violation to the Maximum Fan-Out assignments to improve timing.

Note:

6.5.9.9.2. Automatic Register Duplication: Estimated Physical Proximity

The DUPLICATE_REGISTER assignment helps in leveraging estimated physical proximity information to guide the creation of duplicates and their fan-out assignments.

set_instance_assignment -name DUPLICATE_REGISTER -to <register_name> <num_duplicates>

where,

register_name is the register to duplicate. To create a register tree from a chain, create a unique assignment for each register in the chain. DUPLICATE_REGISTER assignments are processed in the appropriate order if they apply to registers that drive each other in a chain.
num_duplicates is the number of duplicates of the register to create (including the original). If the original signal has M fan-out, the average fan-outs of the duplicates are M/N but any individual duplicate may have more or fewer, at the discretion of the algorithm.

The DUPLICATE_REGISTER assignment is processed during the Fitter stage. It is necessary to create the duplicates and assign fan-outs between the duplicates based on early estimates of physical proximity to maximize the amount of time spent optimizing the design post-duplication. However, this renders fine-grained assignment decisions imprecise. The DUPLICATE_REGISTER assignment is best used when the number of duplicates is small (under 100) and the groups created are coarse-grained enough to allow for flexibility during optimization after the duplicates are created.

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The Fitter Duplication Summary panel of the Fit report details the DUPLICATE_REGISTER assignments picked up by Quartus Prime Pro Edition. It also summarizes any registered signal with greater than 1000 fan-outs, as they could be reasonable candidates for DUPLICATE_REGISTER assignments in future.

Important:

Setting PHYSICAL_SYNTHESIS to OFF disables DUPLICATE_REGISTER .
Unlike other physical synthesis optimizations, the DUPLICATE_REGISTER assignment does allow duplication of registers that feed asynchronous clears and registers having location assignments.
The DUPLICATE_REGISTER assignment does not process registers that have any of the following conditions:
Registers drive global signals or clock signals.
Registers have timing assignments or exceptions applied to them.
Registers have a preserve attribute or a PRESERVE_REGISTER assignment.
Registers are marked as don't touch .
Registers drive or are driven by other partitions.

6.5.9.9.3. Automatic Register Duplication: Hierarchical Proximity

Leveraging design hierarchy information to guide the creation of duplicates and their fan-out assignments is enabled by the DUPLICATE_HIERARCHY_DEPTH assignment.

set_instance_assignment -name DUPLICATE_HIERARCHY_DEPTH -to <register_name> <num_levels>

where,

register_name is the last register in a chain that fans out to multiple hierarchies. To create a register tree, ensure that there are sufficient simple registers behind the node and those simple registers are automatically pulled into the tree.
num_levels corresponds to the upper bound of the number of registers that exist in the chain to use for duplicating down the hierarchies.

The DUPLICATE_HIERARCHY_DEPTH assignment is processed during the Synthesis stage. It is common for high-fanout signals to go through a pipeline of registers and drive into a sub-hierarchy of modules. For example, a system-wide reset can be propagated over several clock cycles and driven into many modules across the design. In several scenarios, it is useful to take advantage of the structure of this subhierarchy to infer the structure of the register tree to be created, such that endpoints within similar hierarchies are assigned the same copy of the signal, and branches in the design hierarchy dictates where to place branches in the register tree.

Important: The registers in the chain must satisfy all of the following conditions to be included in duplication:

Registers must be fed only by another register.
Registers must not be fed by a combinational logic.
Registers must not be part of a synchronizer chain.
Registers must not have any secondary signals.
Registers must not have a preserve attribute or a PRESERVE_REGISTER assignment.
All registers in the chain except the last one must have only one fan-out.

Consider the following example illustration of a netlist with a register chain and hierarchical organization of the endpoints it drives. The DUPLICATE_HIERARCHY_DEPTH assignment duplicates the pipeline registers across hierarchies, as shown in Registers Duplicated Across Hierarchies.

Figure 71. Original Diagram Showing Four Pipeline Registers Connected to Multiple Hierarchies

In this case, regZ is the appropriate assignment target as it is the endpoint in a chain of four registers. There is a maximum of three duplication candidates in this example ( regZ , regY , and regX ), so the assignment value can be anywhere between 1 and 3. regA is not pulled into the hierarchy to preserve the timing and optimization of paths that precede it. The DUPLICATE_HIERARCHY_DEPTH assignment is best used when a signal must be duplicated to more than 100 duplicates and the sub-hierarchy below the chain is deep and meaningful enough to guide the structure of the tree required.

Figure 72. Netlist After Duplicating regZ to Hierarchy Level One

When num_levels is set to 1, only regZ is pulled out of the chain and pushed down one hierarchy level into its fan-out tree.

Figure 73. Netlist After Duplicating regZ to Hierarchy Level Two

set_instance_assignment -name DUPLICATE_HIERARCHY_DEPTH -to regZ 2

When num_levels is set to 2, both regY and regZ are pulled out of the chain. regZ ends up at a maximum hierarchy depth two and regY ends up at hierarchy depth one.

Figure 74. Registers Duplicated Across Hierarchies

When num_levels is set to 3, all three registers ( regZ , regY and regZ ) are pulled out of the chain and pushed to a maximum hierarchy depth of three, two, and one levels, respectively.

The Hierarchical Tree Duplication Summary panel in the Synthesis report provides information on the registers specified by the DUPLICATE_HIERARCHY_DEPTH assignment. It also includes a reason for the chain length that can be used as a starting point for further improvements with the assignment. The Synthesis report also provides a panel named Hierarchical Tree Duplication Details , which provides information about the individual registers in the chain that can be used to better understand the structure of the implemented duplicates.

Related Information

Synchronous Reset Design Strategies, AN 917 Reset Design Techniques for Hyperflex Architecture FPGAs

6.5.9.10. Prevent Shift Register Inference

Turning off the inference of shift registers can increase performance. This setting forces the software to use logic cells to implement the shift register, instead of using the ALTSHIFT_TAPS IP core to implement the registers in memory block. If you implement shift registers in logic cells instead of memory, logic utilization increases.

6.5.9.11. Use Other Synthesis Options Available in Your Synthesis Tool

With your synthesis tool, experiment with the following options if they are available:

Turn on register balancing or retiming
Turn on register pipelining
Turn off resource sharing

These options can increase performance, but typically increase the resource utilization of your design.

6.5.9.12. Fitter Seed

The Fitter seed affects the initial placement configuration of the design. Any change in the initial conditions changes the Fitter results; accordingly, each seed value results in a somewhat different fit. You can experiment with different seeds to attempt to obtain better fitting results and timing performance.

Changes in the design impact performance between compilations. This random variation is inherent in placement and routing algorithms-it is impossible to try all seeds and get the absolute best result.

Note: Any design change that directly or indirectly affects the Fitter has the same type of random effect as changing the seed value. This includes any change in source files, Compiler Settings or Timing Analyzer Settings . The same effect can appear if you use a different computer processor type or different operating system, because different systems can change the way floating point numbers are calculated in the Fitter.

If a change in optimization settings marginally affects the register-to-register timing or number of failing paths, you cannot always be certain that your change caused the improvement or degradation, or whether it is due to random effects in the Fitter. If your design is still changing, running a seed sweep (compiling your design with multiple seeds) determines whether the average result improved after an optimization change, and whether a setting that increases compilation time has benefits worth the increased time, such as with physical synthesis settings. The sweep also shows the amount of random variation to expect for your design.

If your design is finalized you can compile your design with different seeds to obtain one optimal result. However, if you subsequently make any changes to your design, you might need to perform seed sweep again.

Click Assignments ➤ Compiler Settings to control the initial placement with the seed. You can use the DSE II to perform a seed sweep easily.

To specify a Fitter seed use the following Tcl command :

set_global_assignment -name SEED <value>

Related Information

Optimize Settings with Design Space Explorer II on page 107

6.5.9.13. Set Maximum Router Timing Optimization Level

To improve routability in designs where the router did not pick up the optimal routing lines, set the Router Timing Optimization Level to Maximum . This setting determines how aggressively the router tries to meet the timing requirements. Setting this option to Maximum can marginally increase design speed at the cost of increased compilation time. Setting this option to Minimum can reduce compilation time at the cost of marginally reduced design speed. The default value is Normal .

Related Information

Router Timing Optimization Level Logic Option

In Quartus Prime Help

6.5.9.14. Register-to-Register Timing Analysis

Your design meets timing requirements when you do not have negative slack on any register-to-register path on any of the clock domains. When timing requirements are not met, a report on the failed paths can uncover more detail.

6.5.9.14.1. Tips for Analyzing Failing Paths

When you are analyzing failing paths, examine the reports and waveforms to determine if the correct constraints are being applied, and add timing exceptions as appropriate. A multicycle constraint relaxes setup or hold relationships by the specified number of clock cycles. A false path constraint specifies paths that can be ignored during timing analysis. Both constraints allow the Fitter to work harder on affected paths.

Focus on improving the paths that show the worst slack. The Fitter works hardest on paths with the worst slack. If you fix these paths, the Fitter might be able to improve the other failing timing paths in the design.
Check for nodes that appear in many failing paths. These nodes are at the top of the list in a timing report panel, along with their minimum slacks. Look for paths that have common source registers, destination registers, or common intermediate combinational nodes. In some cases, the registers are not identical, but are part of the same bus.
In the timing analysis report panels, click the From or To column headings to sort the paths by source or destination registers. If you see common nodes, these nodes indicate areas of your design that might be improved through source code changes or Quartus Prime optimization settings. Constraining the placement for just one of the paths might decrease the timing performance for other paths by moving the common node further away in the device.

Related Information

Exploring Paths in the Chip Planner on page 184
Design Evaluation for Timing Closure on page 69
Review Timing Path Details on page 80

6.5.9.14.2. Tips for Analyzing Failing Clock Paths that Cross Clock Domains

When analyzing clock path failures:

Check whether these paths cross two clock domains. In paths that cross two clock domains, the From Clock and To Clock in the timing analysis report are different.

Figure 75. Different Value in From Clock and To Clock Field

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Check if the design contains paths that involve a different clock in the middle of the path, even if the source and destination register clock are the same.
Check whether failing paths between these clock domains need to be analyzed synchronously. Set failing paths that are not to be analyzed synchronously as false paths.
When you run report_timing on a design, the report shows the launch clock and latch clock for each failing path. Check whether the relationship between the launch clock and latch clock is realistic and what you expect from your knowledge of the design. For example, the path can start at a rising edge and end at a falling edge, which reduces the setup relationship by one half clock cycle.
Review the clock skew that appears in the Timing Report. A large skew may indicate a problem in the design, such as a gated clock, or a problem in the physical layout (for example, a clock using local routing instead of dedicated clock routing). When you have made sure the paths are analyzed synchronously and that there is no large skew on the path, and that the constraints are correct, you can analyze the data path. These steps help you fine tune your constraints for paths across clock domains to ensure you get an accurate timing report.
Check if the PLL phase shift is reducing the setup requirement. You might adjust this by using PLL parameters and settings.
Ignore paths that cross clock domains for logic protected with synchronization logic (for example, FIFOs or double-data synchronization registers), even if the clocks are related. Alternatively, specify the set_clock_groups -exclusive setting between unrelated clocks
Set false path constraints on all unnecessary paths. Attempting to optimize unnecessary paths can prevent the Fitter from meeting the timing requirements on timing paths that are critical to the design.

Related Information

Report CDC Viewer on page 98

6.5.9.14.3. Tips for Critical Path Analysis

When analyzing the failing paths in a design, it is helpful to understand the interactions around the critical paths.

To understand what may be pulling on a critical path, the following report_timing command can be useful.

In the project directory, run the report_timing command to find the nodes in a critical path.
Copy the code below in a .tcl file, and replace the first two variable with the node names from the From Node and To Node columns of the worst path. The script analyzes the path between the worst source and destination registers.

set wrst_src <insert_source_of_worst_path_here> set wrst_dst <insert_destination_of_worst_path_here> report_timing -setup -npaths 50 -detail path_only -from $wrst_src \ -panel_name "Worst Path||wrst_src -> *" report_timing -setup -npaths 50 -detail path_only -to $wrst_dst \ -panel_name "Worst Path||* -> wrst_dst" report_timing -setup -npaths 50 -detail path_only -to $wrst_src \ -panel_name "Worst Path||* -> wrst_src" report_timing -setup -npaths 50 -detail path_only -from $wrst_dst \ -panel_name "Worst Path||wrst_dst -> *"

From the Script menu, source the .tcl file.
In the resulting timing panel, locate timing failed paths (highlighted in red) in the Chip Planner, and view information such as distance between the nodes and large fan-outs.

The figure shows a simplified example of what these reports analyzed.

Figure 76. Timing Report

The critical path of the design is in red. The relation between the .tcl script and the figure is:

The first two lines show everything inside the two endpoints of the critical path that are pulling them in different directions.
The first report_timing command analyzes all paths the source is driving, shown in green.
The second report_timing command analyzes all paths going to the destination, including the critical path, shown in orange.
The last two report_timing commands show everything outside of the endpoints pulling them in other directions.

If any of these neighboring paths have slacks near the critical path, the Fitter is balancing these paths with the critical path, trying to achieve the best slack.

Related Information

Review Timing Path Details on page 80

6.5.9.14.4. Tips for Creating a .tcl Script to Monitor Critical Paths Across Compiles

Many designs have the same critical paths show up after each compile. In other designs, critical paths bounce around between different hierarchies, changing with each compile.

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This behavior happens in high speed designs where many register-to-register paths have very little slack. Different placements can then result in timing failures in the marginal paths.

In the project directory, create a script named TQ_critical_paths.tcl .
After compilation, review the critical paths and then write a generic report_timing command to capture those paths.

For example, if several paths fail in a low-level hierarchy, add a command such as:

report_timing -setup -npaths 50 -detail path_only \ -to 'main_system: main_system_inst|app_cpu:cpu|*' \ -panel_name 'Critical Paths||s: * -> app_cpu'

If there is a specific path, such as a bit of a state-machine going to other count_sync registers, you can add a command similar to:
Execute this script in the Timing Analyzer after every compilation, and add new report_timing commands as new critical paths appear.

-from 'main_system: main_system_inst|egress_count_sm:egress_inst|update' \ -to '*count_sync*' -panel_name 'Critical Paths||s: egress_sm|update ->

report_timing -setup -npaths 50 -detail path_only \ count_sync'

This helps you monitor paths that consistently fail and paths that are only marginal, so you can prioritize effectively

6.5.9.14.5. Global Routing Resources

Global routing resources are designed to distribute high fan-out, low-skew signals (such as clocks) without consuming regular routing resources. Depending on the device, these resources can span the entire chip or a smaller portion, such as a quadrant. The Quartus Prime software attempts to assign signals to global routing resources automatically, but you might be able to make more suitable assignments manually.

For details about the number and types of global routing resources available, refer to the relevant device handbook.

Check the global signal utilization in your design to ensure that the appropriate signals have been placed on the global routing resources. In the Compilation Report, open the Fitter report and click Resource Section . Analyze the Global & Other Fast Signals and Non-Global High Fan-out Signals reports to determine whether any changes are required.

You might be able to reduce skew for high fan-out signals by placing them on global routing resources. Conversely, you can reduce the insertion delay of low fan-out signals by removing them from global routing resources. Doing so can improve clock enable timing and control signal recovery/removal timing, but increases clock skew. Use the Global Signal setting in the Assignment Editor to control global routing resources.

6.5.9.14.6. Register RAMS and DSPs

If your design includes long timing paths going to and from RAMs and DSPs, you must fully register the RAMs and DSPs.

RAM and DSP performance can vary, depending on the memory mode. A memory using read-during-write mode is slower than a memory that uses a different mode. Refer to your FPGA device documentation for hardware performance specifications. If the fMAX is restricted due to mode, change to a different memory mode with a higher performance specification, if possible.

6.5.10. Metastability Analysis and Optimization Techniques

Metastability problems can occur when a signal is transferred between circuitry in unrelated or asynchronous clock domains, because the designer cannot guarantee that the signal meets its setup and hold time requirements. The mean time between failures (MTBF) is an estimate of the average time between instances when metastability could cause a design failure.

You can use the Quartus Prime software to analyze the average MTBF due to metastability when a design synchronizes asynchronous signals and to optimize the design to improve the MTBF. These metastability features are supported only for designs constrained with the Timing Analyzer, and for select device families.

Synchronization identification can affect retiming. Registers that the Compiler identifies as being part of a synchronizer are not retimed. The default chain length is 3, but in some cases, a synchronizer chain is not necessary and should not be inferred. Use the report_metastability command to identify synchronizer chains that you can reduce.

For example, consider a bus that uses a synchronized enable when crossing clock domains. If you pipeline such a bus, the pipeline stages can be considered as part of a synchronizer chain, and are not used to retime the paths. Setting the chain length to 1 for these paths allows the pipeline registers to be used for retiming.

Related Information

Quartus Prime Pro Edition User Guide: Design Recommendations

6.6. Periphery to Core Register Placement and Routing Optimization

The Periphery to Core Register Placement and Routing Optimization (P2C) option specifies whether the Fitter performs targeted placement and routing optimization on direct connections between periphery logic and registers in the FPGA core. P2C is an optional pre-routing-aware placement optimization stage that enables you to more reliably achieve timing closure.

Note:

The Periphery to Core Register Placement and Routing Optimization option applies in both directions, periphery to core and core to periphery.

Transfers between external interfaces (for example, high-speed I/O or serial interfaces) and the FPGA often require routing many connections with tight setup and hold timing requirements. When this option is turned on, the Fitter performs P2C placement and routing decisions before those for core placement and routing. This reserves the necessary resources to ensure that your design achieves its timing requirements and avoids routing congestion for transfers with external interfaces.

This option is available as a global assignment, or can be applied to specific instances within your design.

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Figure 77. Periphery to Core Register Placement and Routing Optimization (P2C) Flow

P2C runs after periphery placement, and generates placement for core registers on corresponding P2C/C2P paths, and core routing to and from these core registers.

Setting Periphery to Core Optimizations in the Advanced Fitter Setting Dialog Box on page 155

Setting Periphery to Core Optimizations in the Assignment Editor on page 156

Viewing Periphery to Core Optimizations in the Fitter Report on page 156

6.6.1. Setting Periphery to Core Optimizations in the Advanced Fitter Setting Dialog Box

The Periphery to Core Placement and Routing Optimization setting specifies whether the Fitter optimizes targeted placement and routing on direct connections between periphery logic and registers in the FPGA core.

You can optionally perform periphery to core optimizations by instance with settings in the Assignment Editor.

In the Quartus Prime software, click Assignments ➤ Settings ➤ Compiler Settings ➤ Advanced Settings (Fitter) .
In the Advanced Fitter Settings dialog box, for the Periphery to Core Placement and Routing Optimization option, select one of the following options depending on how you want to direct periphery to core optimizations in your design:

a. Select Auto to direct the software to automatically identify transfers with tight timing windows, place the core registers, and route all connections to or from the periphery.
b. Select On to direct the software to globally optimize all transfers between the periphery and core registers, regardless of timing requirements.

Note: Setting this option to On in the Advanced Fitter Settings is not recommended. The intended use for this setting is in the Assignment Editor to force optimization for a targeted set of nodes or instance.

Quartus Prime Pro Edition User Guide: Design Optimization

c. Select Off to disable periphery to core path optimization in your design.

6.6.2. Setting Periphery to Core Optimizations in the Assignment Editor

When you turn on the Periphery to Core Placement and Routing Optimization (P2C/C2P) setting in the Assignment Editor, the Quartus Prime software performs periphery to core, or core to periphery optimizations on selected instances in your design.

You can optionally perform periphery to core optimizations by instance with settings in the Advanced Fitter Settings dialog box.

In the Quartus Prime software, click Assignments ➤ Assignment Editor .
For the selected path, double-click the Assignment Name column, and then click the Periphery to core register placement and routing optimization option in the drop-down list.
In the To column, choose either a periphery node or core register node on a P2C/C2P path you want to optimize. Leave the From column empty. For paths to appear in the Assignments Editor, you must first run Analysis & Synthesis on your design.

6.6.3. Viewing Periphery to Core Optimizations in the Fitter Report

The Quartus Prime software generates a periphery to core placement and routing optimization summary in the Fitter (Place & Route) report after compilation.

Compile your Quartus Prime project.
In the Tasks pane, select Compilation .
Under Fitter (Place & Route) , double-click View Report .
In the Fitter folder, expand the Place Stage folder.
Double-click Periphery to Core Transfer Optimization Summary .

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Table 42. Fitter Report - Periphery to Core Transfer Optimization (P2C) Summary

| From Path | To Path | Status | |-------------|-----------|-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | Node 1 | Node 2 | Placed and Routed -Core register is locked. Periphery to core/core to periphery routing is committed. | | Node 3 | Node 4 | Placed but not Routed -Core register is locked. Routing is not committed. This occurs when P2C is not able to optimize all targeted paths within a single group, for example, the same delay/wire requirement, or the same control signals. Partial P2C routing commitments may cause unresolvable routing congestion. | | Node 5 | Node 6 | Not Optimized -This occurs when P2C is set to Auto and the path is not optimized due to one of the following issues: a. The delay requirement is impossible to achieve. b. The minimum delay requirement (for hold timing) is too large. The P2C algorithm cannot efficiently handle cases when many wires need to be added to meet hold timing. c. P2C encountered unresolvable routing congestion for this particular path. |

6.7. Scripting Support

You can run procedures and make settings described in this manual in a Tcl script. You can also run procedures at a command prompt. For detailed information about scripting command options, refer to the Quartus Prime command-line and Tcl API Help browser. To run the Help browser, type the following command at the command prompt:

If the < value > field includes spaces (for example, 'Standard Fit'), you must enclose

Note: the value in straight double quotation marks.

Related Information

Quartus Prime Pro Edition Settings File Reference Manual
Quartus Prime Pro Edition User Guide: Scripting
Quartus Prime Pro Edition User Guide: Scripting

6.7.1. Initial Compilation Settings

The top table lists the .qsf variable name and applicable values for the settings described in the Initial Compilation: Required Settings section in the Design Optimization Overview chapter. The bottom table lists the advanced compilation settings.

Table 43. Initial Compilation Settings

| Setting Name | .qsf File Variable Name | Values | Type | |--------------------------------------------|--------------------------------------------|------------------------------------------------|--------| | Optimize IOC Register Placement For Timing | OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING | ON , OFF | Global | | Optimize Hold Timing | OPTIMIZE_HOLD_TIMING | OFF , IO PATHS AND MINIMUM TPD PATHS ALL PATHS | Global |

Table 44. Advanced Compilation Settings

| Setting Name | .qsf File Variable Name | Values | Type | |----------------------------------|----------------------------------|----------------------------|--------| | Router Timing Optimization level | ROUTER_TIMING_OPTIMIZATION_LEVEL | NORMAL , MINIMUM , MAXIMUM | Global |

Related Information

Design Optimization Overview on page 7

6.7.2. I/O Timing Optimization Techniques

The table lists the .qsf file variable name and applicable values for the I/O timing optimization settings.

Table 45. I/O Timing Optimization Settings

| Setting Name | .qsf File Variable Name | Values | Type | |--------------------------------------------|--------------------------------------------|----------|----------| | Optimize IOC Register Placement For Timing | OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING | ON , OFF | Global | | Fast Input Register | FAST_INPUT_REGISTER | ON , OFF | Instance | | Fast Output Register | FAST_OUTPUT_REGISTER | ON , OFF | Instance | | Fast Output Enable Register | FAST_OUTPUT_ENABLE_REGISTER | ON , OFF | Instance | | Fast OCT Register | FAST_OCT_REGISTER | ON , OFF | Instance |

Quartus Prime Pro Edition User Guide: Design Optimization

6.7.3. Register-to-Register Timing Optimization Techniques

The table lists the .qsf file variable name and applicable values for the settings described in Register-to-Register Timing Optimization Techniques .

Table 46. Register-to-Register Timing Optimization Settings

| Setting Name | .qsf File Variable Name | Values | Type | |---------------------------------------|-------------------------------------|--------------------------|------------------| | Perform WYSIWYG Primitive Resynthesis | ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP | ON , OFF | Global, Instance | | Fitter Seed | SEED | <integer> | Global | | Maximum Fan-Out | MAX_FANOUT | <integer> | Instance | | Manual Logic Duplication | DUPLICATE_ATOM | <node name> | Instance | | Optimize Power during Synthesis | OPTIMIZE_POWER_DURING_SYNTHESIS | NORMAL, OFF EXTRA_EFFORT | Global | | Optimize Power during Fitting | OPTIMIZE_POWER_DURING_FITTING | NORMAL, OFF EXTRA_EFFORT | Global |

6.8. Timing Closure and Optimization Revision History

The following revision history applies to this chapter:

| Document Version | Quartus Prime Version | Changes | |--------------------|-------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | 2023.10.02 | 23.3 | • Updated version support information and introduction of the Exploration Dashboard GUI ( quartus_edw ) in Aggregating and Comparing Compilation Results with Exploration Dashboard topic. • Revised command syntax in Base Exploration Dashboard Properties topic. • Added new property names to Project Handle Properties topic. • Updated Starting the Exploration Dashboard for the Exploration Dashboard GUI ( quartus_edw ) and options. | | 2023.08.01 | 23.2 | • Updated version support information in Aggregating and Comparing Compilation Results with Exploration Dashboard topic. • Corrected graphic size in Use PLLs to Shift Clock Edges . | | 2023.06.26 | 23.2 | • Revised Base Exploration Dashboard Properties topic to describe user_data property. | | 2023.04.03 | 23.1 | • Added new Aggregating and Comparing Compilation Results with Exploration Dashboard section. • Added new Change Adder Tree Styles topic describing new USE_COMPRESSOR_IMPLEMENTATION assignment. • Updated product family name to "Intel Agilex 7." | | 2022.01.07 | 21.4 | • Clarified device applicability in Spine Clock Limitations topic. • Added Design Assistant information to Review Timing Constraints topic. • Added Design Assistant information to Review Timing Constraints topic. • Removed references to obsolete Advisors throughout. • Added Design Assistant information to Optimize Source Code topic. • Added Design Assistant information to Improving Register-to-Register Timing topic. • Added Design Assistant information to Optimize Synthesis for Performance, Not Area topic. • Added set_clock_groups -exclusive setting information to Tips for Analyzing Failing Clock Paths that Cross Clock Domains topic. • Added new Register RAMS and DSPs topic. • Revised Metastability Analysis and Optimization Techniques topic for synchronizers. | | 2021.10.04 | 21.3 | • Updated name of Report Hierarchical Retiming Restrictions command and report to Report Retiming Restrictions. | | 2021.06.21 | 21.2 | • Added note about variables that can cause differences in the compilation results between seed sweeps with DSE II. | | 2020.09.28 | 20.3 | • Added "Back-Annotate Optimized Assignments" topic to describe new GUI support for back-annotation of pin, RAM, DSP, and clock assignments. • Added "Correct Design Assistant Rule Violations" topic. • Updated "Report Timing" topic for Extra Info tab data. • Added new "Report Logic Depth," "Report Neighbor Paths, "Report Register Spread," "Report Route Net of Interest," "Report Hierarchical Retiming Restrictions," and "Report Pipelining Information," topics to "Review Details of Timing Paths" section. • Moved "Optimize Settings with Design Space Explorer II" to "Design Evaluation for Timing Closure" section and updated links to Help. • Retitled "Intel Stratix 10 Timing Closure Recommendations" topic to "Implement Fast Forward Timing Closure Recommendations". | | 2019.07.01 | 19.1 | Added important notes to Automatic Register Duplication: Estimated Physical Proximity and Automatic Register Duplication: Hierarchical Proximity topics. |

| Document Version | Quartus Prime Version | Changes | |--------------------|-------------------------|-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | 2019.04.01 | 19.1 | • Added more information about register duplication methods in Duplicate Logic for Fan-out Control topic. • Moved content related to manual register duplication from Duplicate Logic for Fan-out Control topic to a newly created sub-topic Manually Adding Duplicate Registers . • Added Automatic Register Duplication: Estimated Physical Proximity and Automatic Register Duplication: Hierarchical Proximity as new sub- topics under Duplicate Logic for Fan-out Control to describe automatic register duplication process. | | 2018.11.12 | 18.1.0 | • Updated "Placement Effort Multiplier" figure and text descriptions in "Adjust Placement Effort" topic. • Updated "Fitter Effort" figure and text descriptions in "Adjust Fitter Effort" topic. • Updated "Optimize Hold Timing Option" screenshot in "Wires Added for Hold" topic. | | 2018.09.24 | 18.1.0 | • Removed duplicated topic: Resource Utilization Optimization Techniques . The topic is now in the Area Optimization chapter. • Removed reference to unsupported CARRY and CASCADE buffers from "Optimize IOC Register Placement for Timing Logic Option" topic. | | 2017.11.06 | 17.1.0 | • Added support for Stratix 10 Hyper-Retiming, Fast Forward compilation, and Fast Forward Viewer. ○ Added topics: Critical Chains, Viewing Critical Chains, Intel Stratix 10 Timing Closure Recommendations, Retiming Limit Details Report, Using the Retiming Limit Details Report, Fast Forward Timing Closure Recommendations, Generating Fast Forward Timing Closure Recommendations, Implementing Fast Forward Recommendations. • Added topic about using partitions to achieve timing closure. • Moved Topic: Design Evaluation for Timing Closure after Initial Compilation: Optional Fitter Settings. • Removed statement about applying physical synthesis optimizations in a portion of a design. • Removed references to optimizing hold timing for selected paths. • Updated logic options about resource utilization optimization settings. | | 2017.05.08 | 17.0.0 | • Added topic: Critical Paths . • Updated Register-to-Register Timing and renamed to Register-to- Register Timing Analysis . • Renamed topic: Timing Analysis with the Timing Analyzer to Displaying Path Reports with the Timing Analyzer . • Removed (LUT-Based Devices) remark from topic titles. • Renamed topic: Optimizing Timing (LUT-Based Devices) to Timing Optimization . • Renamed topic: Debugging Timing Failures in the Timing Analyzer to Displaying Timing Closure Recommendations for Failing Paths . • Renamed topic: Improving Register-to-Register Timing Summary to Improving Register-to-Register Timing . • Removed topics: Tips for Locating Multiple Paths to the Chip Planner , LogicLock Assignments and Hierarchy Assignments , . • Removed reference to deprecated Fitter Effort Logic Option. • Removed information about Pin Advisor and Resource Optimization Advisor. • Removed figure: Clock Regions | | 2016.10.31 | 16.1.0 | • Implemented Intel rebranding. | | 2016.05.02 | 16.0.0 | • Removed information about deprecated physical synthesis options. • Added information about monitoring clustering difficulty. |

| Document Version | Quartus Prime Version | Changes | |--------------------|-------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | 2015.11.02 | 15.1.0 | • Added: Periphery to Core Register Placement and Routing Optimization . • Changed instances of Quartus II to Quartus Prime . | | 2014.12.15 | 14.1.0 | • Updated location of Fitter Settings, Analysis & Synthesis Settings, and Physical Synthesis Optimizations to Compiler Settings. • Updated DSE II content. | | June 2014 | 14.0.0 | • Dita conversion. • Removed content about obsolete devices that are no longer supported in QII software v14.0: Arria GX, Arria II, Cyclone III, Stratix II, Stratix III. • Replaced Megafunction content with IP core content. | | November 2013 | 13.1.0 | • Added Design Evaluation for Timing Closure section. • Removed Optimizing Timing (Macrocell-Based CPLDs) section. • Updated Optimize Multi-Corner Timing and Fitter Aggressive Routability Optimization. • Updated Timing Analysis with the Timing Analyzer to show how to access the Report All Summaries command. • Updated Ignored Timing Constraints to include a help link to Fitter Summary Reports with the Ignored Assignment Report information. | | May 2013 | 13.0.0 | • Renamed chapter title from Area and Timing Optimization to Timing Closure and Optimization. • Removed design and area/resources optimization information. • Added the following sections: Fitter Aggressive Routability Optimization. Tips for Analyzing Paths from/to the Source and Destination of Critical Path. Tips for Locating Multiple Paths to the Chip Planner. Tips for Creating a .tcl Script to Monitor Critical Paths Across Compiles. | | November 2012 | 12.1.0 | • Updated 'Initial Compilation: Optional Fitter Settings' on page 13-2, 'I/O Assignments' on page 13-2, 'Initial Compilation: Optional Fitter Settings' on page 13-2, 'Resource Utilization' on page 13-9, 'Routing' on page 13-21, and 'Resolving Resource Utilization Problems' on page 13-43. | | June 2012 | 12.0.0 | • Updated 'Optimize Multi-Corner Timing' on page 13-6, 'Resource Utilization' on page 13-10, 'Timing Analysis with the Timing Analyzer' on page 13-12, 'Using the Resource Optimization Advisor' on page 13- 15, 'Increase Placement Effort Multiplier' on page 13-22, 'Increase Router Effort Multiplier' on page 13-22 and 'Debugging Timing Failures in the Timing Analyzer' on page 13-24. • Minor text edits throughout the chapter. | | November 2011 | 11.1.0 | • Updated the 'Timing Requirement Settings', 'Standard Fit', 'Fast Fit', 'Optimize Multi-Corner Timing', 'Timing Analysis with the Timing Analyzer', 'Debugging Timing Failures in the Timing Analyzer', 'LogicLock Assignments', 'Tips for Analyzing Failing Clock Paths that Cross Clock Domains', 'Flatten the Hierarchy During Synthesis', 'Fast Input, Output, and Output Enable Registers', and 'Hierarchy Assignments' sections • Updated Table 13-6 • Added the 'Spine Clock Limitations' section • Removed the Change State Machine Encoding section from page 19 • Removed Figure 13-5 • Minor text edits throughout the chapter continued... |

7. Analyzing and Optimizing the Design Floorplan

Determining the layout (placement) of your design elements into physical resources on the FPGA device is known as floorplanning. Floorplanning is a critical design step that helps to ensure that the Compiler places important design logic in the most effective locations for optimum performance and rapid timing closure.

By default, the Compiler determines the best location for logic placement based on your design characteristics and project settings and constraints. You can use the Quartus Prime Chip Planner to visualize the available device resources, and then use a variety of constraints to implement specific placement for important logic, and to group blocks together within specific device regions.

For example, you can define a Logic Lock placement constraint to assign design logic to any arbitrary region of physical resources on the target device that you define. When you assign nodes or entities to the Logic Lock region, the Compiler always places that logic inside the region during fitting. You can define the Logic Lock region's size and location.

Figure 78. Logic Lock Regions in Chip Planner Floorplan

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After compilation, you can back-annotate (copy) the Compiler's resource assignments to preserve that same implementation in subsequent compilations. Assignment backannotation can simplify timing closure by allowing you to lock down placement of your optimized results.

Related Information

Back-Annotate Optimized Assignments, Quartus Prime Pro Edition User Guide: Getting Started

7.1. Location Assignment Optimization Guidelines

Refer to the following optimization guidelines for assigning locations to specific registers and combinational nodes.

Guideline: Assigning Logic to Specific Locations

As part of design optimization, you may want to assign logic in your design to specific locations in the target device floorplan. You may want to make this type of assignment to preserve a good placement result, or to replicate a result in future compiles. In most cases, design partitions are the best way to preserve placement. For more information, refer to Creating a Design Partition in Quartus Prime Pro Edition User Guide: Design Compilation

Guideline: Assigning the Location of One or Two Registers

Sometimes, you may want to assign the location of one or two registers or combinational nodes. In cases where the amount of logic is extremely small, a design partition is not usually practical. If you want to restrict placement to an area of the floorplan, you can use a Logic Lock region placement constraint. For more information, refer to Defining Logic Lock Placement Constraints.

Guideline: Assigning a Register to a Specific Location in an ALM

If you want to assign a register to a specific location in an ALM, you must know the specific location you want to assign. The specific location includes the X and Y coordinates of the LAB that contains the ALM, as well as the sub-location of the register in the ALM in the LAB. The easiest way to find this information during design optimization is to start from a compiled version of the design, and review a timing path report in the Timing Analyzer. Use the string in the Location column as the value for a location assignment.

For example, to assign the LOOP[42].my_div|r[6] register to the location shown in Example Compilation Results , use the following QSF statement:

set_location_assignment -to LOOP[42].my_div|r[6] FF_X117_Y26_N49

Figure 79. Example Compilation Results

| Data Arrival Path | Data Arrival Path | Data Arrival Path | Data Arrival Path | Data Arrival Path | Data Arrival Path | Data Arrival Path | Data Arrival Path | Data Arrival Path | |---------------------|---------------------|---------------------|---------------------|---------------------|---------------------|---------------------|---------------------|------------------------| | | Total | Incr | RF | Type | Fanout | Locatlon | Element Type | Element | | | | 0,317 | RR | IC | | FF_X117_Y26_N49 | ALM Register | LOOP[42] my_divlr[6]ld | | 18 | 8.103 | 0.000 | RR | CELL | | FF_X117_Y26_N49 | ALM Register | LOOP[42] my_divlr[6] |

Guideline: Making Assignments to Compiler-Modified Nodes

If you make location assignments to registers that the Compiler modifies or optimizes during compilation, is unlikely that the Compiler will honor the assignment in subsequent compiles. Compiler-modified or optimized registers include a suffix that begins with a tilde character ( ~ ). If the Compiler modifies a register during compilation, the suffix is likely to change on subsequent compiles as you change other parts of the circuit. When the suffix changes, the name associated with the assignment also changes, so the Compiler does not honor the assignment.

Guideline: Assigning Combinational Logic to Specific Locations

Generally it is not worth assigning combinational logic to specific locations. Combinational logic names are more likely to change in subtle ways from one compile to another. When the names change, any location assignments are ignored if the names don't match.

Related Information

Creating a Design Partition, Quartus Prime Pro Edition User Guide: Design Compilation

7.2. Design Floorplan Analysis in Chip Planner

The Chip Planner simplifies floorplanning by allowing you to view and constrain design logic within a visual display of the FPGA chip resources. You can use the Chip Planner to view and modify the logic placement, connections, and routing paths after running the Fitter. You can also make assignment changes, such as creating and deleting Logic Lock, clock region, and resource assignments.

Figure 80. The Chip Planner

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7.2.1. Starting the Chip Planner

To start the Chip Planner, select Tools ➤ Chip Planner . You can also start the Chip Planner by using any of the following methods:

Click the Chip Planner button on the Quartus Prime software toolbar.

Figure 81. Chip Planner Button on Toolbar

In the following tools, right-click any chip resource and select Locate ➤ Locate in Chip Planner :
[ ] ○ Compilation Report
[ ] ○ Logic Lock Regions Window
[ ] ○ Technology Map Viewer
[ ] ○ Project Navigator window
[ ] ○ Node Finder
[ ] ○ Simulation Report
[ ] ○ Report Timing panel of the Timing Analyzer

7.2.2. Chip Planner GUI

The Chip Planner GUI helps you to visualize and modify the use of device resources for your design. As you zoom in, the level of abstraction decreases, revealing more details about your design.

Figure 82. Zoom to View Device Resource Details in Chip Planner

Chip Planner Toolbar

The Chip Planner toolbar provides access to the main Chip Planner functions for visualizing and modifying device resources. Alternatively, you can access the same Chip Planner commands from the Chip Planner View menu.

Chip Planner Floorplan Views

The Chip Planner includes multiple views to shows various levels of detail for the targeted Altera FPGA device. You can toggle between these different views when you require more or less detail. As you zoom in to the chip, the level of abstraction decreases, revealing more details about the resources that your design targets.

Click the Bird's Eye View button to instantly display a summary high-level chip view, on top of your current Chip Planner view. Use this Bird's Eye view to show your current selection within the larger chip, and to navigate quickly between areas of interest.

Figure 84. Bird's Eye View

The Bird's Eye View is particularly useful when the parts of your design that you want to view are at opposite ends of the chip, allowing you to quickly navigate between resource elements without losing the current frame of reference.

Figure 85. Selected Element Properties

When you select any element in the Chip Planner, the Properties window displays the detailed properties of the objects (such as atoms, paths, Logic Lock regions, or routing elements). To display the Properties window, right-click the object and select View ➤ Properties .

Layers Settings Pane

clicking View ➤ Layers Settings to customize which device structures the Chip Planner displays.

You can select the Basic , Detailed , or Floorplan Editing settings that are preconfigured for specific planning tasks, or specify your own layer settings.

Figure 86. Layer Settings Control Display of Device Resources

Editing Mode

The Chip Planner has two editing modes.

Figure 87. Editing Mode Selection

Assignment -editing mode allows you to make assignment changes that are implemented the next time you run the Fitter.
ECO -editing mode allows you to make post-compilation changes, commonly referred to as engineering change orders (ECOs), without running a full compilation.

Locate History

The Locate History window records all searches you perform using the Locate in Chip Planner command, allowing you to quickly rerun common searches.

7.2.3. Viewing Design Elements in Chip Planner

The Chip Planner allows you to locate and report details on various elements of your design, such as viewing available clock networks, routing congestion, I/O banks, design partitions, and high-speed serial interfaces in the floorplan.

The following section describes how to view various design elements in the Chip Planner.

7.2.3.1. Viewing Architecture-Specific Design Information in Chip Planner

The Chip Planner allows you to view architecture-specific information related to your design. By enabling the options in the Layers Settings pane and Properties tab, you can view:

Device routing resources used by your design -view how blocks are connected, as well as the signal routing that connects the blocks.
LE configuration -view logic element (LE) configuration in your design. For example, you can view which LE inputs are used; whether the LE utilizes the register, the look-up table (LUT), or both; as well as the signal flow through the LE.
ALM configuration -view ALM configuration in your design. For example, you can view which ALM inputs are used; whether the ALM utilizes the registers, the upper LUT, the lower LUT, or all of them. You can also view the signal flow through the ALM.

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I/O configuration -view device I/O resource usage. For example, you can view which components of the I/O resources are used, whether the delay chain settings are enabled, which I/O standards are set, and the signal flow through the I/O.
PLL configuration -View phase-locked loop (PLL) configuration in your design. For example, you can view which control signals of the PLL are used with the settings for your PLL.
Timing -view the delay between the inputs and outputs of FPGA elements. For example, you can analyze the timing of the DATAB input to the COMBOUT output.

7.2.3.2. Viewing Available Clock Networks in Chip Planner

When you enable a clock region layer in the Layers Settings pane, you display the areas of the chip that are driven by global and regional clock networks. When the selected device does not contain a given clock region, the option for that category is unavailable in the dialog box.

Depending on the clock layers that you activate in the Layers Settings pane, the Chip Planner displays regional and global clock regions in the device, and the connectivity between clock regions, pins, and PLLs.

The Stratix 10 and Agilex FPGA portfolio device clocking architecture does not include regional clocks nor spine clocks.

Note:

Clock regions appear as rectangular overlay boxes with labels indicating the clock type and index. Select a clock network region by clicking the clock region. The clock-shaped icon at the top-left corner indicates that the region represents a clock network region.

Figure 88. Clock Regions

Spine/sector clock regions have a dotted vertical line in the middle. This dotted line indicates where two columns of row clocks meet in a sector clock.

To change the color in which the Chip Planner displays clock regions, select Tools ➤ Options ➤ Colors ➤ Clock Regions .

Related Information

Spine Clock Limitations on page 137

7.2.3.3. Viewing Clock Sector Utilization in Chip Planner

The Chip Planner provides a visual representation of a design's clock sector utilization.

To generate the report in the Chip Planner:

In the Tasks pane, double-click Report Clock Sector Utilization to open the Report Clock Sector Utilization dialog box.
If you want the report to include the source nodes, turn on Report source nodes .

The equivalent TCL command appears at the bottom of the Dialog Box.

Click OK .

The report output shows the most used clock sectors.

The Report pane displays a list of clock sectors, with colors according to utilization. The clock sector with the highest utilization appears in red, and the sector with least utilization appears in blue.

You can turn on or off the sector visibility from the Report pane. You can also highlight nodes, if applicable.

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Figure 89. Clock Sector Utilization Report

7.2.3.4. Viewing Routing Congestion in Chip Planner

The Chip Planner offers a comprehensive visual representation of device resources, enabling in-depth analysis of routing and congestion. Through detailed routing information and congestion visualization, you can gain insights into resource utilization across the device. The "Report Routing Utilization Task" generates an accurate heatmap of routing resources utilized in the current compilation, facilitating the identification of areas experiencing routing congestion. This feature aids in making informed design modifications to alleviate congestion and ensure adherence to routing requirements.

To access the Chip Planner window from the Quartus GUI, navigate to Tools ➤ Chip Planner .

In the Chip Planner window, double-click the Report Routing Utilization command in the Task list.
In the Report Routing Utilization dialog box, you have the following options for viewing the heatmap:

Click Preview .

Clicking Preview shows you the utilization heatmap as long as the Report Routing Utilization dialog box remains open.

The heatmap does not persist as a report when you close the dialog box.

For convenience, you can click Preview when you want to quickly check routing utilization and then cancel out of the dialog box without generating a persistent report.

Click OK

Clicking OK generates the utilization heatmap as a persistent Chip Planner report that you can select and deselect.

A persistent heatmap report is useful when you want to review the routing utilization report multiple times in an Chip Planner session.

Change the Routing utilization type to display congestion for specific resources.
Adjust the slider for Threshold percentage to change the congestion threshold level.

| Resource Type | Report Description | Report Description | |----------------------------|-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | Routing hotspots (default) | Shows a heatmap that combines the maximum congestion at each device location, regardless of what wire type is associated with the maximum congestion. Use the report for this resource type to quickly identify all areas of the device that have high routing utilization. | Shows a heatmap that combines the maximum congestion at each device location, regardless of what wire type is associated with the maximum congestion. Use the report for this resource type to quickly identify all areas of the device that have high routing utilization. | | Individual wire type | Select individual wire types to figure out how much routing congestion is associated with each wire type. | Select individual wire types to figure out how much routing congestion is associated with each wire type. | | Individual wire type | Long wires | Areas of congestion in the longest wire types are often associated with timing critical paths. When registers are placed far apart, they may require long routing wires to connect them with a chance of meeting the timing requirement. When parts of a design are insufficiently pipelines, the long wires tend to be used up quickly because there are fewer long wires than short wires. | | Individual wire type | Short wires | Areas of congestion are less common in short wires because there are more of them. However, areas of congestion in short wires can indicated highly interconnected logic or extremely highly utilized areas of the device. |

A good starting point for your analysis is a threshold value in the range of 90-95% . If utilization is below that threshold (that is, no areas of pink in the utilization report), timing failures are unlikely being caused by routing congestion.

Areas of high routing utilization do not necessarily correlate with timing failures, but they are a good place to check against timing failures.

The default display uses dark blue for 0% congestion and red for 100%.

The congestion map aids in assessing whether adjustments to the floorplan or RTL are necessary to alleviate routing congestion. It visualizes resource utilization by shading logic resources, with darker shades indicating higher routing resource usage. Regions surpassing the specified threshold, set in the Report Routing Utilization dialog box, are highlighted in pink, signaling areas of excessive routing utilization.

To identify potential routing resource shortages, it's essential to examine each routing interconnect type individually from the drop-down list in the Routing Utilization Settings dialog box. Typically, peak interconnect usage exceeding 75%, or average interconnect usage surpassing 60%, may suggest challenges in accommodating your design. Moreover, peak interconnect usage above 90%, or average interconnect usage beyond 75%, indicate heightened risk of encountering fitting issues.

Related Information

Viewing Routing Resources on page 186

7.2.3.4.1. Areas with Routing Congestion

Even if the average congestion is not excessively high, certain areas of the design may experience significant congestion in specific routing types. In such cases, exploring modifications to the design connections can mitigate routing congestion. Occasionally, this congestion might arise from the HDL coding style. It's advisable to examine the HDL code of the blocks positioned in congested zones to identify opportunities for reducing interconnect usage through code modifications. Additionally, if the congested area falls within a Logic Lock region or lies between Logic Lock regions, consider adjusting or removing the Logic Lock regions and recompiling the design. If the compilation time remains unchanged, it indicates an inherent characteristic of your design and placement. In contrast, if the time decreases, contemplate modifying the size, location, or contents of Logic Lock regions to alleviate congestion and reduce routing time.

7.2.3.4.2. Congestion due to HDL Coding style

Sometimes, routing congestion may be a result of the HDL coding style used in your design. After identifying congested areas using the Chip Planner, review the HDL code for the blocks placed in those areas to determine whether you can reduce interconnect usage by code changes.

7.2.3.5. Viewing I/O Banks in Chip Planner

To view the I/O bank map of the device in the Chip Planner, double-click Report All I/O Banks in the Tasks pane.

7.2.3.6. Viewing High-Speed Serial Interfaces (HSSI) in Chip Planner

The Chip Planner displays a detailed block view of the receiver and transmitter channels of the high-speed serial interfaces. To display the HSSI block view, doubleclick Report HSSI Block Connectivity in the Tasks pane.

Figure 90. Arria 10 HSSI Channel Blocks

7.2.3.7. Viewing Source and Destination Nodes in Chip Planner

The Chip Planner allows you to view the registered fan-in or fan-outs of nodes in compiled designs with the Report Registered Connections task. This report is different from the Generate Fanin/Fanout connections report in that the source and destination nodes appear without connection lines, which may obscure the view.

In the Chip Planner, select one or more nodes.
In the Task pane, double-click Report Registered Connections .
Select the options from the dialog box, and click OK .

The Reports pane displays the registered source and destination nodes. Turn on or off to switch visibility in the graphic view.

Figure 91. Report Registered Connections

Related Information

Viewing Fan-In and Fan-Out in Chip Planner on page 177

7.2.3.8. Viewing Fan-In and Fan-Out in Chip Planner

Displays the atoms that fan-in to or fan-out from a resource, including connectivity lines.

To display the fan-in or fan-out connections from a resource you selected,

In the Chip Planner toolbar, click the Generate Fan-In Connections button or the Generate Fan-Out Connections button.

Figure 92. Chip Planner Toolbar Buttons

To remove other connections that appear on the Chip Planner view, click the Clear Unselected Connections button.

You can also perform this actions from the Chip Planner View menu.

Related Information

Viewing Source and Destination Nodes in Chip Planner on page 177

7.2.3.9. Viewing Immediate Fan-In and Fan-Out in Chip Planner

Displays the immediate fan-in or fan-out connection for the selected atom.

For example, when you view the immediate fan-in for a logic resource, you see the routing resource that drives the logic resource. You can generate immediate fan-ins and fan-outs for all logic resources and routing resources.

To display the immediate fan-in or fan-out connections, click View ➤ Generate Immediate Fan-In Connections or View ➤ Generate Immediate Fan-Out Connections .
To remove the connections displayed, use the Clear Unselected Connections button in the Chip Planner toolbar.

Figure 93. Chip Planner Toolbar Buttons

7.2.3.10. Viewing the Selected Contents in Chip Planner

You can view a detailed report of the contents of any area that you select in the Chip Planner. When you view the contents of a selected area, Chip Planner generates a hierarchical, color coded list of the design elements in the selection. This functionality allows you to quickly determine where the Compiler places specific modules of the design.

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Figure 94. Report Selection Contents Dialog Box

Follow these steps to view selected contents in the Chip Planner:

In the Tasks pane, double-click Report Selection Contents . The Report Selection Contents dialog box appears.
Under Report design instances in selection , turn on or off Show registers names and Show combinational names to display names of those type in the report.
Click OK . The report generates and displays the list of selected elements in the Reports pane.

Figure 95. Viewing Selected Contents

To customize the color coding of report folders, right-click any report, and then click Properties . You can customize the Report Name , Report Color , and the Highlighted Area Minimum Size for the report.

Figure 96. Selected Entities Report Properties

7.2.3.11. Viewing the Location and Utilization of Device Resources in Chip Planner

Chip Planner can generate reports about the different types of device resources located in the in Chip Planner view, including the resource location and utilization.

To view the location and utilization of a device resource in Chip Planner:

On the Chip Planner Tasks pane, click Report Resources . The Report Resources dialog box appears.
In Resource Type , select the device resource type that you want to locate.
Click OK . The report generates and displays the list of selected resources in the Reports pane.
In the Reports pane, right-click a resource type to Zoom to Report or view the Properties of the resource in the Resources report.

Figure 97. Report Resources Dialog Box

7.2.3.12. Viewing Module Placement by Cross-Probing to Chip Planner

You can use cross-probing to determine the location of a design module on the device in Chip Planner.

To view the placement of a module with cross-probing following place and route:

On the Project Navigator Hierarchy tab, right-click on a module name and click Locate in Chip Planner .

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Figure 98. Locate in Chip Planner Command from Project Navigator

In the Reports pane, view the list of Located Entities color-coded and separated by module.

Figure 99. Located Entities in Reports Pane

7.2.4. Finding Design Elements in the Chip Planner

Use the Find tab to locate any design atom, port, location, or routing element by name within the Chip Planner view. The Find tab located in Chip Planner, you can view more information about the element on the Properties tab.

Figure 100. Click the Find Button to Search Chip Planner

To use the Find tab to locate design elements in Chip Planner:

In Chip Planner, click the Find button. The Find tab opens.
In Find what , enter the design element name(s) (and any wildcard characters) to find in Chip Planner.
Under Find In , enable or disable the types of design elements to include in the search, as Find Options (Chip Planner Search) on page 184 describes.
To begin the search, click Find Next . The search results display in the Results list.
To view details about any item in the Results list, click the Properties tab.
To locate found elements in Chip Planner, right-click the design element in the Results list and click Zoom Into Selections . Chip Planner zooms into the selected elements.

Figure 101. Find Options and Controls

Figure 102. Zoom Into Selections from Search Results

7.2.4.1. Find Options (Chip Planner Search)

You can enable or disable the following Find In options to narrow or expand the search for design elements in Chip Planner:

Table 47. Find In Options

| Option | Description | |----------------------|----------------------------------------------------------------------------------| | Atoms | Finds all matching atom names in the design within Chip Planner. | | Location Assignments | Finds all matching location assignments in the design within Chip Planner. | | Routing Elements | Find all matching routing element names in the design within Chip Planner. | | All | Find all matching elements of all supported types within Chip Planner. | | Input/Output Ports | Find all matching input and output port names in the design within Chip Planner. | | Resource Locations | Find all matching routing element names in the design within Chip Planner. | | Partition Ports | Find all matching partition port names in the design within Chip Planner. | | Select all found | Automatically selects all found elements following search. |

7.2.5. Exploring Paths in the Chip Planner

Use the Chip Planner to explore paths between logic elements. The following examples use the Chip Planner to traverse paths from the Timing Analysis report.

7.2.5.1. Analyzing Connections for a Path

To determine the elements forming a selected path or connection in the Chip Planner, click the Expand Connections button in the Chip Planner toolbar.

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Figure 103. Chip Planner Toolbar Buttons

7.2.5.2. Locate Path from the Timing Analysis Report to the Chip Planner

To locate a path from the Timing Analysis report to the Chip Planner, perform the following steps:

Select the path you want to locate in the Timing Analysis report.
Right-click the path and point to Locate Path ➤ Locate in Chip Planner . The path appears in the Locate History window of the Chip Planer.

Figure 104. Path List in the Locate History Window

7.2.5.3. Show Delays

With the Show Delays feature, you can view timing delays for paths appearing in Timing Analyzer reports. To access this feature, click View ➤ Show Delays in the main menu. Alternatively click the Show Delays button in the Chip Planner toolbar. To see the partial delays on the selected path, click the '+' sign next to the path delay displayed in the Locate History window.

Figure 105. Show Delays Button on Chip Planner Toolbar

For example, you can view the delay between two logic resources or between a logic resource and a routing resource.

Figure 106. Show Delays Associated in a Timing Analyzer Path

7.2.5.4. Viewing Routing Resources

With the Chip Planner and the Locate History window, you can view the routing resources that a path or connection uses. You can also select and display the Arrival Data path and the Arrival Clock path.

In the Locate History window, right-click a path and select Show Physical Routing to display the physical path. To adjust the display, right-click and select Zoom to Selection .

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Figure 107. Show Physical Routing

Figure 108. Highlight Routing

To see the rows and columns where the Fitter routed the path, right-click a path and select Highlight Routing .

Related Information

Viewing Routing Congestion in Chip Planner on page 173

7.2.6. Viewing Assignments in the Chip Planner

You can view location assignments in the Chip Planner by selecting the appropriate layer, or any custom preset that displays block utilization in the Layers Settings pane. The Chip Planner displays assigned resources in a predefined color (gray, by default).

Figure 109. Viewing Assignments in the Chip Planner

Drag resource to move to neighboring cell

To create or move an assignment, or to make node and pin location assignments to Logic Lock regions, drag the selected resource to a new location. The Fitter applies the assignments that you create during the next place-and-route operation.

7.2.7. Viewing High-Speed and Low-Power Tiles in the Chip Planner

Some Altera devices have ALMs that can operate in either high-speed mode or lowpower mode. The power mode is set during the fitting process in the Quartus Prime software. These ALMs are grouped together to form larger blocks, called 'tiles'.

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Figure 110. High-Speed and Low Power Tiles in an Arria 10 Device

To view a power map, double-click Tasks ➤ Core Reports ➤ Report High-Speed/ Low-Power Tiles after running the Fitter. The Chip Planner displays low-power and high-speed tiles in contrasting colors; yellow tiles operate in a high-speed mode, while blue tiles operate in a low-power mode.

7.2.8. Viewing Design Partition Placement

With the Report Design Partitions command, you can view the physical placement of design partitions using the same color map as the Design Partition Planner.

The Report Design Partitions Advanced command opens the Report Design Partitions Advanced dialog box that allows you to select a partition and generate a report of the pins belonging to the partition. It highlights the selected partition's boundary ports and pins in the Chip Planner, and optionally reports the routing utilization and routing element details.

7.3. Defining Logic Lock Placement Constraints

A Logic Lock region is a powerful type of logic placement and routing constraint. You can define any arbitrary region of physical resources on the target device as a Logic Lock region, and then assign design nodes and other properties to the region. When you constrain design nodes to a Logic Lock region, the Fitter always places those nodes within the region resulting in more predictable results with each design iteration.

Your floorplan can contain multiple Logic Lock regions, depending on your design characteristics. You can also define a routing region as part of a Logic Lock region. The routing region specifies the routing area constraint.

The Chip Planner makes it easy to visualize and constrain device resources within a device floorplan. You can draw or specify the dimensions of a Logic Lock region in the floorplan using the Logic Lock Regions window. After running synthesis or fitting, you can then assign design nodes as members of the region to implement the constraint.

Figure 111. u_blinking_led Logic Lock Region Defined in Chip Planner

To detect and resolve any potential problems with Logic Lock regions in your project, click Report DRC to run the Design Assistant to check for the FLP rule category. FLP Design Assistant rules detect possible issues with floorplanning and Logic Lock regions.

Figure 112. Floorplanning (FLP) Design Assistant Rules

7.3.1. The Logic Lock Regions Window

Use the Logic Lock Regions window GUI to view, define, and modify the attributes of Logic Lock regions in your project.

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Figure 113. Logic Lock Regions Window

The Logic Lock Regions window organizes the constraints into the following two tabs:

Table 48. Logic Lock Regions Window Tabs

| Logic Lock Regions Window Tab | Description | |---------------------------------|-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | Assignment Regions | Displays the properties of all Logic Lock regions that you define in the current project (saved in the .qsf ). Modify Logic Lock region properties in this tab. | | Compilation Regions | Displays the properties of any Logic Lock region contained in a .qdb file in the project. Tab is read-only because you must edit imported Logic Lock region properties in the original project. |

Open the Logic Lock Regions window by clicking:

Assignments ➤ Logic Lock Window .
View ➤ Logic Lock Window in the Chip Planner.
Right-click Logic Lock Region ➤ Logic Lock Regions Window in Project Navigator.

You can customize the appearance of Logic Lock Regions window by dragging the columns to change their order and showing or hiding optional columns by rightclicking any column.

7.3.2. Defining Logic Lock Regions

The Quartus Prime provides multiple entry points in the GUI to create and modify Logic Lock constraints as appropriate in your workflow.

Before Analysis & Elaboration-you can use the Logic Lock Regions window and the Chip Planner to visualize the chip and define empty regions without member nodes.
After Analysis & Elaboration or Fitter-you can assign member nodes, and even define a Logic Lock region from a selected design entity.

You can assign an entity in the design to only one Logic Lock region, but the entity can inherit regions by hierarchy. This hierarchy allows a reserved region to have a sub region without reserving the resources in the sub region.

If a Logic Lock region boundary includes part of a device resource, the Quartus Prime software allocates the entire resource to that Logic Lock region.

Figure 114. Chip Planner with Logic Lock Button on Toolbar

7.3.2.1. Defining a Logic Lock Region in Chip Planner

The Chip Planner allows you to easily see Logic Lock region locations and properties in relation to other resources in the device.

Before Analysis and Elaboration, the Chip Planner displays the device floorplan resources that are available. You can define Logic Lock regions in this floorplan. After running Analysis & Elaboration, you can add member nodes to the region.

To draw a Logic Lock region in the Chip Planner:

Open an Quartus Prime project.
Click Processing ➤ Start ➤ Start Analysis & Elaboration . Note: You can this step if you want to reserve the empty region without adding

member nodes yet.

To open the Chip Planner, click Tools ➤ Chip Planner . Chip Planner opens and loads device resource information.
Click the Create Logic Lock Region button on the Chip Planner Toolbar.

Figure 115. Create Logic Lock Region Button on Toolbar

To define the region dimensions and location, click and drag the cursor on the Chip Planner floorplan to draw a region of your preferred location and size. An <<unassigned>> Logic Lock region appears in the Chip Planner and Logic Lock Regions window at the coordinates you specify.

Quartus Prime Pro Edition User Guide: Design Optimization

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Figure 116. Drag Cursor to Define Region Location and Size

In the Logic Lock Regions window, double-click <<unassigned>> and type a descriptive name for the region.
To add member nodes to the region, click the Members cell, and then click the (…) button to search for the nodes you want to add. You must complete step 2 before this step.
Confirm or customize the region Width , Height , and point of Origin settings in the Logic Lock Regions window.
To prevent the Fitter from placing any other logic in the region, turn on the Reserved option. This option is useful for preliminary floorplanning and for reserving device resources for logic to be added later. Otherwise, leave this option off.
To exclude periphery device resources from the region, turn on the Core-Only option.
For region Size/State , specify whether you or the Fitter determines the size and placement of the Logic Lock region:

Figure 117. Specifying Region Name and Members

If set to Fixed/Locked , the default value, you define the Logic Lock region's size and placement.
If set to Auto/Floating , the Fitter determines the size and placement of the Logic Lock region.

For Routing Region , specify the type of routing region constraint, such as Unconstrained , Whole Chip , or Fixed Width Expansion options. Refer to Defining Routing Regions on page 197.

7.3.2.1.1. Logic Lock Region Properties

You can view and modify the following properties for the Logic Lock regions that you define. You can access these properties using either of these methods:

Click Assignments ➤ Logic Lock Regions Window .
Right-click and existing Logic Lock region, and then click Logic Lock Region Properties .

Table 49. Attributes of Logic Lock Regions

| Option | Values | Behavior | |----------------|---------------------------------------------------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | Width | Number of columns | Specifies the width of the Logic Lock region. If Size/State is set to Auto/Floating , the attribute is set to Undetermined . | | Height | Number of rows | Specifies the height of the Logic Lock region. If Size/State is set to Auto/Floating , the attribute is set to Undetermined . | | Origin | Any Floorplan Location | Specifies the location of the Logic Lock region on the floorplan. The origin is at the lower left corner of the Logic Lock region. | | Reserved | Off | On | Prevents the Fitter from placing other logic in the region. Unless enabled, the Fitter fills unoccupied resources with other nodes and entities that have not been assigned to another region. You cannot apply the Reserved assignment to routing regions. | | Core-Only | Off | On | Excludes periphery resources from a region. Quartus Prime Pro Edition region assignments apply to periphery resources by default. If the region is designated as Reserved and Core Only , periphery resources are not reserved from the region. | | Size/State | Fixed/Locked | Auto/Floating | Specifies whether you or the Fitter determines the size and placement of the Logic Lock region. • If set to Fixed/Locked , the default value, you define the Logic Lock region's size and placement. • If set to Auto/Floating , the Fitter determines the size and placement of the Logic Lock region. | | Routing Region | Unconstrained | Whole Chip | Fixed with Expansion | Custom | The type of routing region constraint, such as Unconstrained , Whole Chip , or Fixed Width Expansion options. For more details, refer to Defining Routing Regions on page 197. |

7.3.2.1.2. Snapping to a Region

When placing Logic Lock regions in the Chip Planner by hand, Chip Planner is set to snap the placement of the region to adjacent LAB boundaries by default. This means that as you drag the region to a location, the region snaps to the adjacent lab boundary when you drop the region in the floorplan.

Alternatively, you can click View ➤ Logic Lock Regions ➤ Snap Logic Lock Region to to toggle the snapping between Snap to Lab or Snap to Clock Sector Region . When your turn on Snap to Clock Sector Region , orange grid lines appear to show the clock sector region boundaries when you create, resize, or move the region.

Figure 118. Snapped to the Region

Creating Region : Left-click on the mouse to create the Logic Lock region. Upon releasing the mouse, the created Logic Lock region snaps to the containing clock region or sector.
Resize region (and resize diagonal) : Left-click on the mouse and drag the Logic Lock region handle. Upon releasing the mouse, the Logic Lock region resizes and snaps to the containing clock region or sector.
Move region : Select and drag the Logic Lock region to highlight the clock region boundaries. Upon releasing the mouse button, the Logic Lock region moves to the new position and snaps to the containing clock region or sector.
Same place and route regions are moved : Both Logic Lock regions move and snap to the containing clock sectors.
Only place | route region is moved : The selected region moves and snaps to the clock sector, and prompts warning if the new location or size of the region does not adhere to 'place bboxes contained within route bboxes' rule.
Subtract or make a hole : When performing subtract in the snap-to-clock-region mode, you create a region where the region is snapped to a clock region or a sector, and then subtract away.

7.3.2.1.3. Considerations for Auto Sized Regions

If you use Auto/Floating Size/State Logic Lock regions, consider the following limitations and effects:

Auto/Floating regions cannot be reserved.
Verify that your Logic Lock region is not empty. If you do not assign any instance to the region, the Fitter reduces the size to 0 by 0, making the region invalid.
The region may or may not be associated with a partition. When you combine partitions with Auto/Floating Size/State Logic Lock regions, you get flexibility to solve your particular fitting challenges. However, every constraint that you add reduces the solutions available, and too many constraints can result in the Fitter not finding a solution. Some cases are:
If a partition is preserved at synthesis or not preserved, the Logic Lock region confines the logic to a specific area, allowing the Fitter to optimize the logic within the partition, and optimize the placement within the Logic Lock region.
If a partition is preserved at placement, routed, or final; a Logic Lock region is not an effective placement boundary, because the location of the partition's logic is fixed.
However, if the Logic Lock region is reserved, the Fitter avoids placing other logic in the area, which can help you reduce resource congestion.
Once the outcome of the Logic Lock region meets your specification, you can:
Convert the Logic Lock region to Fixed/Locked Size/State.
Leave the Logic Lock region with Auto/Floating Size/State attribute and use the region as a 'keep together' type of function.
If the Logic Lock region is also a partition, you can preserve the place and route through the partition and remove the Logic Lock region entirely.

7.3.2.2. Defining a Logic Lock Region from the Project Navigator

After you run Analysis & Elaboration or the Fitter, you can assign the member nodes to the Logic Lock region. The Project Navigator facilitates easy Logic Lock constraint creation and member assignment from your design entities in a single step.

To define a Logic Lock region from the Project Navigator:

Run Analysis & Elaboration or the Fitter (Finalize) from the Compilation Dashboard. The Project Navigator displays the design hierarchy when complete.
Expand the design hierarchy in the Project Navigator, right-click any design entity, and click Logic Lock Region ➤ Create New Logic Lock Region .

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Figure 119. Create New Logic Lock Region

The new region appears with the assigned node in the Logic Lock Regions window. Modify the Region Name and other properties in the Logic Lock Regions window.

Figure 120. New Logic Lock Region In Logic Lock Regions Window

7.3.2.3. Defining Routing Regions

A routing region is an element of a Logic Lock region that specifies the routing area. A routing region must encompass the existing Logic Lock placement region. Routing regions cannot be set as reserved. To define the routing region, double-click the Routing Region cell in the Logic Lock Regions window, and select an option from the drop-down menu.

Figure 121. Routing Regions

Table 50. Routing Region Options

| Option | Description | |-------------------------|-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | Unconstrained (default) | Allows the Fitter to use any available routes on the device. | | Whole Chip | Same result as Unconstrained , but writes the constraint in the Quartus Prime settings file ( .qsf ). | | Fixed with Expansion | Follows the outline of the placement region. The routing region scales by a number of rows and columns larger than the placement region. | | Custom | Allows you to define a custom shape routing region around the Logic Lock region. When you select the Custom option, the placement and routing regions move independently in the Chip Planner. In this case, move the placement and routing regions by selecting both using the Shift key. |

7.3.2.4. Defining Empty Logic Lock Regions

The Quartus Prime supports the use of Logic Lock regions without any members. You can use such empty regions to reserve device resources to contain logic to be add later. This technique require that you turn on the region's Reserved setting to prevent the Fitting from placing any other logic within this region.

Empty Logic Lock regions can be useful for the following scenarios:

Preliminary floorplanning
Complex incremental builds, such as root partition reuse
Team based design and interconnect logic
Confining logic placements

Since Logic Lock regions do not reserve any routing resources by default, the Fitter may use the reserved area for routing purposes.

Custom Routing

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Use the Core Only attribute for empty Logic Lock regions. When you include periphery resources in empty regions, you restrict the periphery component placement, which can result in a no fit design. After you name the empty region, you can perform the same manipulations as with any Logic Lock region that includes members.

Figure 122. All Logic Placed Outside an Empty region

The figure shows an empty Logic Lock region and the logic placed around it. However, some I/Os, HSSIO, and PLLs are present in the empty region because the output port connects to the I/O that is part of the root_partition (top-level partition).

7.3.2.5. Defining Hierarchical Logic Lock Regions

Logic Lock regions can be fully hierarchical. Parent regions must completely contain all child regions. The Reserved and Core-Only assignments also apply hierarchically.

Logic Lock assignments follow the same precedence as other constraints and assignments.

7.3.3. Customizing the Shape of Logic Lock Regions

To create custom shaped Logic Lock regions, you can perform logic operations. Nonrectangular Logic Lock regions can help you exclude certain resources, or place parts of your design around specific device resources to improve performance.

Attention:

There is no undo feature for the Logic Lock shapes for 17.1.

Logic Lock Regions Properties Dialog Box

Use the Logic Lock Regions Properties dialog box to view and modify detailed information about your Logic Lock region, such as which entities and nodes are assigned to your region, and which resources are required.

To open the Logic Lock Regions Properties dialog box, right-click the region and select Logic Lock Regions Properties... .

7.3.3.1. Adding a New Shape to a Logic Lock Region

To add a new shape to an existing Logic Lock region, perform the following steps in the Chip Planner:

Select the Logic Lock region.
In the Navigation toolbar, click the Add Logic Lock Region button.

Figure 123. Add Logic Lock Region Button in Toolbar

Click and drag to generate the shape you want to add. The new shape merges automatically with the selected Logic Lock region.

Attention: If you selected more than one region, the operation appends the new shape to all of the regions.

Figure 124. Using the Add Logic Lock Region Feature

7.3.3.2. Subtracting Shape from Logic Lock Region

To subtract a shape from an existing Logic Lock region, perform the following steps in the Chip Planner:

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Select the Logic Lock region.
In the Navigation toolbar, click the Subtract Logic Lock Region button.

Figure 125. Subtract Logic Lock Region Toolbar Button

Click and drag the shape you want to subtract. The modified region displays automatically.

The operation performs in all selected regions.

Figure 126. Using the Subtract Logic Lock Region Feature

7.3.3.3. Merging Logic Lock Regions

To merge two or more Logic Lock regions, perform the following steps:

Ensure that no more than one of the regions that you intend to merge has logic assignments.
Arrange the regions into the locations where you want the resultant region.
Select all the individual regions that you want to merge by clicking each of them while pressing the Shift key.
Right-click the title bar of any of the selected Logic Lock regions and select Logic Lock Regions ➤ Merge Logic Lock Region . The individual regions that you select merge to create a single new region.
If you select multiple named regions, the Merge Logic Lock Region option is deactivated.

Figure 127. Using the Merge Logic Lock Region command

7.3.3.4. Defining Noncontiguous Logic Lock Regions

You can create disjointed regions by using the Logic Lock region manipulation tools. Noncontiguous regions act as a single Logic Lock region for all Logic Lock region attributes.

Figure 128. Logic Lock Regions in Chip Planner Floorplan

7.3.4. Assigning Device Pins to Logic Lock Regions

A Logic Lock region incorporates all device resources within its boundaries, including memory and pins. The Quartus Prime Pro Edition software does not include pins automatically when you assign an entity to a region, unless the Core Only attribute is off.

You can manually assign pins to Logic Lock regions; however, this placement puts location constraints on the region. The software only obeys pin assignments to locked regions that border the periphery of the device. The locked regions must include the I/O pins as resources.

7.3.5. Viewing Connections Between Logic Lock Regions in Chip Planner

You can view and edit Logic Lock regions using the Chip Planner. To view and edit Logic Lock regions, use Floorplan Editing in the Layers Settings window, or any layers setting mode that has the User-assigned Logic Lock regions setting enabled.

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The Chip Planner shows the connections between Logic Lock regions. By default, you can view each connection as an individual line. You can choose to display connections between two Logic Lock regions as a single bundled connection rather than as individual connection lines. To use this option, open the Chip Planner and on the View menu, click Inter-region Bundles .

Related Information

Inter-region Bundles Dialog Box

For more information about the Inter-region Bundles dialog box, refer to Quartus Prime Help.

7.3.6. Example: Placement Best Practices for Arria 10 FPGAs

Logic Lock regions must take into account the device topology.

This example describes how I/O Columns constrain locations in Logic Lock regions in designs targeting Arria 10 FPGAs.

Figure 129. I/O Columns in Arria 10 FPGAs

Arria 10 FPGAs have I/O columns located in the middle of the device. Signals can only enter or exit these columns from the side that faces the device edge.

Figure 130. Signals Crossing I/O Columns in Arria 10 FPGAs

Routing a signal to cross the I/O column increases the routing delay, and can reduce design performance.

Figure 131. Strategic Placement for Logic Lock Regions in Arria 10 FPGAs

If a Logic Lock region contains a register that interface with the I/O column, place the Logic Lock region so that the region covers the I/O column and the core logic, for better access to the I/O column adjacent to the outer column edge.
For high speed signal, you can get best results if you place the Logic Lock region on the outside of the I/O column, because the fitter is less likely to cross the column and incur delay.

7.3.7. Migrating Assignments between Quartus Prime Standard Edition and Quartus Prime Pro Edition

The Quartus Prime Pro Edition software does not support the Quartus Prime Standard Edition Logic Lock (Standard) assignments. Therefore, if you are migrating a design from Quartus Prime Standard Edition to Quartus Prime Pro Edition, you must convert the Logic Lock (Standard) assignments into Logic Lock assignments.

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Related Information

Replace Logic Lock Regions

In Quartus Prime Pro Edition User Guide: Getting Started

7.4. Defining Virtual Pins

A virtual pin is an I/O element that the Compiler temporarily maps to a logic element, rather than to a pin. The Compiler implements these virtual pins as LUTs.

By making assignments to virtual pins, you can ensure that the Fitter places those pins in the same device region as the corresponding internal nodes in the top-level module. You can apply the Virtual Pin option to successfully compile a Logic Lock module that has more pins than the target device. The Virtual Pin option can enable timing analysis of a design module that more closely matches the performance of the module after you integrate it into the top-level design.

You can create and assign virtual pins to an I/O element using the Virtual Pin logic option in the Assignment Editor ( Assignments ➤ Assignment Editor ).

Figure 132. Virtual Pin Logic Option in the Assignment Editor

When you apply the Virtual Pin assignment to an input pin, the pin no longer appears as an FPGA pin. Rather, the Compiler fixes the virtual pin to GND in the design. The virtual pin is not a floating node.

Use virtual pins only for I/O elements in lower-level design entities that become nodes after you import the entity to the top-level design; for example, when compiling a partial design. In the top-level design, you connect these virtual pins to an internal node of another module

You must assign the Virtual Pin logic option to an input or output pin. If you assign this option to a bidirectional pin, tri-state pin, or registered I/O element, synthesis ignores the assignment. If you assign this option to a tri-state pin, the Fitter inserts an I/O buffer to account for the tri-state logic; therefore, the pin cannot be a virtual pin. You can use multiplexer logic instead of a tri-state pin if you want to continue to use the assigned pin as a virtual pin. Do not use tri-state logic except for signals that connect directly to device I/O pins.

Note:

To display all assigned virtual pins in the design with the Node Finder, you can set Filter Type to Pins: Virtual . To access the Node Finder from the Assignment Editor, double-click the To field; when the arrow appears on the right side of the field, click and select Node Finder .

Related Information

Assigning Virtual Pins with a Tcl command on page 215

7.5. Using Logic Lock Regions in Combination with Design Partitions

You can optimize timing in a design by placing entities that share significant logical connectivity close to each other on the device.

By default, the Fitter attempts to place closely connected entities in the same area of the device. However, without constraint, this same placement is not assured for each compilation. You can use Logic Lock regions, together with design partitions, to ensure that logically connected entities retain optimal placement from one compilation to the next.

Using Logic Lock regions in combination with design partitions allows you to preserve the location and performance of a block, so that the Fitter focuses time and effort on other portions of the design.

For more details about these techniques, refer to Quartus Prime Pro Edition User Guide: Block-Based Design

To use the Design Partition Planner in conjunction with the Chip Planner to readily create partitions and define Logic Lock regions, follow these steps:

On the Compilation Dashboard, double-click Plan to compile through that Fitter stage, or run a full compilation.
Open the Chip Planner and the Design Partition Planner:

Click Tools ➤ Chip Planner
Click Tools ➤ Design Partition Planner

In the Chip Planner, double-click Report Design Partitions in the Tasks pane. The Chip Planner displays the physical locations of design partitions using the same colors as the entities in the Design Partition Planner.

Note:

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Figure 133. Design Partition Planner Overlaying Chip Planner

In the Chip Planner, click View ➤ Bird's Eye View
In the Design Partition Planner, drag all the larger entities out from their parents. Alternatively, you can right-click the entity and click Extract from Parent . The Chip Planner displays the physical placement of the entities shown in the Design Partition Planner, with consistent colors between the two tools. You can view physical placement in the Chip Planner and connectivity in the Design Partition Planner.
Identify entities that are unsuitable to place in Logic Lock regions:

The Chip Planner shows an entity to be physically dispersed over noncontiguous areas of the device.
The Design Partition Planner shows an entity to have a large number of connections to other entities.

Drag the entities that are unsuitable for placement in Logic Lock regions back to the parent entities. Alternatively, right-click the entity and click Collapse to Parent .
Create a partition for each remaining entity by right-clicking the entity, and then clicking Create Design Partition .
Create a Logic Lock region for each partition by right-clicking the partition, and then clicking Create Logic Lock Region .

Related Information

Quartus Prime Pro Edition User Guide: Block-Based Design
Quartus Prime Pro Edition User Guide: Partial Reconfiguration

7.5.1. Viewing Design Connectivity and Hierarchy

By default, when you open a compiled design, the Design Partition Planner displays the design as a single top-level entity, containing lower-level entities. If the Design Partition Planner has opened the design previously, the design appears in its last state.

Figure 134. Top-Level Entity in the Design Partition Planner

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To show connectivity between entities, extract entities from the top-level entity by dragging them into the surrounding white space, or by right-clicking an entity and clicking Extract from Parent on the shortcut menu. When you extract entities, Design Partition Planner draws the connection bundles between entities, showing the number of connections between pairs of entities.
To customize the appearance of connection bundles or to set thresholds for connection counts, click View ➤ Bundle Configuration , and set the necessary options in the Bundle Configuration dialog box.
To see bundles containing failing paths, open the Timing Analyzer, and then click View ➤ Show Timing Data in the Design Partition Planner. Bundles containing failing paths are displayed in red, as are entities having nodes that reside on failing paths.
To see detailed information about the connections in a bundle, right-click the bundle, and then click Bundle Properties to open the Bundle Properties dialog box.
To switch between connectivity display mode and hierarchical display mode, click View ➤ Hierarchy Display . Alternatively, click and hold the hierarchy button in the top-left corner of any entity to switch temporarily to a hierarchy display.

Figure 135. Partitioned Design with Connection Bundles

Figure 136. Hierarchy Display Button

7.6. Creating Clock Region Assignments in Chip Planner

You can easily create and manipulate clock regions in the Chip Planner and make clock assignments to the regions.

You can create a user-defined clock region assignment to ensure that a given global clock signal is available to resources in a certain area of the device throughout all design iterations. In instances of congestion involving global signal resources, you may specify a smaller clock region assignment to prevent a signal from using congested clock resources in other sectors.

If you create user-defined clock regions and subsequently compile the design, those user-defined clock regions become Fitter-defined clock regions, and are read-only.

Summary of User-Defined Clock Region Feature Support

| Feature | Clock Region Support | |-------------------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------| | Shapes of clock regions | Limited to rectangular regions that snap to clock sector grids. | | Peripheral element assignments | Limited to clocking design elements. | | Clock region name | Identified by the source clocking design element. | | Support for multiple instances per region | Create one region per clock design element, and then specify the same definition for multiple clock design elements to assign to the same clock region. |

Using Clock Region Assignments in Stratix 10 and Agilex FPGA Portfolio Devices

You can constrain clock regions to a rectangle whose dimensions are defined by the sector grid, as seen in the Clock Sector Region layer of the Chip Planner. The rectangle is defined by the coordinates of its bottom-left and top-right corners. For example, SX0, SY0, SX1, SY1 constrains the clock to a 2 × 2 region, from the bottom left of sector 0,0 to the top right of sector 1,1.

You can alternatively specify the bounding rectangle in chip coordinates, for example X37 Y181 X273 Y324 . However, you should sector-align such a constraint. The Fitter automatically snaps to the smallest sector-aligned rectangle that encompasses the original assignment.

7.6.1. Creating Clock Assignments in Chip Planner

To create clock assignments with the Chip Planner, follow these steps:

Select the Create Clock Assignment button, or click View ➤ Clock Assignments ➤ Create Clock Assignment .

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Figure 137. Create Clock Assignment Button on Chip Planner Toolbar

Figure 138. Newly Created Clock Region

Click and drag the mouse on the Chip Planner floorplan to draw a clock region of your preferred location and size. The region that you draw snaps to the smallest clock sector capable of containing the region. Orange clock sector grids help visualize positioning of the clock region relative to clock sectors.
Assign a clock signal from the context menu. A clock symbol in the region title bar identifies a clock region. The clock region is unassigned until you assign a clock signal from the context menu.

7.6.1.1. Clock Assignment Properties

The Clock Assignment Properties pane displays properties of the selected clock assignment.

By default, the Clock Assignment Properties pane appears on a tab at the right side of the Chip Planner.

Figure 139. Clock Assignment Properties Pane

7.6.2. Resizing a Clock Assignment in Chip Planner

To resize an existing clock assignment in the Chip Planner, follow these steps:

Figure 140. Clock Assignment in Chip Planner

Select an existing clock assignment in the Chip Planner floorplan. Handles appear on each side of the region and at the corners.
Position the crosshairs over the handle of your choice and the resize mouse cursor appears.
Hold the left mouse button and drag the resize cursor to expand or shrink the boundary of the clock assignment. When you release the mouse button, the clock assignment boundaries snap to the nearest containing clock sector grid.

7.6.3. Moving a Clock Assignment in Chip Planner

To move a clock assignment in the Chip Planner, follow these steps:

Select the clock assignment in the Chip Planner floorplan.
Position the crosshairs over the clock assignment title bar and the move cursor appears.
Hold the left mouse button and drag the clock assignment to the new location.

7.6.4. Deleting a Clock Region Assignment in Chip Planner

To delete a clock region assignment in the Chip Planner, follow these steps:

Select the clock assignment that you want to delete in the Chip Planner floorplan.
Right-click the clock assignment title bar to display the context menu, or select View from the main menu bar.
Click Clock Assignments ➤ Delete Clock Assignment .
You are prompted to confirm that you want to delete the selected clock assignment. Click Yes to confirm the deletion.

The specified clock region assignment is deleted from the system.

7.6.5. Assigning a Clock Signal to a Clock Region in Chip Planner

To assign a clock signal to a clock region in the Chip Planner, follow these steps:

Right-click the clock assignment title bar to display the context menu, or select View from the main menu bar in the Chip Planner.
Click Clock Assignments ➤ Set Clock Signal Name .
In the Set Clock Signal Name dialog box, browse to or type the desired clock signal name.
Click Ok .

The system renames the clock assignment according to the name of the specified clock signal.

7.7. Scripting Support

You can run the commands and specify the settings described in this chapter as part of a Tcl script. You can also run some commands at a command prompt. The following topics describe the commands.

Related Information

Quartus Prime Pro Edition User Guide: Scripting

7.7.1. Creating Logic Lock Assignments with Tcl commands

The Quartus Prime software supports Tcl commands to create or modify Logic Lock assignments.

Note:

Specify node names by using the full hierarchy path to the node.

Create or Modify a Placement Region

You can create the Logic Lock region from the GUI, or add the region directly to the QSF. The QSF entry contains the X/Y coordinates of the vertices and the Placement Region name.

The following assignment creates a new placement region with bounding box coordinates X46 Y36 X65 Y49 :

set_instance_assignment -name PLACE_REGION "X46 Y36 X65 Y49" -to <node names>

You can use the same command format to modify an existing assignment.
To specify a non-rectangular or disjoint region, use a semicolon ( ; ) as the delimiter between two or more bounding boxes.
Assign multiple instances to the same region with multiple PLACE_REGION instance assignments.

Create or Modify a Routing Region

The following assignment creates a routing region with bounding box coordinates X5 Y5 X30 Y30 :

set_instance_assignment -name ROUTE_REGION -to <node names> "X5 Y5 X30 Y30"

You can use the same command format to modify an existing assignment.
All instances with a routing region assignment must have a respective placement region; the routing region must fully contain the placement region.

Specify a Region as Reserved

The following assignment reserves an existing region:

set_instance_assignment -name <instance name> RESERVE_PLACE_REGION -to <node names> ON

You can only reserve placement regions.

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Specify a Region as Core Only

By default, the Quartus Prime Pro Edition software includes pins in Logic Lock assignments. To specify a region as core only (that is, periphery logic in the instance that is not constrained), use the following assignment:

set_instance_assignment -name <instance name> CORE_ONLY_PLACE_REGION -to <node names> ON

Related Information

Defining Logic Lock Regions on page 191

7.7.2. Assigning Virtual Pins with a Tcl command

Use the following Tcl command to turn on the virtual pin setting for a pin called my_pin :

set_instance_assignment -name VIRTUAL_PIN ON -to my_pin

Related Information

Defining Virtual Pins on page 205

7.7.3. Logic Lock Region Assignment Examples

The following examples show the syntax of Logic Lock region assignments in the .qsf file. Optionally, you can enter these assignments in the Assignment Editor, the Logic Lock Regions Window, or the Chip Planner.

Example 1. Assign Rectangular Logic Lock Region

Assigns a rectangular Logic Lock region to a lower left corner location of (10,10), and an upper right corner of (20,20) inclusive.

set_instance_assignment -name PLACE_REGION -to a|b|c "X10 Y10 X20 Y20"

Example 2. Assign Non-Rectangular Logic Lock Region

Assigns instance with full hierarchical path " x|y|z " to non-rectangular L-shaped Logic Lock region. The software treats each set of four numbers as a new box.

set_instance_assignment -name PLACE_REGION -to x|y|z "X10 Y10 X20 Y50; X20 Y10 X50 Y20"

Example 3. Assign Subordinate Logic Lock Instances

By default, the Quartus Prime software constrains every child instance to the Logic Lock region of its parent. Any constraint to a child instance intersects with the constraint of its ancestors. For example, in the following example, all logic beneath ' a|b|c|d ' constrains to box (10,10), (15,15) , and not (0,0), (15,15) . This result occurs because the child constraint intersects with the parent constraint.

set_instance_assignment -name PLACE_REGION -to a|b|c "X10 Y10 X20 Y20" set_instance_assignment -name PLACE_REGION -to a|b|c|d "X0 Y0 X15 Y15"

Example 4. Assign Multiple Logic Lock Instances

By default, a Logic Lock region constraint allows logic from other instances to share the same region. These assignments place instance c and instance g in the same location. This strategy is useful if instance c and instance g are heavily interacting.

set_instance_assignment -name PLACE_REGION -to a|b|c "X10 Y10 X20 Y20" set_instance_assignment -name PLACE_REGION -to e|f|g "X10 Y10 X20 Y20"

Example 5. Assigned Reserved Logic Lock Regions

Optionally reserve an entire Logic Lock region for one instance and any of its subordinate instances.

set_instance_assignment -name PLACE_REGION -to a|b|c "X10 Y10 X20 Y20" set_instance_assignment -name RESERVE_PLACE_REGION -to a|b|c ON # The following assignment causes an error. The logic in e|f|g is not # legally placeable anywhere: # set_instance_assignment -name PLACE_REGION -to e|f|g "X10 Y10 X20 Y20" # The following assignment does *not* cause an error, but is effectively # constrained to the box (20,10), (30,20), since the (10,10),(20,20) box is reserved # for a|b|c set_instance_assignment -name PLACE_REGION -to e|f|g "X10 Y10 X30 Y20"

7.8. Analyzing and Optimizing the Design Floorplan Revision History

The following revision history applies to this chapter:

Table 51. Document Revision History

| Document Version | Quartus Prime Version | Changes | |--------------------|-------------------------|-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | | | • Replaced missing graphics in Viewing Fan-In and Fan-Out in Chip Planner . • Replaced missing graphics in Viewing Design Connectivity and Hierarchy . • Replaced missing graphics in Subtracting Shape from Logic Lock Region . | | 2023.04.03 | 23.1 | • Updated product family name to "Intel Agilex 7." | | 2022.09.26 | 22.3 | • Updated chapter for new Compilation Regions tab in the Logic Lock Regions window. This read-only tab displays the properties of any Logic Lock regions contained in a .qdb file in the current project. | | 2022.01.07 | 21.4 | • Added Properties tab information to Viewing Architecture-Specific Design Information topic. • Added Design Assistant information to Using Logic Lock Regions in the Chip Planner topic. • Added new Viewing the Location and Utilization of Device Resources in Chip Planner topic. • Added new Viewing Module Placement by Cross-Probing to Chip Planner topic. • Added new Finding Design Elements in the Chip Planner topic. • Added new Find In Options topic. | | 2019.07.30 | 19.3.0 | Added new Using User-Defined Clock Regions in the Chip Planner section. | | 2019.07.01 | 19.1.0 | Added new "Snapping to a Region" topic that describes the Snap Logic Lock Region to option. | | 2019.04.01 | 19.1.0 | • Added new "Viewing Selected Contents" topic that describes a new report listing selected design elements. | | 2018.09.24 | 18.1.0 | • Added topic: Viewing Clock Sector Utilization • Added topic: Viewing the Source and Destination of Placed Nodes . • Renamed topic: Generating Fan-In and Fan-Out Connections to Viewing Fan-In and Fan-Out Connections of Placed Resources . | | 2018.05.07 | 18.0.0 | • Added recommendations for using iterative methods for floorplanning. | | 2017.11.06 | 17.1.0 | • Changed instances of LogicLock Plus to Logic Lock . • Added support for auto-sized Logic Lock regions. • Added support for empty Logic Lock regions. • Added topics: Considerations on Using Auto Sized Regions, Creating Partitions and Logic Lock Regions with the Design Partition Planner and Chip Planner. | | 2017.05.08 | 17.0.0 | • Chapter reorganization and content update. • Added figures: Clock Regions, Path List in the Locate History Window, Show Physical Routing, Using the Add Rectangle Feature, Using the Subtract Rectangle Feature, Creating a Hole in a LogicLock Region, Noncontiguous LogicLock Region, Routing Regions, Logic Placed Outside of an Empty Region. • Updated figures: HSSI Channel Blocks, Highlight Routing, High-Speed and Low Power Tiles in an Arria 10 Device, Show Delays Highlight Routing, Viewing Assignments in the Chip Planner, LogicLock Plus Regions Window, Using the Merge LogicLock Plus Region Command. • Created topics: Adding Rectangle to a LogicLock Plus Region , Subtracting Rectangle from a LogicLock Plus Region . • Moved topic: Viewing Critical Paths to Timing Closure and Optimization chapter and renamed to Critical Paths . continued... |

8. Using the ECO Compilation Flow

In a typical FPGA project development cycle, the specification of the programmable logic portion of the design can change during the design process. The Quartus Prime software supports these last-minute, targeted engineering change orders (ECOs), even after full compilation is complete.

ECOs typically occur during the design verification stage. For example, during verification you may determine that the design requires a small change, such as a netlist connection change, correcting a LUT logic error, or placing a node in a new location. Implementing an ECO change, rather than changing RTL and fully recompiling the design, requires significantly less time, and changes only the affected logic.

You specify the ECO commands in a Tcl script using the ::quartus::eco package.

The Quartus Prime Pro Edition software supports ECOs for Stratix 10 and Agilex FPGA portfolio devices only.

Note:

8.1. ECO Compilation Flow

Identify an ECO modification you want to make in a compiled design.
Determine if ECO commands support the change, by reviewing ECO Commands on page 223 and ECO Command Limitations on page 231.
Create a Tcl script, as ECO Tcl Script Example on page 221 shows.
Before running ECO compilation, click Project ➤ Archive Project and archive the compilation database and output file set.
Click Processing ➤ Start ➤ Perform ECO Compilation .
Specify the ECO Tcl Script file, and click OK . The Fitter processes the ECO commands and updates the finalized netlist. The Fitter generates an error if you specify any commands incorrectly. The changes apply when the Fitter processing completes.
View the ECO results in post-fit analysis tools, such as the Compilation Report, Timing Analyzer, Netlist Viewer, or Chip Planner. To view ECO changes in the Fitter report, click Processing ➤ Compilation Report ➤ Fitter ➤ ECO Changes .

*Other names and brands may be claimed as the property of others.

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Figure 141. Example of ECO Changes Report

As an alternative to the GUI methods, you can use the following commands to run the ECO Tcl scripts. If running from command line, any active Quartus Prime GUI application does not refresh. Close and reopen the project to refresh the GUI.

$ quartus_fit -s load_package eco project_open <project_name> eco_load_design ... eco_commit_design project_close

Note: If you rerun the Fitter on a design after implementing an ECO, the Fitter overwrites the ECO changes. Update RTL, IP parameters, and recompile the design to permanently implement the ECO changes.

8.2. ECO Tcl Script Example

The following shows an example ECO Tcl script that places existing nodes in new locations:

Figure 142. ECO Tcl Script Example

8.3. Viewing ECO Compilation Reports

The Compiler generates a report showing the details of each ECO compilation that you run successfully. You can view the report contents in the ECO Changes report under Fitter in the Compilation Report.

Figure 143. Example of ECO Changes Report

Alternatively, you can view this data in the generated fit.eco file. The Compiler organizes the report output according to the category of ECO change, such as Placement Changes. The table specifies the "Changes in Previous ECO Runs" and "Changes in Current ECO Run".

Figure 144. ECO Report Example

Locate nodes from the Fitter's ECO reports to confirm ECO changes.

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Figure 145. Locate Node from Fitter ECO Reports

8.4. ECO Commands

The Quartus Prime Pro Edition software supports the following ECO commands:

Note:

Check available arguments by running <eco_command> -h|help|long_help .

ECO Command Quick Reference on page 224

make_connection on page 224

remove_connection on page 225

modify_lutmask on page 226

adjust_pll_refclk on page 226

modify_io_slew_rate on page 227

modify_io_current_strength on page 227

modify_io_delay_chain on page 227

create_new_node on page 228

remove_node on page 229

place_node on page 229

unplace_node on page 230

create_wirelut on page 230

8.4.1. ECO Command Quick Reference

Table 52. ECO Command Quick Reference

| ECO Change | ECO Commands | |-------------------------------------------|---------------------------------------------------------------------------------------------------------| | Route | make_connection -from <src> -to <dst> -port <port> remove_connection -from <src> -to <dst> -port <port> | | Tie-Off | make_connection -tieoff <VCC/GND> -to <node> -port <port> | | Lutmask | modify_lutmask -to <node> [-eqn <lut equation>] [-mask 0x00] | | Slew Rate | modify_io_slew_rate <value> -to <pin_name> | | Current Strength | modify_io_current_strength <value> -to <pin_name> | | Delay Chains | modify_io_delay_chain <value> -type <io_type> -to <pin_name> | | Update MIF | update_mif_files | | IOPLL Ref Clock (Stratix 10 devices only) | adjust_pll_refclk -to <pll name> -refclk <freq> | | Create New Node | create_new_node -type <LUT|FF> -name <name> | | Remove Node | remove_node -name <name> | | Place Node | place_node -name <name> [-location <location>] | | Unplace Node | unplace_node -name <name> | | Create Wirelut | create_wirelut -from <src> -to <dst> -port <port> [-location <location>] |

8.4.2. make_connection

Description

Connects the source signal to the destination block port. If the port has an existing connection, the command removes the previous connection and connects it to the signal you specify. The actual routing change occurs implicitly when appropriate. You can locate node names by right-clicking a node in Netlist Viewer, and then clicking Properties .

make_connection also supports adding connections from and to Hyper-Registers. In the case of Hyper-Registers, the command first disconnects the destination port, before making a new connection. You can the run the make_connection command to specify a replacement signal source or destination.

If a port is shared among multiple RAM slice atoms, then the ECO Fitter automatically updates all relevant atoms, and reports them accordingly.

8. Using the ECO Compilation Flow

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Usage

The following example connects top|a_out to the D input port of node top|x .

make_connection -from top|a_out -to top|x -port D

Arguments

from Output net of the source block of the new connection.

to Name of the destination block.

port The input port name of the destination block.

Options

tieoff To explicitly tie off an input port to VCC or GND . VCC or GND Example: make_connection -tieoff VCC -to {node1} -port DATAA

to Name of the destination block.

port The input port name of the destination block.

8.4.3. remove_connection

Description

Disconnects the src signal from the destination block port. The actual routing change occurs implicitly. You can locate node names by right-clicking a node in Netlist Viewer, and then clicking Properties .

If a port is shared among multiple RAM slice atoms, then the ECO Fitter automatically updates all relevant atoms, and reports them accordingly.

Usage

The following example disconnects top|a_out from the D input port of node top|x , and set top|x:D to a disconnected state.

remove_connection -from top|a_out -to top|x -port D

Arguments

from Output net of the source block of the current connection.

to Name of the destination block.

port The input port name of the destination block.

8.4.4. modify_lutmask

Description

Modifies the lutmask of the matching destination node, with the lutmask value ( -mask ) in binary or hexadecimal, or with the equivalent lutmask value ( -eqn ) computed from specified logical equation.

Usage

The following example disconnects top|a_out from the D input port of node top|x , and set top|x:D to a disconnected state.

modify_lutmask -to top|lut_c -eqn {a&b&c} modify_lutmask -to top|lut_a -mask 0xFF00FF00 modify_lutmask -to top|lut_b -mask 0b111111111001010

Arguments

eqn The logical equation of the inputs ( A, B, C, D, E, F ). The supported lexical tokens include AND('&') , OR('|') , XOR('^') , NOT('!') , OPEN_BRACE('(') , CLOSE_BRACE(')') . Specify -mask or -eqn

to Destination atom name.

mask The lutmask value to be modified in binary or hexadecimal format. Specify -mask or -eqn

When you view the lutmask equations in the Resource Property Viewer, the equations display in terms of F0/F1/F2/F3 LUTs for A , B , C and D inputs. For LUTs also using E or F inputs, you must combine these sub-functions using the connectivity that the ALM diagram shows for the E and F muxes.

Note:

8.4.5. adjust_pll_refclk

Description

Changes the IOPLL frequencies by modifying the input reference clock frequency. The following stipulations apply:

Maintain the original refclk and outclk ratios.
The IOPLLs you change cannot generate IP clocks.
Cascaded IOPLLs must connect directly (no clock gates in between them).
IOPLLs cannot be in 'nondedicated' compensation modes.
For all IOPLLs, outclks duty cycle equals 50 and phase shift equals 0.
No support for Agilex FPGA portfolio devices.

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8. Using the ECO Compilation Flow

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Usage

The following example adjusts the pll_main IOPLL by modifying the input clock frequency to 100 MHz.

adjust_pll_refclk -to {*pll_main*} -refclk 100

Arguments

to Instance name of upstream IOPLL that you want to adjust. Escape any [ or ] characters in the target name.

refclk New refclk frequency value in MHz.

8.4.6. modify_io_slew_rate

Description

Implements the I/O pin slew setting rate that you specify for the I/O pin.

Usage

modify_io_slew_rate 1 -to top|ipin

Arguments

to Instance name of destination pin that you want to modify.

8.4.7. modify_io_current_strength

Description

Implements the change to the I/O pin current strength setting that you specify for the I/O pin.

Usage

modify_io_current_strength 3mA -to top|ipin

Arguments

to Instance name of the destination pin that you want to modify.

8.4.8. modify_io_delay_chain

Description

Implements the change to the delay chain settings that you specify for the I/O pin.

Usage

modify_io_delay_chain 3 -to top|ipin -type input

Arguments

type Specifies one of the following I/O types: input , output , oe , io_12_lane_input , io_12_lane_input_strobe

to Instance name of I/O pin that you want to modify the delay chain settings.

8.4.9. create_new_node

Description

Creates a LUT cell or flip-flop in the design netlist. The following use cases apply:

Adding a gate to fix a logic bug.
Adding a wire LUT to help add hold delay.
Creates a new flip-flop or flip-flops where needed.

The name of the new node is hierarchical. Therefore, when creating node a|b|c|d , you must ensure that hierarchy a|b|c exists in the netlist. If the source or destination node lies under a partition, the new LUT inserts under that partition.

Note: This command does not support extended or arithmetic LUTs.

After creating the new node, you can run the following commands to connect, modify the lutmask, or place the new node:

Run make_connection to connect to the new LUT's DATA inputs and output port.
Run modify_lutmask to change the lutmask for the new LUT.
Run place_node to place (and subsequently route) the new LUT.

This flow ensures that all routing requirements are analyzed when determining a legal placement for the new node.

Usage

The following example creates a new_lut LUT node with input ports DATAA and DATAB , and with outputs connected accordingly. modify_lutmask the modifies the lutmask to perform A&B logic. place_node next places the new LUT. The connections route after node placement is complete.

create_new_node -name new_lut -type lut make_connection -from src_a -to new_lut -port DATAA make_connection -from src_b -to enew_lut -port DATAB make_connection -from new_lut -to dst_reg -port D modify_lutmask -to new_lut -eqn A&B place_node -name new_lut

8. Using the ECO Compilation Flow

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To connect to a new flip-flop node that you create, use the make_connection command to connect to the flip-flop data port ( D ), and control ports ( CLK , ENA , SCLR , CLRN ), and from its output Q port. You must place the new flip-flop node with the place_node command. The connections are automatically routed after the place_node command.

create_new_node -name my_ff -type ff make_connection -from reg0 -to my_ff -port D make_connection -from clk -to my_ff -port CLK make_connection -from my_ff -to reg1 -port D place_node -name my_ff -location 'X10 Y10 X10 Y10'

Arguments

name Name of the new LUT of flip-flop node.

8.4.10. remove_node

Description

Removes a LUT cell or flip-flop from the design netlist.

Usage

The following example deletes a flip-flop node with the name ff1 :

remove_node -name ff1

Arguments

name Name of the LUT of flip-flop node to delete.

8.4.11. place_node

Description

Places the node that you specify in a location that the ECO Fitter selects. Optionally, you can specify the location argument to assign a specific device region location. You can also run this command for nodes already placed by the Fitter.

place_node also supports placement of newly added or existing flip-flops. place_node does not support Hyper-Register locations.

Usage

The following examples show three placement cases. For node1 , the ECO Fitter determines the placement location. For node2 , the command specifies the exact LAB location constraint. For node3 , the command specifies a placement region constraint.

place_node -name node1 # let ECO Fitter decide placement place_node -name node2 -location FF_X20_Y60_N17 # place node at specific location place_node -name node3 -location 'X10 Y10 X20 Y20' # place node in region place_node -name my_ff -location 'X10 Y10 X10 Y10' # place flip-flop in region

Arguments

name Name of the node.

$$location Device region coordinates (X1 Y1 X10 Y10)(X1 Y1) (FF_X20_Y60_N17) .$$

8.4.12. unplace_node

Description

Unplaces the node that you specify. unplace_node supports moving larger clouds of logic. To simplify the process of moving a larger cloud of logic, such as an entire ALM, you can first unplace all of the nodes. The Fitter does not perform placement legality checking until you re-place the final ALM cell.

Usage

The following example unplaces a node with the name ff1 :

Arguments

name Name of the node to unplace.

8.4.13. create_wirelut

Description

Creates and inserts a wire LUT node in the connection that you specify. The ECO Fitter places the new LUT and routes the modified connections automatically. Optionally, you can specify the location argument to specify a particular device region location constraint.

create_wirelut also supports adding connections from and to Hyper-Registers. In the case of Hyper-Registers, the command first disconnects the destination port, before making a new connection. You can the run the create_wirelut command to specify a replacement signal source or destination.

If a port is shared among multiple atoms (for example, RAM), then the ECO Fitter automatically updates all relevant atoms, and reports them accordingly.

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Usage

The following example creates the my_wirelut wire LUT, connects my_wirelut output to the D input port of dest_node , and connects the output of src_output to the input port of the wire LUT. Finally, the ECO Fitter places the new node within region ( 20, 20 ) to ( 40, 40 ) and routes automatically.

create_wirelut -name my_wirelut -from src_output -to dest_node \ -port D -location "X20 Y20 X40 Y40"

Arguments

name

Name of the node.

From

Source of the connection.

Name of destination node.

Port

Input port name of destination node.

location Device region coordinates ( X1 Y1 X10 Y10 ) (X1 Y1)

(FF_X20_Y60_N17) .

8.5. ECO Command Limitations

The ECO commands have the following limitations due to connection dependencies within Altera devices.

You cannot use ECO commands to modify dedicated connections.
You cannot modify dedicated connections within a single ALM. This limitation applies to direct connections between LUT and flip-flop nodes.
You can connect from or to a Hyper-Register. However, you cannot remove connections from or to a Hyper-Register because removing a connection from a Hyper-Register would leave the routing dangling. As an alternative, you can use make_connection to change a Hyper-Register connection immediately, without removing the previous connection first.
Use of the place_node command with location arguments does not overwrite Partial Reconfiguration region constraints.
If a LAB already has the maximum number of legal connections where a node is placed, the place_node or make_connection commands can fail, preventing the connection to the first placed node that cannot be legalized. You can then either move the original node to a different location, or move other nodes from the LAB to free up routing resources.
The Fitter may fail to apply some I/O related ECO modifications, such as modify_io_slew_rate , modify_io_current_strength , and modify_io_delay_chain , if called using a command-line Tcl script or in interactive context. That is, any case that calls the eco_load_design command directly. To ensure all I/O modifications are applied successfully, use the standard ECO Tcl script approach this document describes.

The recommended order for creating and placing new LUTs or new flipflops is:

Create the node by using the create_new_node command.
Make connections to and from the node by using the make_connection command.
Update the lutmask by using the modify_lutmask command.
Place the node by using the place_node command.

This flow ensures that analysis includes all routing requirements when determining a legal placement for the new node. For example:

Create a new LUT in an exact location

set lut_name new_lut create_new_node -name $lut_name -type lut make_connection -from input1 -to $lut_name -port DATAA make_connection -from input2 -to $lut_name -port DATAB make_connection -from $lut_name -to output_dest -port DATAD modify_lutmask -to $lut_name -eqn {A&B} place_node -name $lut_name -location 'X80 Y80 X85 Y95'

Create a new Flipflop in an exact location

set ff_name new_ff create_new_node -name $ff_name -type ff make_connection -from input1 -to $ff_name -port DATAA make_connection -from input2 -to $ff_name -port DATAB make_connection -from $ff_name -to output_dest -port DATAD modify_lutmask -to $ff_name -eqn {A&B} place_node -name $ff_name -location 'X80 Y80 X85 Y95'

To minimize issues with name matching caused by escaped characters, it can be useful to surround entity names with {} characters, instead of "" . This technique is particularly useful if entity names contain backslashes or any other special characters.

Note:

8.6. Interactive ECO Fitting

The quartus_fit executable supports ECO changes in an interactive shell through quartus_fit -s .

In an interactive context, the ECO Fitter legalizes the changes, when appropriate. For example, for make_connection changes immediately after node creation, the Fitter does not attempt to route the connections immediately; rather, the Fitter waits until after the placement of the node prior to routing.

8.6.1. eco_load_design and eco_commit_design Commands

Description

eco_load_design -loads the final netlist in the ECO context.
eco_commit_design -commits the ECO modified netlist to disk while running in interactive mode.

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Usage

The following example shows an interactive ECO session to modify the lut_x lutmask for project top . If the ECO modifications are legal, the eco_commit_design command commits the final netlist.

$ quartus_fit -s >> load_package eco >> project_open top >> eco_load_design >> modify_lutmask -to lut_x -eqn B&C # some ECO changes >> eco_commit_design >> project_close

8.7. Using the ECO Compilation Flow Revision History

The following revision history applies to this chapter:

Table 53. Document Revision History

9. Quartus Prime Pro Edition Design Optimization User Guide Archives

For the latest and previous versions of this user guide, refer to Quartus Prime Pro Edition User Guide: Design Optimization. If an IP or software version is not listed, the user guide for the previous IP or software version applies.

*Other names and brands may be claimed as the property of others.

A. Quartus Prime Pro Edition User Guides

Refer to the following user guides for comprehensive information on all phases of the Quartus Prime Pro Edition FPGA design flow.

Related Information

Quartus Prime Pro Edition User Guide: Getting Started

Introduces the basic features, files, and design flow of the Quartus Prime Pro Edition software, including managing Quartus Prime Pro Edition projects and IP, initial design planning considerations, and project migration from previous software versions.

Quartus Prime Pro Edition User Guide: Platform Designer

Describes creating and optimizing systems using Platform Designer, a system integration tool that simplifies integrating customized IP cores in your project. Platform Designer automatically generates interconnect logic to connect intellectual property (IP) functions and subsystems.

Quartus Prime Pro Edition User Guide: Design Recommendations

Describes best design practices for designing FPGAs with the Quartus Prime Pro Edition software. HDL coding styles and synchronous design practices can significantly impact design performance. Following recommended HDL coding styles ensures that Quartus Prime Pro Edition synthesis optimally implements your design in hardware.

Quartus Prime Pro Edition User Guide: Design Compilation

Describes set up, running, and optimization for all stages of the Quartus Prime Pro Edition Compiler. The Compiler synthesizes, places, and routes your design before generating a device programming file.

Quartus Prime Pro Edition User Guide: Design Optimization

Describes Quartus Prime Pro Edition settings, tools, and techniques that you can use to achieve the highest design performance in Altera FPGAs. Techniques include optimizing the design netlist, addressing critical chains that limit retiming and timing closure, optimizing device resource usage, device floorplanning, and implementing engineering change orders (ECOs).

Quartus Prime Pro Edition User Guide: Programmer

Describes operation of the Quartus Prime Pro Edition Programmer, which allows you to configure Altera FPGA devices, and program CPLD and configuration devices, via connection with an Altera FPGA download cable.

Quartus Prime Pro Edition User Guide: Block-Based Design

Describes block-based design flows, also known as modular or hierarchical design flows. These advanced flows enable preservation of design blocks (or logic that comprises a hierarchical design instance) within a project, and reuse of design blocks in other projects.

*Other names and brands may be claimed as the property of others.

UG-20133 | 2026.01.07

· Quartus Prime Pro Edition User Guide: Partial Reconfiguration

Describes Partial Reconfiguration, an advanced design flow that allows you to reconfigure a portion of the FPGA dynamically, while the remaining FPGA design continues to function. Define multiple personas for a particular design region, without impacting operation in other areas.

· Quartus Prime Pro Edition User Guide: Third-party Simulation

Describes RTL- and gate-level design simulation support for third-party simulation tools by Aldec*, Cadence*, Siemens EDA, and Synopsys that allow you to verify design behavior before device programming. Includes simulator support, simulation flows, and simulating Altera IP.

· Quartus Prime Pro Edition User Guide: Third-party Synthesis

tools by Siemens EDA, and Synopsys. Includes design flow steps, generated file descriptions, and synthesis guidelines.

Describes support for optional synthesis of your design in third-party synthesis

Quartus Prime Pro Edition User Guide: Third-party Logic Equivalence Checking Tools

Describes support for optional logic equivalence checking (LEC) of your design in third-party LEC tools by OneSpin*.

Quartus Prime Pro Edition User Guide: Debug Tools

Describes a portfolio of Quartus Prime Pro Edition in-system design debugging tools for real-time verification of your design. These tools provide visibility by routing (or 'tapping') signals in your design to debugging logic. These tools include System Console, Signal Tap logic analyzer, system debugging toolkits, In-System Memory Content Editor, and In-System Sources and Probes Editor.

Quartus Prime Pro Edition User Guide: Timing Analyzer

Explains basic static timing analysis principals and use of the Quartus Prime Pro Edition Timing Analyzer, a powerful ASIC-style timing analysis tool that validates the timing performance of all logic in your design using an industrystandard constraint, analysis, and reporting methodology.

· Quartus Prime Pro Edition User Guide: Power Analysis and Optimization

Describes the Quartus Prime Pro Edition Power Analysis tools that allow accurate estimation of device power consumption. Estimate the power consumption of a device to develop power budgets and design power supplies, voltage regulators, heat sink, and cooling systems.

· Quartus Prime Pro Edition User Guide: Design Constraints

Describes timing and logic constraints that influence how the Compiler implements your design, such as pin assignments, device options, logic options, and timing constraints. Use the Interface Planner to prototype interface implementations, plan clocks, and quickly define a legal device floorplan. Use the Pin Planner to visualize, modify, and validate all I/O assignments in a graphical representation of the target device.

· Quartus Prime Pro Edition User Guide: PCB Design Tools

and Cadence*. Also includes information about signal integrity analysis and

Describes support for optional third-party PCB design tools by Siemens EDA

simulations with HSPICE and IBIS Models.

· Quartus Prime Pro Edition User Guide: Scripting

Describes use of Tcl and command line scripts to control the Quartus Prime Pro Edition software and to perform a wide range of functions, such as managing projects, specifying constraints, running compilation or timing analysis, or generating reports.

Metadata

SourceQuartus Prime Pro: Timing Closure

Tokens160,638

Chunks471

Chunks (471)

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## Answers to Top FAQs: Updated for Quartus ® Prime Design Suite: 25.3.1 This document is part of a collection - Quartus ® Prime Pro Edition User Guides - Combined PDF link - Q What are th...

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## Contents | 1. Answers to Top FAQs...................................................................................................... 6 | 1. Answers to Top FAQs.............................

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## Contents When to Use the Netlist Viewers: Analyzing Design Problems | ....................................17 ...

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## Contents View LUT Representations in the Technology Map Viewer...............................35 | ...

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## Contents | 4. Netlist Optimizations and Physical Synthesis................................................................42 | ...

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## Contents | 54 | | 5.2.2. I/O Pin Utilization or Placement...............

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## Contents Revise and Recompile...............................................................................75 | ...

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## Contents | 6.5.7. Aggregating and Comparing Compilation Results with Exploration Dashboard.126 | ...

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## Contents Viewing Design Elements in Chip Planner...................................................170 | ...

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## Contents Resizing a Clock Assignment in Chip Planner..............................................212 | ...

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## Contents | 8.1. ECO Compilation Flow.........................................................................................220 | | |--------------------------------------------------------...

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## 1. Answers to Top FAQs | Q | What are the optimization trade-offs? | A | Optimization Trade-Offs and Limitations on page 67 | |-----|-------------------------------------------|-----|---...

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## 2. Design Optimization Overview In the early stages of FPGA design development, you typically focus on meeting your timing requirement, resource usage, and power consumption goals. After meeting t...

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## 2.1. Initial FPGA Device Considerations Quartus Prime Pro Edition User Guide: Design Compilation All Altera ® FPGAs have a unique timing model that describes the delay information between all p...

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## 2.1.1. Device Migration Considerations If you anticipate that you might later migrate your design to a different target device later in the design cycle (for example, a larger or faster device), y...

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## 2.2. Initial Compiler Settings Migration Devices Dialog Box In Quartus Prime Help Your design compilation results can vary significantly, depending on the initial assignments and settings that ...

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## 2.2.1. Initial I/O Assignment Guidelines UG-20133 | 2026.01.07 Click Assignments ➤ Settings ➤ Compiler Settings ➤ Optimization Mode to adjust the Compiler's effort on Performance , Area , Routab...

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## 2.2.2. Initial Timing Constraint Guidelines Quartus Prime Pro Edition User Guide: Design Constraints In Quartus Prime Pro Edition User Guide: Design Constraints Before running initial compilat...

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## 2.3. Optimization Trade-Offs and Limitations - Using the Quartus Prime Timing Analyzer In Quartus Prime Pro Edition User Guide: Timing Analyzer - Quartus Prime Timing Analyzer Cookbook Design op...

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## Table 1. Design Optimization Trade-Off Examples | Trade-off | Comments ...

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## 2.3.1. Area Reduction Trade-Offs By default, the Quartus Prime Fitter might physically spread a design over the entire device to meet the set timing constraints. If you prefer to optimize your des...

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## 2.3.2. Critical Path Delay Reduction Trade-Offs - Area Optimization on page 49 - Netlist Optimizations and Physical Synthesis on page 42 To meet complex timing requirements involving multiple cl...

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## 2. Design Optimization Overview UG-20133 | 2026.01.07 Turn on only those options that help you keep reasonable compilation times and resource usage. Alternately, you can modify the HDL to man...

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## 2.3.3. Power Consumption Reduction Trade-Offs Optimize Critical Paths on page 67 The Quartus Prime software has features that help reduce design power consumption. The power optimization options...

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## 2.3.4. Compilation Time Trade-Offs Power Optimization In Quartus Prime Pro Edition User Guide: Power Analysis and Optimization Many Fitter settings influence compilation time. Most of the defau...

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## 2.4. Design Visualization and Optimization Tools Quartus Prime Pro Edition User Guide: Design Compilation The Quartus Prime software provides various tools to help you visualize and optimize the...

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## 2.4.1. Design Visualization Tools The Quartus Prime software provides tools that display different graphical representations of your design to help you visualize and optimize placement, connectivi...

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## Table 2. Design Visualization Tools | Tool | Description ...

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## Related Information - Design Floorplan Analysis in Chip Planner on page 166 - Using Logic Lock Regions in Combination with Design Partitions on page 206 - RTL Viewer Overview on page 19 - Technolo...

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## Table 3. Design Optimization Tools The Quartus Prime software provides tools help you identify design RTL and project settings that potentially limit performance. UG-20133 | 2026.01.07 | Tool...

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## Related Information - Quartus Prime Pro Edition User Guide: Design Compilation - • - Quartus Prime Pro Edition User Guide: Design Recommendations

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## 2.5. Design Optimization Overview Revision History The following revision history applies to this chapter: | Document Version | Quartus Prime Version | Changes ...

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## 2.5. Design Optimization Overview Revision History | Document Version | Quartus Prime Version | Changes ...

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## Related Information You can use the Quartus Prime Netlist Viewers to analyze and debug your design netlist. - Quartus Prime Design Flow with the Netlist Viewers on page 18 - RTL Viewer Overview ...

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## 3.1. When to Use the Netlist Viewers: Analyzing Design Problems You can use the Netlist Viewers to analyze and debug your design. The following simple examples show how to use the RTL Viewer and T...

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## 3.2. Quartus Prime Design Flow with the Netlist Viewers When you first open one of the Netlist Viewers after compiling the design, a preprocessor stage runs automatically before the Netlist Viewer...

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## 3.3. RTL Viewer Overview The RTL Viewer allows you to view a register transfer level (RTL) graphical representation of Quartus Prime Pro Edition synthesis results or third-party netlist files in t...

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## 3.3.1. Maximizing Readability in RTL Viewer While displaying a design, the RTL Viewer optimizes the netlist to maximize readability: - Removes logic with no fan-out (unconnected output) or fan-in...

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## 3.4. Technology Map Viewer Overview The Quartus Prime Technology Map Viewer provides a technology-specific, graphical representation of FPGA designs after Analysis and Synthesis or after the Fitte...

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## Figure 8. RTL Viewer Netlist Viewers also contain a toolbar that provides tools to use in the schematic view. - Use the Back and Forward buttons to switch between schematic views. - Click the Nex...

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## 3.5.1. Netlist Navigator Pane - Netlist Navigator Pane on page 23 - Netlist Viewers Find Pane on page 25 - Properties Pane on page 24 The Netlist Navigator pane displays the entire netlist in a ...

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## Table 4. Netlist Navigator Pane Elements | Elements | Description ...

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## 3. Optimizing the Design Netlist UG-20133 | 2026.01.07 The Properties pane contains tabs with the following information about the selected node: - The Fan-in tab displays the Input port and Fa...

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## 3.6. Schematic View The schematic view is shown on the right side of the RTL Viewer and Technology Map Viewer. The schematic view contains a schematic representing the design logic in the netlist....

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## 3.6.1. Display Schematics in Multiple Tabbed View The RTL Viewer and Technology Map Viewer support multiple tabbed views. With multiple tabbed view, schematics can be displayed in different tabs....

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## 3.6.2. Schematic Symbols The symbols for nodes in the schematic represent elements of your design netlist. These elements include input and output ports, registers, logic gates, Altera primitives,...

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## Table 6. Symbols in the Schematic View This table lists and describes the primitives and basic symbols that you can display in the schematic view of the RTL Viewer and Technology Map Viewer. | Sy...

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## Table 7. Operator Symbols in the RTL Viewer Schematic View The following lists and describes the additional higher level operator symbols in the RTL Viewer schematic view. | Symbol ...

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## Figure 15. Show Connectivity Details In cases where the net connects to an instance outside the hierarchy, you can select the net, and unwrap the node to see the destination ports. You can sel...

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## 3.6.7. Moving Nodes in the Schematic View Rearrange items in the schematic view by dragging to destination. To move a node from one area of the netlist to another, select the node and hold down t...

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## 3.6.12. Follow Nets Across Schematic Pages Netlist Viewer User Interface on page 21 Input and output connector symbols indicate nodes that connect across pages of the same hierarchy. Double-clic...

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## 3.7. Cross-Probing to a Source Design File and Other Quartus Prime Windows Schematic Symbols on page 26 The RTL Viewer and Technology Map Viewer allow you to cross-probe to the source design fil...

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## 3.8. Cross-Probing to the Netlist Viewers from Other Quartus Prime Windows You can cross-probe to the RTL Viewer and Technology Map Viewer from other windows in the Quartus Prime software. You can...

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## 3.9. Viewing a Timing Path After completing a full design compilation, including the timing analyzer stage, you can see a visual representation of a timing path cross-probe from a timing report. F...

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## 3.10. Optimizing the Design Netlist Revision History Quartus Prime Pro Edition User Guide: Timing Analyzer The following revision history applies to this chapter: | Document Version | Q...

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## 3.10. Optimizing the Design Netlist Revision History ...

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## 3. Optimizing the Design Netlist UG-20133 | 2026.01.07 | Document Version | Quartus Prime Version | Changes ...

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## 4. Netlist Optimizations and Physical Synthesis The Quartus Prime software offers netlist optimizations during synthesis, and physical synthesis optimization during fitting, that can improve the p...

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## Table 8. Synthesis Netlist Optimization and Physical Synthesis Options | Options | Location/Description ...

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## 4.1. Physical Synthesis Optimizations The Quartus Prime Fitter places and routes the logic cells to ensure critical portions of logic are close together and use the fastest possible routing resour...

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## Related Information Compiler Settings Page (Settings Dialog Box) In Quartus Prime Help © Altera Corporation. Altera, the Altera logo, the 'a' logo, and other Altera marks are trademarks of Alte...

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## 4.1.1. Disabling or Enabling Physical Synthesis Optimization Physical synthesis optimization improves circuit performance by performing combinational and sequential optimization and register dupli...

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## 4.1.2. Physical Synthesis Options The Quartus Prime software provides physical synthesis optimization options to improve fitting results. To access these options, click Assignments ➤ Settings ➤ Co...

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## Table 9. Physical Synthesis Options | Option | Description ...

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## 4.2. Applying Netlist Optimizations The improvement in performance when using netlist optimizations is design dependent. If you have restructured your design to balance critical path delays, netli...

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## 4.2.1. WYSIWYG Primitive Resynthesis Optimize Settings with Design Space Explorer II on page 107 For designs synthesized with a third-party tool, the Perform WYSIWYG primitive resynthesis option...

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## 4.3. Scripting Support You can run procedures and make settings described in this chapter in a Tcl script. You can also run some procedures at a command prompt. For detailed information about scri...

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## 4.3.1. Synthesis Netlist Optimizations Quartus Prime Pro Edition User Guide: Scripting Quartus Prime Pro Edition User Guide: Design Optimization The project .qsf file preserves the settings...

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## 4.3.2. Physical Synthesis Optimizations The project .qsf file preserves the settings that you specify in the GUI. Alternatively, you can edit the .qsf directly. The .qsf file supports the followin...

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## 4.4. Netlist Optimizations and Physical Synthesis Revision History The following revision history applies to this chapter: | Document Version | Quartus Prime Version | Changes ...

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## 4.4. Netlist Optimizations and Physical Synthesis Revision History ...

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## 4.4. Netlist Optimizations and Physical Synthesis Revision History UG-20133 | 2026.01.07 | Document Version | Quartus Prime Version | Changes ...

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## 5.1. Resource Utilization Information This chapter describes techniques for efficient use of device resources. Determining device utilization provides useful information regardless of whether th...

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## 5.1.1. Flow Summary Report The Flow Summary section of the compilation report indicates whether the design exceeds the available device resources, and reports resource utilization, including pins,...

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## Figure 20. Flow Summary Report The Fitter can spread logic throughout the device, which may lead to higher overall utilization. As the device fills up, the Fitter automatically searches for logic ...

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## 5.1.2. Fitter Reports The Fitter generates detailed reports for each stage of place and route. The Fitter section of the Compilation Report includes reports detailing the Fitter's use of device re...

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## 5.1.2.1. Route Stage Reports Quartus Prime Pro Edition User Guide: Design Compilation The Route stage reports ( Compilation Report ➤ Fitter ➤ Route Stage ) provide details about the various type...

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## 5.1.2.1.1. Nets with Highest Wire Count Report UG-20133 | 2026.01.07 The Nets with Highest Wire Count report ( Route Stage ➤ Nets with Highest Wire Count ) lists in descending order the nets tha...

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## 5.1.2.1.2. Delay Chain Summary Report A delay chain is a series of LCELL or EXP primitives or I/O delay chains in the I/O block that you use to create an intentional delay or asynchronous pulse. A...

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## 5.1.2.1.3. Top Congested Hierarchies and Nets Reports If your design fails to route, you can use the Top Congested Hierarchies and Top Congested Nets reports to determine the most congested hierar...

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## 5.1.2.1.4. Global Route Reports A global routing congested region is an area of the FPGA where short wire usage in a particular direction exceeds the capacity of that region. A congested net is a ...

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## 5.1.3. Design Assistant Recommendations You can run the Design Assistant at various stages throughout the compilation process. Correcting Design Assistant rule violations improves the reliability,...

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## 5.1.4. Analysis and Synthesis Reports For designs synthesized with the Quartus Prime synthesis engine, you can see reports describing optimizations that occurred during compilation. For example, ...

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## 5.1.5. Compilation Messages Quartus Prime Pro Edition User Guide: Design Recommendations If the reports show resource usage lower than 100%, but the design does not fit, either resources are ins...

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## 5.1.6. Chip Planner Visualization Viewing Messages The Chip Planner can help you find areas of the device that have routing congestion for specific types of routing resources. If you find areas ...

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## 5.2. Optimizing Resource Utilization Viewing Routing Congestion in Chip Planner on page 173 The following lists the stages after design analysis: 1. Optimize resource utilization-Ensure that yo...

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## 5.2.1. Resource Utilization Issues Overview - Design Optimization Overview on page 7 - Timing Closure and Optimization on page 67 Resource utilization issues can be divided into three categories...

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## 5.2.2.1. Guideline: Modify Pin Assignments or Choose a Larger Package Resolve I/O resource problems with these guidelines. If a design that has pin assignments fails to fit, compile the design w...

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## 5.2.3. Logic Utilization or Placement Quartus Prime Pro Edition User Guide: Design Constraints Resolve logic resource problems, including logic cells containing registers and LUTs, as well as de...

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## 5.2.3.1. Guideline: Optimize Source Code If your design does not fit because of logic utilization, then evaluate and modify the design at the source. The Design Assistant reports can help you to i...

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## 5.2.3.2. Guideline: Optimize Synthesis for Area, Not Speed - AN 584: Timing Closure Methodology for Advanced FPGA Designs - Quartus Prime Pro Edition User Guide: Design Recommendations If...

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## 5.2.3.3. Guideline: Restructure Multiplexers Optimization Mode Multiplexers form a large portion of the logic utilization in many FPGA designs. By optimizing your multiplexed logic, you can achi...

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## 5.2.3.4. Guideline: Perform WYSIWYG Primitive Resynthesis with Balanced or Area Setting Restructure Multiplexers logic option For more information about the Restructure Multiplexers option Note:...

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## 5.2.3.5. Guideline: Use Register Packing Perform WYSIWYG Primitive Resynthesis logic option For information about this logic option The Auto Packed Registers option implements the functions of t...

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## DSP Register Packing Entity Assignment In addition, you can control DSP register packing at the entity level by specifying the DSP Register Packing entity assignment in the Assignment Editor, or w...

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## DSP\_REGISTER\_PACKING\_LEVEL Entity Assignment In addition, you can enter the DSP\_REGISTER\_PACKING\_LEVEL entity assignment directly in the project .qsf to specify the maximum number of registe...

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## Fixed Point DSP Register Packing Summary Report and Fixed Point DSP Register Packing Details Report After running the Compiler's Plan stage, the Compilation Report includes the Fixed Point DSP Reg...

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## Related Information - DSP\_REGISTER\_PACKING Assignment, Quartus Prime Pro Edition Settings File Reference Manual For complete command syntax and options - DSP\_REGISTER\_PACKING\_LEVEL Assignme...

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## 5.2.3.6. Guideline: Remove Fitter Constraints A design with conflicting constraints or constraints that are difficult to meet may not fit in the targeted device. For example, a design might fail t...

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## 5.2.3.7. Guideline: Flatten the Hierarchy During Synthesis Analyzing and Optimizing the Design Floorplan on page 164 Synthesis tools typically provide the option of preserving hierarchical bound...

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## 5.2.3.8. Guideline: Re-target Memory Blocks If the Fitter cannot resolve a design due to memory resource limitations, the design may require a type of memory that the device does not have. For me...

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## 5.2.3.9. Guideline: Use Physical Synthesis Options to Reduce Area - Quartus Prime Pro Edition User Guide: Design Recommendations - Agilex 7 Embedded Memory User Guide - Stratix 10 Embedded Memory ...

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## 5.2.3.10. Guideline: Retarget or Balance DSP Blocks Advanced Fitter Settings Dialog Box A design might not fit because it requires more DSP blocks than the target FPGA device has available. You...

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## UG-20133 | 2026.01.07 design. You can use other settings for a specific node or entity, or on a project-wide basis, to control how the Quartus Prime software converts DSP functions into logic cell...

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## 5.2.3.11. Guideline: Use a Larger Device Fractal Synthesis Optimizations, Quartus Prime Pro Edition User Guide: Design Compilation If a successful fit cannot be achieved because of a shortage of...

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## 5.2.3.12. Guideline: Reduce Global Signal Congestion For Stratix 10 and Arria 10 devices, you can refer to the generated Global Signal Visualization report to see global signal routing and clock s...

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## 5.2.3.13. Guideline: Report Pipelining Information Pipelining the design can be useful for providing resources for retiming and improving performance. However, excessive pipelining can unnecessari...

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## 5.2.4.1. Guideline: Set Auto Packed Registers to Sparse or Sparse Auto Quartus Prime Pro Edition User Guide: Design Optimization Resolve routing resource problems with these guidelines. Th...

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## 5.2.4.2. Guideline: Set Fitter Aggressive Routability Optimizations to Always Auto Packed Registers logic option The Fitter Aggressive Routability Optimization option is useful if your design do...

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## 5.2.4.3. Guideline: Increase Router Effort Multiplier Fitter Aggressive Routability Optimizations logic option The Router Effort Multiplier controls how quickly the router tries to find a valid ...

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## 5.2.4.4. Guideline: Remove Fitter Constraints A design with conflicting constraints or constraints that are difficult to meet may not fit in the targeted device. For example, a design might fail t...

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## 5.2.4.5. Guideline: Optimize Synthesis for Routability Analyzing and Optimizing the Design Floorplan on page 164 You can specify Compiler optimization modes that optimize for routability over sp...

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## 5.2.4.6. Guideline: Optimize Source Code Optimization Mode If your design does not fit because of routing problems and the methods described in the preceding sections do not sufficiently improve...

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## Related Information - Design Assistant Rules List - Design Assistant Design Rule Checking, Quartus Prime Pro Edition User Guide: Design Recommendations - Global Router Wire Visualization Map, Quar...

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## 5.3. Scripting Support If a successful fit cannot be achieved because of a shortage of routing resources, you might require a larger device. You can run procedures and assign settings described ...

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## 5.3.1. Initial Compilation Settings - Quartus Prime Pro Edition Settings File Reference Manual For information about all settings and constraints in the Quartus Prime software. - Quartus Prime Pro...

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## Table 12. Advanced Compilation Settings | Setting Name | .qsf File Variable Name | Values | Type | |----------------------------------|------...

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## Table 13. Resource Utilization Optimization Settings This table lists QSF assignments and applicable values for Resource Utilization Optimization settings: | Setting Name ...

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## 5.4. Area Optimization Revision History The following revision history applies to this chapter: | Document Version | Quartus Prime Version | Changes ...

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## 5.4. Area Optimization Revision History | Document Version | Quartus Prime Version | Changes ...

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## 5.4. Area Optimization Revision History ...

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## 5.4. Area Optimization Revision History ...

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## 5.4. Area Optimization Revision History ...

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## 6. Timing Closure and Optimization This chapter describes techniques to improve timing performance when designing for Altera FPGA devices. The application of techniques varies between designs and ...

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## 6.1. Optimize Multi Corner Timing Process variations and changes in operating conditions can result in path delays that are significantly smaller than those in the slow corner timing model. As a c...

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## 6.2. Optimize Critical Paths Critical paths are timing paths in your design that have a negative slack and may require optimization. These timing paths can span from device I/Os to internal regist...

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## 6.2.1. Viewing Critical Paths Critical Path Delay Reduction Trade-Offs on page 12 Viewing critical paths in the Chip Planner shows why a specific path is failing. You can see if any modification...

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## 6.3. Optimize Critical Chains Critical chains are design paths that limit further register retiming optimization. You can use the Hyper-Aware design flow to shorten design cycles and optimize crit...

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## 6.3.1. Viewing Critical Chains Hyperflex Architecture High-Performance Design Handbook Looking at the critical chain shows the exact logic that limits retiming operations in your design. For exa...

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## 6.4. Design Evaluation for Timing Closure - Hyperflex Architecture High-Performance Design Handbook - Stratix 10 HyperFlex Design: Analyzing Critical Chains (OS10CRCHNS) Online Course As you m...

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## 6.4.1. Review Messages After compiling your design, review the messages in each section of the compilation report. Most designs that fail timing start out with other problems that the Fitter repor...

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## 6.4.2. Evaluate Fitter Netlist Optimizations You can specify options that direct the Fitter to perform optimizations to the design netlist. Specify global options, such as register packing, duplic...

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## 6.4.3. Evaluate Optimization Results After checking what optimizations were done and how they improved performance, evaluate the runtime it took to get the extra performance. To reduce compilation...

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## 6.4.4. Evaluate Resource Usage Evaluate the device resources that the design consumes, including global and nonglobal signal usage, routing utilization, and clustering difficulty. Determine whethe...

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## 6.4.4.1. Evaluate Global and Non-Global Usage For Arria 10 and Cyclone 10 GX designs that contain many clocks, evaluate global and non-global signals to determine whether global resources are used...

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## 6.4.4.2. Evaluate Routing Usage Review routing usage reported in the Fitter Resource Usage Summary report. UG-20133 | 2026.01.07 Figure 29. Fitter Resource Usage Summary Report Average inte...

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## 6.4.4.3. Evaluate Wires Added for Hold During routing the Fitter may add wire between register paths to increase delay to meet hold time requirements. The Fitter reports how much routing delay was...

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## 6.4.5.1. Difficulty Packing Design In the Fitter Resource Section, under the Resource Usage Summary , review the Difficulty Packing Design report. The Difficulty Packing Design report details the ...

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## 6.4.5.2. Review Ignored Assignments The Compilation Report includes details of any assignments that the Fitter ignores. The Fitter may ignore assignments if they refer to nodes names that change, ...

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## 6.4.5.4. Review the Design Floorplan The Synthesis and Fitter reports list all settings set to a non-default value during the compilation. Review the non-default settings to ensure benefit. Use ...

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## 6.4.5.5. Adjust Placement Effort You can increase the Assignments ➤ Settings ➤ Compiler Settings ➤ Advanced Settings (Fitter) ➤ Placement Effort Multiplier value to spend additional compilation ti...

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## 6.4.5.6. Adjust Fitter Effort Fitter Optimization mode settings allow you to specify whether the Compiler focuses optimization efforts for performance, resource utilization, power, or compile time...

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## 6.4.5.7. Review Timing Constraints Ensure that you constrain all clocks with the correct frequency requirements. To confirm the proper application of timing constraints, run the Design Assistant ...

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## 6.4.6. Evaluate Clustering Difficulty You can evaluate clustering difficulty to help reach timing closure. You can monitor clustering difficulty whenever you add logic and recompile. Use the clust...

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## 6.4.7. Revise and Recompile Look for obvious problems that you can fix with minimal effort. To identify where the Compiler had trouble meeting timing, perform seed sweeping with about five compile...

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## 6.5. Timing Optimization You can use the techniques and tools in this section to optimize timing when your design does not meet its timing requirements. Also, refer to the design recommendations i...

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## 6.5.1. Correct Design Assistant Rule Violations After running any stage of the Compiler, review the Design Assistant reports to analyze any design rule violations and view recommendations to corre...

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## 6.5.2. Implement Fast Forward Timing Closure Recommendations Quartus Prime Pro Edition User Guide: Design Recommendations In traditional FPGA timing closure flows, the starting point for most de...

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## 6.5.2.1. Retiming Limit Details Report Hyperflex Architecture High-Performance Design Handbook Use the Retiming Limit Details report to get specific information on what is currently limiting the...

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## 6.5.2.1.1. Using the Retiming Limit Details Report To access the Retiming Limit Details report: 1. In the Reports tab, double-click Retiming Limit Details under Fitter ➤ Retime Stage . 2. To loca...

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## 6.5.2.2. Fast Forward Timing Closure Recommendations When running Fast Forward compilation, the Compiler removes signals from registers to allow mobility within the netlist for subsequent retiming...

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## Table 14. Fast Forward Details Report Information | Name | Description ...

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## 6.5.2.2.1. Generating Fast Forward Timing Closure Recommendations To generate Fast Forward timing closure recommendations: 1. On the Compilation Dashboard, click Fast Forward Timing Closure Recom...

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## 6.5.2.2.2. Implementing Fast Forward Recommendations After implementing timing closure recommendations in your design, you can rerun the Retime stage to obtain the predictive performance gains. ...

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## 6.5.3.1. Report Timing Reporting the timing paths and routing details can help uncover correctable timing and routing delays and other conditions that prevent retiming registers for higher perform...

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## Table 15. Report Timing Settings UG-20133 | 2026.01.07 Figure 38. Report Timing Dialog Box (Top Section) Figure 39. Report Timing Dialog Box (Bottom Section) | Option ...

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## Table 15. Report Timing Settings ...

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## Table 15. Report Timing Settings ...

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## Setup Slack Breakdown On the Extra Info Tab UG-20133 | 2026.01.07 Figure 40. Extra Info Tab The Extra Info tab contains other timing metrics to help you diagnose timing closure issues, includ...

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## Table 16. Extra Info Tab Data | Extra Info Data | Description ...

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## Table 16. Extra Info Tab Data No indicates that the setup margin is insufficient for hold timing. ...

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## Table 16. Extra Info Tab Data The following describe the interpretation of timing conditions indicated by the Setup Slack Breakdown : - When the Setup Slack Breakdown is less than 0 -the path has...

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## 6.5.3.2. Report Logic Depth Hyperflex Architecture High-Performance Design Handbook The Timing Analyzer's Reports ➤ Design Metrics ➤ Report Logic Depth... command allows you to report the number...

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## Table 17. Report Logic Depth Settings Call report logic depth by topology for each clock, intraclock only. Close timing with accurate histogram cross probing. You can specify various option...

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## 6.5.3.3. Report Neighbor Paths The Timing Analyzer's Reports ➤ Design Metrics ➤ Report Neighbor Paths... command helps you to determine the root cause of critical paths (for example, high logic le...

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## Figure 45. Report Neighbor Paths Report Report Neighbor Paths reports the most timing-critical paths in the design, including associated slack, additional path summary information, and path boundi...

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## Figure 45. Report Neighbor Paths Report | Option | Description ...

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## 6.5.3.4. Report Register Spread The Timing Analyzer's Reports ➤ Design Metrics ➤ Report Register Spread command analyzes the final placement to identify registers with sinks pulling them in variou...

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## 6.5.3.4. Report Register Spread | Option | Available Settings ...

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## 6.5.3.4. Report Register Spread ...

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## 6.5.3.4.1. Understanding Report Register Spread Data It is helpful to understand the concept of tension in utilizing Report Register Spread data. Tension is the sum over each sink of the distance ...

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## What Is a Good Tension Value? There is no absolute threshold for a good or bad tension value. A register's tension value depends on the number of fan-outs, their distance, and the degree to which ...

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## Duplicate a Register to Reduce Tension Value You can use Report Register Spread in combination with other design information to make effective changes. For example, in a design suffering from rout...

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## Selecting Registers for Duplication The best candidate registers for duplication are those with a single data fan-in because such nodes are unlikely to have much additional congestion to feed othe...

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## 6. Timing Closure and Optimization UG-20133 | 2026.01.07 Consider an example register from the tension report with the following fan-out pattern in Chip Planner: Figure 50. Example Fan-Out Pat...

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## 6.5.3.5. Report Route Net of Interest The Timing Analyzer's Reports ➤ Design Metrics ➤ Report Route Net of Interest... command allows you to report the nets that require the most effort from the r...

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## 6.5.3.6. Report Retiming Restrictions The Timing Analyzer's Reports ➤ Design Metrics ➤ Report Retiming report\_retiming\_restrictions is the equivalent scripting command. Restrictions... command ...

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## 6.5.3.7. Report Pipelining Information Retiming Restrictions and Workarounds, Hyperflex Architecture High-Performance Design Handbook The Timing Analyzer's Reports ➤ Design Metrics ➤ Report Pipe...

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## Figure 55. Report Detailed Pipelining The detailed report shows every register in a tree structure. Over- or under-pipelining recommendations are in the main report. The following shows every sing...

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## Figure 56. Detailed Pipelining Result To help identify potential over-pipelining, Report Pipelining Information reports: - The recommended pipeline stage adjustment across bus - The minimum total...

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## 6.5.3.8. Report CDC Viewer The Timing Analyzer's Reports ➤ Clock Domain Crossings ➤ Report CDC Viewer... command allows you to configure and display a custom clock domain crossing report and the C...

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## Table 22. Report Clock Domain Crossing Viewer Settings | Option | Description ...

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## Table 23. CDC Viewer Report Controls | Control | Description ...

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## Table 23. CDC Viewer Report Controls ...

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## Table 24. Transfer Cell Content | Cell Color | Color Legend ...

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## Table 25. Transfer Cell Right-Click Menus | Command | Description | |----------------...

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## Table 26. Clock Header Right-Click Menus | Command | Description ...

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## 6.5.3.9. Timing Closure Recommendations Tips for Analyzing Failing Clock Paths that Cross Clock Domains on page 150 The Report Timing Closure Recommendations command in the Timing Analyzer Task ...

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## 6.5.3.10. Global Network Buffers Routing paths allow you to identify global network buffers that fail timing. Buffer locations names reflect the network they drive. - CLK\_CTRL\_Gn -for Global dr...

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## 6.5.3.10.2. Insertion Delay If you cannot move the register feeding the global buffer closer, then consider changing either the design logic or the routing type. If the design requires a global ...

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## 6.5.3.10.3. Fan-Out Nodes with very high fan-out that use local routing tend to pull logic that they drive close to the source node. This can make other paths fail timing. Duplicating registers ca...

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## 6.5.3.11. Resets and Global Networks You can use the Global Signal assignment to control the global signal usage on a persignal basis. For example, if a signal needs local routing, you set the Glo...

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## 6.5.3.12. Suspicious Setup Suspicious setup failures include paths with very small or very large requirements. One typical cause is math precision error. For example, 10Mhz/3 = 33.33 ns per perio...

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## 6.5.3.13. Auto Shift Register Replacement During synthesis, the Compiler can convert shift registers or register chains into RAMs to save area. However, conversion to RAM often reduces speed. The ...

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## 6.5.3.14. Clocking Architecture For better timing results, place all registers driven by a regional clock in one quadrant of the chip. You can review the clock region boundaries in the Chip Planne...

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## 6.5.4. Try Optional Fitter Settings Viewing Available Clock Networks in Chip Planner on page 171 This section focuses only on the optional timing-optimization Fitter settings, which are the Opti...

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## Related Information The settings that best optimize different designs might vary. The group of settings that work best for one design does not necessarily produce the best result for another desig...

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## 6.5.4.1. Optimize Hold Timing The Optimize Hold Timing option directs the Quartus Prime software to optimize minimum delay timing constraints. When you turn on Optimize Hold Timing in the Advance...

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## 6.5.4.2. Fitter Aggressive Routability Optimization Quartus Prime Pro Edition User Guide: Design Recommendations The Fitter Aggressive Routability Optimizations logic option allows you to specif...

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## Table 27. Fitter Aggressive Routability Optimizations Logic Option Settings | Settings | Description ...

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## 6.5.5. Back-Annotating Optimized Assignments The Compiler maps the elements of your design to specific device resources during fitting. After compilation, you can back-annotate (copy) the Compiler...

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## Figure 61. Back-Annotate Assignments Dialog Box To back-annotate (copy) the device resource assignments from the last compilation to the project .qsf (or to a Tcl file) for use in the next compila...

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## 6.5.6. Optimize Settings with Design Space Explorer II The Design Space Explorer II tool ( Tools ➤ Launch Design Space Explorer II ) helps you to find the optimal project settings for the performa...

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## 6.5.6.1.1. Running Quartus DSE on Kubernetes Clusters - Using Design Space Explorer - 21 Minute Online Course - Setting Up Remote Farm Using Design Space Explorer II, Quartus Prime Pro Edition Use...

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## Public Cloud Kubernetes Cluster on Azure AKS Example The following script creates a Kubernetes cluster on Azure using their AKS (Azure Kubernetes Service) managed service. Prerequisites: This exa...

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## Option 1: Create a Service Account - DSE requires permission to launch Kubernetes jobs within your cluster. You can grant this permission by creating a Kubernetes Service Account. This is a one-ti...

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## Steps to configure: 1. Copy the template file : Make a copy of 2. kube\_job\_serviceaccount\_template.json to your working directory. 2. Customize the configuration : Update the copied file with v...

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## Option 2: Enable Automatic Service Account Creation DSE can automatically create the Service Account for you. To enable this feature, your user account must have permission to access the Kubernete...

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## Requirements: - Your Kubernetes user must have cluster administrator privileges or equivalent RBAC permissions. - The cluster must have RBAC enabled. This option is more convenient as it eliminat...

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## Container Image with Quartus DSE requires a container image that includes the appropriate version of Quartus Prime installed, or is configured with correct mounts to access Quartus Prime from the ...

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## Public Container Images Altera publishes official Quartus Prime container images on Docker Hub. The following images are available Quartus Prime Pro Edition software version 25.3 for different dev...

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## Launch Quartus Design Space Explorer Altera Docker Hub The procedures below demonstrate how to set up and configure DSE with Kubernetes. 1. Run quartus\_dsew to start the Design Space Explorer...

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## Service Account Configuration 1. Click Setup in the left toolbar. 2. For Compilation Type , select Remote and choose Kubernetes from the dropdown menu. 3. Enable out-of-network mode by setting Rem...

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## Kubeconfig File Setup Under Full path to kubectl , enter the complete file path for the kubectl executable. If kubectl is already in your system PATH, you can leave this field blank. In the Kube...

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## Security Note - Protecting Your Kubeconfig File A cluster can have one or more namespaces that partition the cluster resources. Enter the name of the namespace you plan to use. The kubeconfig fi...

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## Container Image Setup In Pull image before running , select how to download the container image: - Leave blank to pull the image only once. - Set to Always to allow Kubernetes to download a new i...

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## Compute Resource Requirements Set the Initial Work Directory to specify where DSE should run within the container. Example: /tmp/run1 - CPU Limit : Sets the number of CPUs to request from the c...

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## Time Limit Active Deadline Seconds sets a time limit for how long the exploration can run. Jobs that do not finish within this time will be automatically terminated. The default value is 86400 sec...

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## How DSE Connects to Kubernetes Use the LM\_LICENSE\_FILE entry to specify the license server(s) that Quartus should use within the cluster. UG-20133 | 2026.01.07 When the DSE GUI starts, ...

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## Configure Exploration 1. Access the Exploration Panel : Select the Exploration panel from the left toolbar. 2. Set Exploration Name : Enter a descriptive name for your exploration run in the Explo...

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## 6.5.6.2. Running DSE II Settings Exploration To run DSE II settings exploration to identify the optimum settings combination for your design goals, follow these steps: 1. Specify all timing const...

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## 6.5.6.3. Specifying DSE II Computing Resources You can configure DSE II to take advantage of distributed computing resources to run multi-compilation design explorations more efficiently. In the D...

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## Compilation Type Settings DSE II provides the following options for configuring your DSE II setup: Choose one of the following options for specifying the type of computing resources to use for D...

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## Table 28. Compilation Type Settings | Compilation Type | Description | |--------------------|--------------------------------...

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## Table 29. Kubernetes Remote Farm Settings The following settings are available for this option. | Parameter | Comments ...

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## Table 29. Kubernetes Remote Farm Settings | Parameter | Comments ...

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## Table 30. LSF Remote Farm Settings The following settings are available for this option: | Parameter | Comments ...

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## Table 31. PBSPro Remote Farm Settings The following settings are available for this option: | Parameter | Comments ...

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## Slurm Remote Farm Settings The following settings are available for this option: Table 32. Slurm Remote Farm Settings | Parameter | Comments ...

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## SunGrid (Beta) Remote Farm Settings The following settings are available for this option: Table 33. SunGrid Remote Farm Settings | Parameter | Comments ...

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## Torque Remote Farm Settings The following settings are available for this option: Table 34. Torque Remote Farm Settings | Parameter | Comments ...

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## 6.5.6.4. DSE II Optimization Parameters (Exploration Page) DSE II provides a collection of predefined exploration spaces on the Exploration page that allow you to target settings optimization for ...

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## 6.5.6.5. Viewing DSE II Results Exploration Page (Design Space Explorer II) In Quartus Prime Help DSE II compares the compilation results to determine the best Quartus Prime software settings fo...

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## Saving DSE II Results DSE II has reporting tools that help you quickly determine important design metrics, such as worse-case slack, across all exploration points. By default, DSE II saves all t...

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## 6.5.7. Aggregating and Comparing Compilation Results with Exploration Dashboard Report Page (Design Space Explorer II) In Quartus Prime Help You can use the Exploration Dashboard ( quartus...

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## Figure 66. Exploration Dashboard Use Model Use the Exploration Dashboard to quickly compare the aggregated compilation results from multiple projects or sets of results to determine the best imple...

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## 6.5.7.1. Aggregation Use Case AN 1006: Multi-Project Analysis with Exploration Dashboard Aggregation helps you see all the results from your compiles in one workspace. For example, you can use a...

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## 6.5.7.2. Comparison Use Case Comparison of compilation results can be helpful in determining the set of conditions or properties that are different between two sets of compilation results. For exa...

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## Table 35. Exploration Dashboard Terms The Exploration Dashboard operates on an object-property model that defines the following roles, responsibilities, and properties of the major object types: ...

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## 6.5.7.3.1. Base Exploration Dashboard Properties ::quartus::qed, Quartus Prime Pro Edition User Guide: Scripting This section describes the Exploration Dashboard objects and properties tha...

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## Table 36. Base Exploration Dashboard Objects and Properties | Property Name | Property Type | Property Description | Default Value ...

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## ::qed::set\_user\_data and ::qed::get\_user\_data Specializations In addition to set\_property and get\_property user\_data also supports the set\_user\_data and get\_user\_data specializations fo...

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## Table 37. Project Handle Properties The main purpose of Project Handle objects is to configure, launch, and manage a connection to a single project compilation database. | Property Name | Pr...

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## Table 37. Project Handle Properties Each group ID present in a project's groups property corresponds to a group object that is guaranteed to have that project's ID present in its projects property...

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## Table 38. Project Group Objects and Properties The main purpose of a Project Group is to provide a convenient way to refer to and work with an arbitrary subset of the Project Handles that are load...

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## 6.5.7.3.4. Workspace Objects and Properties The main purpose of a workspace is to act as a single container for all other Exploration Dashboard objects, reports, and results. The workspace also ha...

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## Table 39. Workspace Objects and Properties | Property Name | Property Type | Property Description | D...

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## 6.5.7.4. Starting the Exploration Dashboard To start the Exploration Dashboard using the Tcl API, follow these steps: 1. To start the Exploration Dashboard, perform one of the following: - To sta...

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## 6.5.8. I/O Timing Optimization Techniques - AN 1006: Multi-Project Analysis with Exploration Dashboard - ::quartus::qed, Quartus Prime Pro Edition User Guide: Scripting This stage of design opti...

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## Summary of Techniques for Improving Setup and Clock-to-Output Times The table lists the recommended order of techniques to reduce tSU and tCO times. Reducing tSU times increases hold (tH) times. ...

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## 6.5.8.1. I/O Timing Constraints Initial Compiler Settings on page 8 Note: UG-20133 | 2026.01.07 Timing Analyzer supports the Synopsys* Design Constraints (SDC) format for constraining your d...

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## 6.5.8.2. Optimize IOC Register Placement for Timing Logic Option Quartus Prime Pro Edition User Guide: Timing Analyzer This option moves registers into I/O elements to meet tSU or tCO assignment...

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## 6.5.8.3. Fast Input, Output, and Output Enable Registers Optimize IOC Register Placement for Timing Logic Option Help Topic In Quartus Prime Help You can place individual registers in I/O cells ...

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## 6.5.8.4. Programmable Delays - Fast Input Register logic option Help Topic - Fast Output Register logic option - Fast Output Enable Register logic option - Fast OCT Register logic option You can...

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## Related Information - Input Delay from Pin to Input Register logic option Help Topic - Input Delay from Pin to Internal Cells logic option Help Topic UG-20133 | 2026.01.07 - Output Enable Pin ...

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## 6.5.8.5. Use PLLs to Shift Clock Edges Using a PLL typically improves I/O timing automatically. If the timing requirements are still not met, most devices allow the PLL output to be phase shifted ...

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## 6.5.8.6. Use Fast Regional Clock Networks and Regional Clocks Networks You can achieve the same type of effect in certain devices by using the programmable delay called Input Delay from Dual Purpo...

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## 6.5.8.7. Spine Clock Limitations In Arria 10 and Cyclone 10 GX designs with high clock routing demands, limitations in the Quartus Prime software can cause spine clock errors. These limits do not ...

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## 6.5.9. Register-to-Register Timing Optimization Techniques Viewing Available Clock Networks in Chip Planner on page 171 The next stage of design optimization seeks to improve register-to-registe...

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## 6.5.9.1. Optimize Source Code - Quartus Prime Pro Edition User Guide: Design Recommendations - Design Assistant Rules List In many cases, optimizing the design's source code can have a very sign...

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## 6.5.9.2. Improving Register-to-Register Timing AN 584: Timing Closure Methodology for Advanced FPGA Designs The choice of options and settings to improve the timing margin (slack) or to improve ...

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## 6.5.9.3. Physical Synthesis Optimizations - Optimize Settings with Design Space Explorer II on page 107 - Initial Compiler Settings on page 8 The Quartus Prime software offers physical synthesis...

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## 6.5.9.4. Set Power Optimization During Synthesis to Normal Compilation - Perform WYSIWYG Primitive Resynthesis Logic Option Help Topic - Optimization Technique Logic Option Help Topic In Quartu...

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## 6.5.9.5. Optimize Synthesis for Performance, Not Area Power Optimization Design performance varies depending on coding style, synthesis tool used, and options you specify when synthesizing. Chan...

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## 6.5.9.6. Flatten the Hierarchy During Synthesis Optimization Technique Logic Option Help Topic In Quartus Prime Help Synthesis tools typically let you preserve hierarchical boundaries, which can...

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## 6.5.9.8. Change Adder Tree Styles Synthesis tools offer varying synthesis effort levels to trade off compilation time with synthesis results. Set the synthesis effort to high to achieve best resul...

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## Figure 70. Balanced Binary Versus Compressor Style Adder Trees For designs that may benefit, you can apply the Use Compressor Implementation ( USE\_COMPRESSOR\_IMPLEMENTATION ) global, entity, or ...

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## 6.5.9.9. Duplicate Registers for Fan-Out Control Often, timing failures can occur due to the influence of signals that are not directly involved in the failing transfers. This condition tends to m...

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## 6.5.9.9.1. Manual Register Duplication Synthesis tools support options or attributes that specify the maximum fan-out of a register. When using Quartus Prime synthesis, you can set the Maximum Fan...

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## 6.5.9.9.2. Automatic Register Duplication: Estimated Physical Proximity The DUPLICATE\_REGISTER assignment helps in leveraging estimated physical proximity information to guide the creation of dup...

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## Important: - Setting PHYSICAL\_SYNTHESIS to OFF disables DUPLICATE\_REGISTER . - Unlike other physical synthesis optimizations, the DUPLICATE\_REGISTER assignment does allow duplication of registe...

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## 6.5.9.9.3. Automatic Register Duplication: Hierarchical Proximity Leveraging design hierarchy information to guide the creation of duplicates and their fan-out assignments is enabled by the DUPLIC...

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## where, - register\_name is the last register in a chain that fans out to multiple hierarchies. To create a register tree, ensure that there are sufficient simple registers behind the node and thos...

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## Figure 73. Netlist After Duplicating regZ to Hierarchy Level Two When num\_levels is set to 1, only regZ is pulled out of the chain and pushed down one hierarchy level into its fan-out tree. set...

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## 6.5.9.10. Prevent Shift Register Inference Synchronous Reset Design Strategies, AN 917 Reset Design Techniques for Hyperflex Architecture FPGAs Turning off the inference of shift registers can i...

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## 6.5.9.11. Use Other Synthesis Options Available in Your Synthesis Tool With your synthesis tool, experiment with the following options if they are available: - Turn on register balancing or retim...

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## 6.5.9.12. Fitter Seed The Fitter seed affects the initial placement configuration of the design. Any change in the initial conditions changes the Fitter results; accordingly, each seed value resul...

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## 6.5.9.13. Set Maximum Router Timing Optimization Level Optimize Settings with Design Space Explorer II on page 107 To improve routability in designs where the router did not pick up the optimal ...

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## 6.5.9.14. Register-to-Register Timing Analysis Router Timing Optimization Level Logic Option In Quartus Prime Help Your design meets timing requirements when you do not have negative slac...

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## 6.5.9.14.1. Tips for Analyzing Failing Paths When you are analyzing failing paths, examine the reports and waveforms to determine if the correct constraints are being applied, and add timing excep...

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## 6.5.9.14.2. Tips for Analyzing Failing Clock Paths that Cross Clock Domains - Exploring Paths in the Chip Planner on page 184 - Design Evaluation for Timing Closure on page 69 - Review Timing Path...

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## UG-20133 | 2026.01.07 - Check if the design contains paths that involve a different clock in the middle of the path, even if the source and destination register clock are the same. - Check whether...

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## 6.5.9.14.3. Tips for Critical Path Analysis Report CDC Viewer on page 98 When analyzing the failing paths in a design, it is helpful to understand the interactions around the critical paths. To...

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## Figure 76. Timing Report The critical path of the design is in red. The relation between the .tcl script and the figure is: - The first two lines show everything inside the two endpoints of the c...

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## 6.5.9.14.4. Tips for Creating a .tcl Script to Monitor Critical Paths Across Compiles Review Timing Path Details on page 80 Many designs have the same critical paths show up after each compile. ...

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## 6.5.9.14.5. Global Routing Resources Global routing resources are designed to distribute high fan-out, low-skew signals (such as clocks) without consuming regular routing resources. Depending on t...

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## 6.5.9.14.6. Register RAMS and DSPs If your design includes long timing paths going to and from RAMs and DSPs, you must fully register the RAMs and DSPs. RAM and DSP performance can vary, depe...

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## 6.5.10. Metastability Analysis and Optimization Techniques Metastability problems can occur when a signal is transferred between circuitry in unrelated or asynchronous clock domains, because the d...

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## 6.6. Periphery to Core Register Placement and Routing Optimization Quartus Prime Pro Edition User Guide: Design Recommendations The Periphery to Core Register Placement and Routing Optimization ...

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## Figure 77. Periphery to Core Register Placement and Routing Optimization (P2C) Flow P2C runs after periphery placement, and generates placement for core registers on corresponding P2C/C2P paths, a...

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## 6.6.1. Setting Periphery to Core Optimizations in the Advanced Fitter Setting Dialog Box The Periphery to Core Placement and Routing Optimization setting specifies whether the Fitter optimizes tar...

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## 6.6.2. Setting Periphery to Core Optimizations in the Assignment Editor When you turn on the Periphery to Core Placement and Routing Optimization (P2C/C2P) setting in the Assignment Editor, the Qu...

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## 6.6.3. Viewing Periphery to Core Optimizations in the Fitter Report The Quartus Prime software generates a periphery to core placement and routing optimization summary in the Fitter (Place & R...

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## 6.7. Scripting Support You can run procedures and make settings described in this manual in a Tcl script. You can also run procedures at a command prompt. For detailed information about scripting ...

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## 6.7.1. Initial Compilation Settings - Quartus Prime Pro Edition Settings File Reference Manual - Quartus Prime Pro Edition User Guide: Scripting - Quartus Prime Pro Edition User Guide: Scripting ...

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## Table 44. Advanced Compilation Settings | Setting Name | .qsf File Variable Name | Values | Type | |----------------------------------|----------...

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## Table 45. I/O Timing Optimization Settings Design Optimization Overview on page 7 The table lists the .qsf file variable name and applicable values for the I/O timing optimization settings. | ...

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## 6.7.3. Register-to-Register Timing Optimization Techniques The table lists the .qsf file variable name and applicable values for the settings described in Register-to-Register Timing Optimization ...

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## 6.8. Timing Closure and Optimization Revision History The following revision history applies to this chapter: | Document Version | Quartus Prime Version | Changes ...

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## 6.8. Timing Closure and Optimization Revision History ...

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## 6.8. Timing Closure and Optimization Revision History | Document Version | Quartus Prime Version | Changes ...

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## 6.8. Timing Closure and Optimization Revision History • Updated product family name to "Intel Agilex 7." ...

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## 6.8. Timing Closure and Optimization Revision History | Document Version | Quartus Prime Version | Changes ...

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## 6.8. Timing Closure and Optimization Revision History ○ Added topics: Critical Chains, Viewing Critical Chains, Intel Stratix 10 Timing Closure Recommendations, Retiming Limit Details Report, Usin...

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## 6.8. Timing Closure and Optimization Revision History | Document Version | Quartus Prime Version | Changes ...

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## 6.8. Timing Closure and Optimization Revision History ...

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## 6.8. Timing Closure and Optimization Revision History | Document Version | Quartus Prime Version | Changes ...

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## 7. Analyzing and Optimizing the Design Floorplan Determining the layout (placement) of your design elements into physical resources on the FPGA device is known as floorplanning. Floorplanning is a...

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## 7.1. Location Assignment Optimization Guidelines Back-Annotate Optimized Assignments, Quartus Prime Pro Edition User Guide: Getting Started Refer to the following optimization guidelines for ass...

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## Guideline: Assigning Logic to Specific Locations As part of design optimization, you may want to assign logic in your design to specific locations in the target device floorplan. You may want to m...

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## Guideline: Assigning the Location of One or Two Registers Sometimes, you may want to assign the location of one or two registers or combinational nodes. In cases where the amount of logic is extre...

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## Guideline: Assigning a Register to a Specific Location in an ALM If you want to assign a register to a specific location in an ALM, you must know the specific location you want to assign. The spec...

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## Guideline: Making Assignments to Compiler-Modified Nodes If you make location assignments to registers that the Compiler modifies or optimizes during compilation, is unlikely that the Compiler wil...

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## Guideline: Assigning Combinational Logic to Specific Locations Generally it is not worth assigning combinational logic to specific locations. Combinational logic names are more likely to change in...

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## 7.2. Design Floorplan Analysis in Chip Planner Creating a Design Partition, Quartus Prime Pro Edition User Guide: Design Compilation The Chip Planner simplifies floorplanning by allowing you to ...

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## 7.2.1. Starting the Chip Planner UG-20133 | 2026.01.07 To start the Chip Planner, select Tools ➤ Chip Planner . You can also start the Chip Planner by using any of the following methods: - Clic...

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## Figure 81. Chip Planner Button on Toolbar - In the following tools, right-click any chip resource and select Locate ➤ Locate in Chip Planner : - [ ] ○ Compilation Report - [ ] ○ Logic Lock Regio...

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## Chip Planner Toolbar The Chip Planner GUI helps you to visualize and modify the use of device resources for your design. As you zoom in, the level of abstraction decreases, revealing more details ...

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## Chip Planner Floorplan Views The Chip Planner includes multiple views to shows various levels of detail for the targeted Altera FPGA device. You can toggle between these different views when you r...

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## Layers Settings Pane clicking View ➤ Layers Settings to customize which device structures the Chip Planner displays. You can select the Basic , Detailed , or Floorplan Editing settings that are p...

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## Editing Mode The Chip Planner has two editing modes. Figure 87. Editing Mode Selection - Assignment -editing mode allows you to make assignment changes that are implemented the next time you r...

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## 7.2.3. Viewing Design Elements in Chip Planner The Locate History window records all searches you perform using the Locate in Chip Planner command, allowing you to quickly rerun common searches. ...

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## 7.2.3.1. Viewing Architecture-Specific Design Information in Chip Planner The Chip Planner allows you to view architecture-specific information related to your design. By enabling the options in t...

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## 7.2.3.2. Viewing Available Clock Networks in Chip Planner When you enable a clock region layer in the Layers Settings pane, you display the areas of the chip that are driven by global and regional...

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## Figure 88. Clock Regions Spine/sector clock regions have a dotted vertical line in the middle. This dotted line indicates where two columns of row clocks meet in a sector clock. To change the...

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## 7.2.3.3. Viewing Clock Sector Utilization in Chip Planner Spine Clock Limitations on page 137 The Chip Planner provides a visual representation of a design's clock sector utilization. To genera...

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## 7.2.3.4. Viewing Routing Congestion in Chip Planner The Chip Planner offers a comprehensive visual representation of device resources, enabling in-depth analysis of routing and congestion. Throug...

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## 7.2.3.4. Viewing Routing Congestion in Chip Planner | Resource Type | Report Description ...

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## 7.2.3.4. Viewing Routing Congestion in Chip Planner To identify potential routing resource shortages, it's essential to examine each routing interconnect type individually from the drop-down list...

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## 7.2.3.4.1. Areas with Routing Congestion Viewing Routing Resources on page 186 Even if the average congestion is not excessively high, certain areas of the design may experience significant ...

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## 7.2.3.4.2. Congestion due to HDL Coding style Sometimes, routing congestion may be a result of the HDL coding style used in your design. After identifying congested areas using the Chip Planner, r...

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## 7.2.3.6. Viewing High-Speed Serial Interfaces (HSSI) in Chip Planner To view the I/O bank map of the device in the Chip Planner, double-click Report All I/O Banks in the Tasks pane. The Chip Pla...

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## 7.2.3.7. Viewing Source and Destination Nodes in Chip Planner The Chip Planner allows you to view the registered fan-in or fan-outs of nodes in compiled designs with the Report Registered Connecti...

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## 7.2.3.8. Viewing Fan-In and Fan-Out in Chip Planner Viewing Fan-In and Fan-Out in Chip Planner on page 177 Displays the atoms that fan-in to or fan-out from a resource, including connectivity li...

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## 7.2.3.9. Viewing Immediate Fan-In and Fan-Out in Chip Planner Viewing Source and Destination Nodes in Chip Planner on page 177 Displays the immediate fan-in or fan-out connection for the selecte...

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## 7.2.3.10. Viewing the Selected Contents in Chip Planner You can view a detailed report of the contents of any area that you select in the Chip Planner. When you view the contents of a selected are...

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## Figure 95. Viewing Selected Contents 4. To customize the color coding of report folders, right-click any report, and then click Properties . You can customize the Report Name , Report Color , and ...

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## 7.2.3.11. Viewing the Location and Utilization of Device Resources in Chip Planner Chip Planner can generate reports about the different types of device resources located in the in Chip Planner vi...

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## 7.2.3.12. Viewing Module Placement by Cross-Probing to Chip Planner You can use cross-probing to determine the location of a design module on the device in Chip Planner. To view the placement of ...

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## 7.2.4. Finding Design Elements in the Chip Planner Use the Find tab to locate any design atom, port, location, or routing element by name within the Chip Planner view. The Find tab located in Chip...

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## 7.2.4.1. Find Options (Chip Planner Search) You can enable or disable the following Find In options to narrow or expand the search for design elements in Chip Planner: Table 47. Find In Options ...

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## 7.2.5.1. Analyzing Connections for a Path Use the Chip Planner to explore paths between logic elements. The following examples use the Chip Planner to traverse paths from the Timing Analysis repor...

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## 7.2.5.2. Locate Path from the Timing Analysis Report to the Chip Planner To locate a path from the Timing Analysis report to the Chip Planner, perform the following steps: 1. Select the path you ...

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## 7.2.5.3. Show Delays With the Show Delays feature, you can view timing delays for paths appearing in Timing Analyzer reports. To access this feature, click View ➤ Show Delays in the main menu. Alt...

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## 7.2.5.4. Viewing Routing Resources With the Chip Planner and the Locate History window, you can view the routing resources that a path or connection uses. You can also select and display the Arriv...

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## 7.2.6. Viewing Assignments in the Chip Planner Viewing Routing Congestion in Chip Planner on page 173 You can view location assignments in the Chip Planner by selecting the appropriate layer, or...

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## Figure 109. Viewing Assignments in the Chip Planner Drag resource to move to neighboring cell To create or move an assignment, or to make node and pin location assignments to Logic Lock regions, ...

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## 7.2.7. Viewing High-Speed and Low-Power Tiles in the Chip Planner Some Altera devices have ALMs that can operate in either high-speed mode or lowpower mode. The power mode is set during the fittin...

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## 7.2.8. Viewing Design Partition Placement With the Report Design Partitions command, you can view the physical placement of design partitions using the same color map as the Design Partition Plann...

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## 7.3. Defining Logic Lock Placement Constraints A Logic Lock region is a powerful type of logic placement and routing constraint. You can define any arbitrary region of physical resources on the ta...

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## 7.3.1. The Logic Lock Regions Window Use the Logic Lock Regions window GUI to view, define, and modify the attributes of Logic Lock regions in your project. UG-20133 | 2026.01.07 Figure 113. L...

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## 7.3.2. Defining Logic Lock Regions The Quartus Prime provides multiple entry points in the GUI to create and modify Logic Lock constraints as appropriate in your workflow. - Before Analysis &...

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## 7.3.2.1. Defining a Logic Lock Region in Chip Planner The Chip Planner allows you to easily see Logic Lock region locations and properties in relation to other resources in the device. Before Ana...

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## Figure 115. Create Logic Lock Region Button on Toolbar 5. To define the region dimensions and location, click and drag the cursor on the Chip Planner floorplan to draw a region of your preferred l...

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## 7.3.2.1.1. Logic Lock Region Properties You can view and modify the following properties for the Logic Lock regions that you define. You can access these properties using either of these methods: ...

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## 7.3.2.1.2. Snapping to a Region When placing Logic Lock regions in the Chip Planner by hand, Chip Planner is set to snap the placement of the region to adjacent LAB boundaries by default. This mea...

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## 7.3.2.1.3. Considerations for Auto Sized Regions If you use Auto/Floating Size/State Logic Lock regions, consider the following limitations and effects: - Auto/Floating regions cannot be rese...

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## 7.3.2.2. Defining a Logic Lock Region from the Project Navigator After you run Analysis & Elaboration or the Fitter, you can assign the member nodes to the Logic Lock region. The Project Navig...

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## 7.3.2.3. Defining Routing Regions A routing region is an element of a Logic Lock region that specifies the routing area. A routing region must encompass the existing Logic Lock placement region. R...

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## Table 50. Routing Region Options | Option | Description ...

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## 7.3.2.4. Defining Empty Logic Lock Regions The Quartus Prime supports the use of Logic Lock regions without any members. You can use such empty regions to reserve device resources to contain logic...

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## Figure 122. All Logic Placed Outside an Empty region The figure shows an empty Logic Lock region and the logic placed around it. However, some I/Os, HSSIO, and PLLs are present in the empty region...

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## 7.3.2.5. Defining Hierarchical Logic Lock Regions Logic Lock regions can be fully hierarchical. Parent regions must completely contain all child regions. The Reserved and Core-Only assignments als...

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## 7.3.3. Customizing the Shape of Logic Lock Regions To create custom shaped Logic Lock regions, you can perform logic operations. Nonrectangular Logic Lock regions can help you exclude certain reso...

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## Logic Lock Regions Properties Dialog Box Use the Logic Lock Regions Properties dialog box to view and modify detailed information about your Logic Lock region, such as which entities and nodes are...

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## 7.3.3.1. Adding a New Shape to a Logic Lock Region To add a new shape to an existing Logic Lock region, perform the following steps in the Chip Planner: 1. Select the Logic Lock region. 2. In the...

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## Figure 123. Add Logic Lock Region Button in Toolbar 3. Click and drag to generate the shape you want to add. The new shape merges automatically with the selected Logic Lock region. Attention: If ...

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## 7.3.3.2. Subtracting Shape from Logic Lock Region To subtract a shape from an existing Logic Lock region, perform the following steps in the Chip Planner: UG-20133 | 2026.01.07 1. Select the...

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## Figure 125. Subtract Logic Lock Region Toolbar Button 3. Click and drag the shape you want to subtract. The modified region displays automatically. The operation performs in all selected regions....

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## 7.3.3.3. Merging Logic Lock Regions To merge two or more Logic Lock regions, perform the following steps: 1. Ensure that no more than one of the regions that you intend to merge has logic assignm...

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## 7.3.3.4. Defining Noncontiguous Logic Lock Regions You can create disjointed regions by using the Logic Lock region manipulation tools. Noncontiguous regions act as a single Logic Lock region for ...

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## 7.3.4. Assigning Device Pins to Logic Lock Regions A Logic Lock region incorporates all device resources within its boundaries, including memory and pins. The Quartus Prime Pro Edition software do...

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## 7.3.5. Viewing Connections Between Logic Lock Regions in Chip Planner You can view and edit Logic Lock regions using the Chip Planner. To view and edit Logic Lock regions, use Floorplan Editing in...

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## 7.3.6. Example: Placement Best Practices for Arria 10 FPGAs For more information about the Inter-region Bundles dialog box, refer to Quartus Prime Help. Logic Lock regions must take into account...

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## Figure 129. I/O Columns in Arria 10 FPGAs Arria 10 FPGAs have I/O columns located in the middle of the device. Signals can only enter or exit these columns from the side that faces the device edge...

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## Figure 131. Strategic Placement for Logic Lock Regions in Arria 10 FPGAs - If a Logic Lock region contains a register that interface with the I/O column, place the Logic Lock region so that the re...

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## 7.3.7. Migrating Assignments between Quartus Prime Standard Edition and Quartus Prime Pro Edition The Quartus Prime Pro Edition software does not support the Quartus Prime Standard Edition Logic L...

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## 7.4. Defining Virtual Pins Replace Logic Lock Regions In Quartus Prime Pro Edition User Guide: Getting Started A virtual pin is an I/O element that the Compiler temporarily maps to a logic elem...

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## 7.5. Using Logic Lock Regions in Combination with Design Partitions Assigning Virtual Pins with a Tcl command on page 215 You can optimize timing in a design by placing entities that share signi...

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## 7.5.1. Viewing Design Connectivity and Hierarchy - Quartus Prime Pro Edition User Guide: Block-Based Design - Quartus Prime Pro Edition User Guide: Partial Reconfiguration By default, when you o...

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## 7.6. Creating Clock Region Assignments in Chip Planner You can easily create and manipulate clock regions in the Chip Planner and make clock assignments to the regions. You can create a user-...

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## Summary of User-Defined Clock Region Feature Support | Feature | Clock Region Support ...

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## Using Clock Region Assignments in Stratix 10 and Agilex FPGA Portfolio Devices You can constrain clock regions to a rectangle whose dimensions are defined by the sector grid, as seen in the Clock ...

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## 7.6.1. Creating Clock Assignments in Chip Planner To create clock assignments with the Chip Planner, follow these steps: 1. Select the Create Clock Assignment button, or click View ➤ Clock Assign...

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## 7.6.1.1. Clock Assignment Properties The Clock Assignment Properties pane displays properties of the selected clock assignment. By default, the Clock Assignment Properties pane appears on a tab a...

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## 7.6.2. Resizing a Clock Assignment in Chip Planner To resize an existing clock assignment in the Chip Planner, follow these steps: Figure 140. Clock Assignment in Chip Planner 1. Select an exi...

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## 7.6.3. Moving a Clock Assignment in Chip Planner To move a clock assignment in the Chip Planner, follow these steps: 1. Select the clock assignment in the Chip Planner floorplan. 2. Position the ...

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## 7.6.4. Deleting a Clock Region Assignment in Chip Planner To delete a clock region assignment in the Chip Planner, follow these steps: 1. Select the clock assignment that you want to delete in th...

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## 7.6.5. Assigning a Clock Signal to a Clock Region in Chip Planner To assign a clock signal to a clock region in the Chip Planner, follow these steps: 1. Right-click the clock assignment title bar...

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## Related Information You can run the commands and specify the settings described in this chapter as part of a Tcl script. You can also run some commands at a command prompt. The following topics de...

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## Create or Modify a Placement Region The Quartus Prime software supports Tcl commands to create or modify Logic Lock assignments. Note: Specify node names by using the full hierarchy path to the ...

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## Create or Modify a Routing Region The following assignment creates a routing region with bounding box coordinates X5 Y5 X30 Y30 : set\_instance\_assignment -name ROUTE\_REGION -to <node names&...

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## Specify a Region as Reserved The following assignment reserves an existing region: set\_instance\_assignment -name <instance name> RESERVE\_PLACE\_REGION -to <node names> ON - You ca...

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## Specify a Region as Core Only By default, the Quartus Prime Pro Edition software includes pins in Logic Lock assignments. To specify a region as core only (that is, periphery logic in the instance...

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## Related Information Defining Logic Lock Regions on page 191 Use the following Tcl command to turn on the virtual pin setting for a pin called my\_pin : ``` set_instance_assignment -name VIRTUAL...

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## 7.7.3. Logic Lock Region Assignment Examples The following examples show the syntax of Logic Lock region assignments in the .qsf file. Optionally, you can enter these assignments in the Assignment...

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## Example 1. Assign Rectangular Logic Lock Region Assigns a rectangular Logic Lock region to a lower left corner location of (10,10), and an upper right corner of (20,20) inclusive. ``` set_instanc...

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## Example 2. Assign Non-Rectangular Logic Lock Region Assigns instance with full hierarchical path " x|y|z " to non-rectangular L-shaped Logic Lock region. The software treats each set of four numbe...

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## Example 3. Assign Subordinate Logic Lock Instances By default, the Quartus Prime software constrains every child instance to the Logic Lock region of its parent. Any constraint to a child instance...

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## Example 4. Assign Multiple Logic Lock Instances By default, a Logic Lock region constraint allows logic from other instances to share the same region. These assignments place instance c and instan...

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## Example 5. Assigned Reserved Logic Lock Regions Optionally reserve an entire Logic Lock region for one instance and any of its subordinate instances. ``` set_instance_assignment -name PLACE_REGIO...

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## Table 51. Document Revision History The following revision history applies to this chapter: | Document Version | Quartus Prime Version | Changes ...

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## Table 51. Document Revision History | Document Version | Quartus Prime Version | Changes ...

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## Table 51. Document Revision History • Added new Find In Options topic. ...

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## Table 51. Document Revision History ...

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## Table 51. Document Revision History | Document Version | Quartus Prime Version | Changes ...

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## Table 51. Document Revision History ...

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## Table 51. Document Revision History | Document Version | Quartus Prime Version | Changes ...

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## 8. Using the ECO Compilation Flow In a typical FPGA project development cycle, the specification of the programmable logic portion of the design can change during the design process. The Quartus P...

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## 8.1. ECO Compilation Flow 1. Identify an ECO modification you want to make in a compiled design. 2. Determine if ECO commands support the change, by reviewing ECO Commands on page 223 and ECO Comm...

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## 8.3. Viewing ECO Compilation Reports The following shows an example ECO Tcl script that places existing nodes in new locations: Figure 142. ECO Tcl Script Example The Compiler generates...

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## 8.4. ECO Commands The Quartus Prime Pro Edition software supports the following ECO commands: Note: Check available arguments by running <eco\_command> -h|help|long\_help . ECO Command Qu...

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## 8.4.1. ECO Command Quick Reference Table 52. ECO Command Quick Reference | ECO Change | ECO Commands ...

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## Description Connects the source signal to the destination block port. If the port has an existing connection, the command removes the previous connection and connects it to the signal you specify....

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## Options tieoff To explicitly tie off an input port to VCC or GND . VCC or GND Example: make\_connection -tieoff VCC -to {node1} -port DATAA - to Name of the destination block. port The input por...

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## Description Disconnects the src signal from the destination block port. The actual routing change occurs implicitly. You can locate node names by right-clicking a node in Netlist Viewer, and then ...

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## Description Modifies the lutmask of the matching destination node, with the lutmask value ( -mask ) in binary or hexadecimal, or with the equivalent lutmask value ( -eqn ) computed from specified ...

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## Usage The following example disconnects top|a\_out from the D input port of node top|x , and set top|x:D to a disconnected state. ``` modify_lutmask -to top|lut_c -eqn {a&b&c} modify_lutmask -to ...

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## Arguments ``` eqn The logical equation of the inputs ( A, B, C, D, E, F ). The supported lexical tokens include AND('&') , OR('|') , XOR('^') , NOT('!') , OPEN_BRACE('(') , CLOSE_BRACE(')') . Spec...

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## Description Changes the IOPLL frequencies by modifying the input reference clock frequency. The following stipulations apply: - Maintain the original refclk and outclk ratios. - The IOPLLs you ch...

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## Arguments UG-20133 | 2026.01.07 The following example adjusts the *pll\_main* IOPLL by modifying the input clock frequency to 100 MHz. ``` adjust_pll_refclk -to {*pll_main*} -refclk 100 ``` t...

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## Description Implements the I/O pin slew setting rate that you specify for the I/O pin. ``` modify_io_slew_rate 1 -to top|ipin ``` to Instance name of destination pin that you want to modify. ...

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## Description ``` modify_io_current_strength 3mA -to top|ipin ``` to Instance name of the destination pin that you want to modify. Implements the change to the delay chain settings that you spec...

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## Arguments ``` modify_io_delay_chain 3 -to top|ipin -type input ``` ``` type Specifies one of the following I/O types: input , output , oe , io_12_lane_input , io_12_lane_input_strobe ``` ...

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## Description Creates a LUT cell or flip-flop in the design netlist. The following use cases apply: - Adding a gate to fix a logic bug. - Adding a wire LUT to help add hold delay. - Creates a new f...

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## Usage The following example creates a new\_lut LUT node with input ports DATAA and DATAB , and with outputs connected accordingly. modify\_lutmask the modifies the lutmask to perform A&B logic...

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## 8. Using the ECO Compilation Flow UG-20133 | 2026.01.07 To connect to a new flip-flop node that you create, use the make\_connection command to connect to the flip-flop data port ( D ), and con...

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## Usage name Name of the new LUT of flip-flop node. Removes a LUT cell or flip-flop from the design netlist. The following example deletes a flip-flop node with the name ff1 : ``` remove_node -...

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## Description name Name of the LUT of flip-flop node to delete. Places the node that you specify in a location that the ECO Fitter selects. Optionally, you can specify the location argument to ass...

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## Usage The following examples show three placement cases. For node1 , the ECO Fitter determines the placement location. For node2 , the command specifies the exact LAB location constraint. For node...

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## Description name Name of the node. $$location Device region coordinates (X1 Y1 X10 Y10)(X1 Y1) (FF_X20_Y60_N17) .$$ Unplaces the node that you specify. unplace\_node supports moving larger clou...

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## Description The following example unplaces a node with the name ff1 : name Name of the node to unplace. Creates and inserts a wire LUT node in the connection that you specify. The ECO Fitter...

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## Usage The following example creates the my\_wirelut wire LUT, connects my\_wirelut output to the D input port of dest\_node , and connects the output of src\_output to the input port of the wire L...

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## Arguments name Name of the node. From Source of the connection. To Name of destination node. Port Input port name of destination node. location Device region coordinates ( X1 Y1 X10 Y10 ) ...

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## 8.5. ECO Command Limitations The ECO commands have the following limitations due to connection dependencies within Altera devices. - You cannot use ECO commands to modify dedicated connections. -...

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## Create a new LUT in an exact location ``` set lut_name new_lut create_new_node -name $lut_name -type lut make_connection -from input1 -to $lut_name -port DATAA make_connection -from input2 -to $lu...

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## Create a new Flipflop in an exact location ``` set ff_name new_ff create_new_node -name $ff_name -type ff make_connection -from input1 -to $ff_name -port DATAA make_connection -from input2 -to $ff...

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## 8.6. Interactive ECO Fitting The quartus\_fit executable supports ECO changes in an interactive shell through quartus\_fit -s . In an interactive context, the ECO Fitter legalizes the changes, wh...

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## Usage - eco\_load\_design -loads the final netlist in the ECO context. - eco\_commit\_design -commits the ECO modified netlist to disk while running in interactive mode. UG-20133 | 2026.01.07 ...

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## Table 53. Document Revision History The following revision history applies to this chapter: | Document Version | Quartus Prime Version | Changes ...

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## 9. Quartus Prime Pro Edition Design Optimization User Guide Archives For the latest and previous versions of this user guide, refer to Quartus Prime Pro Edition User Guide: Design Optimization. If...

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## Related Information Refer to the following user guides for comprehensive information on all phases of the Quartus Prime Pro Edition FPGA design flow. - Quartus Prime Pro Edition User Guide: Gett...

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## · Quartus Prime Pro Edition User Guide: Partial Reconfiguration Describes Partial Reconfiguration, an advanced design flow that allows you to reconfigure a portion of the FPGA dynamically, while t...

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## · Quartus Prime Pro Edition User Guide: Third-party Simulation Describes RTL- and gate-level design simulation support for third-party simulation tools by Aldec*, Cadence*, Siemens EDA, and Synops...

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## · Quartus Prime Pro Edition User Guide: Third-party Synthesis tools by Siemens EDA, and Synopsys. Includes design flow steps, generated file descriptions, and synthesis guidelines. Describes supp...

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## · Quartus Prime Pro Edition User Guide: Power Analysis and Optimization - Describes the Quartus Prime Pro Edition Power Analysis tools that allow accurate estimation of device power consumption. E...

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## · Quartus Prime Pro Edition User Guide: Design Constraints Describes timing and logic constraints that influence how the Compiler implements your design, such as pin assignments, device options, l...

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## · Quartus Prime Pro Edition User Guide: Scripting and Cadence*. Also includes information about signal integrity analysis and Describes support for optional third-party PCB design tools by Siemen...